Flux Feedback Firing Control for a Load Commutated Inverter

Reference is made to a microfiche appendix which sets forth a computer program listing including that which is applicable to the present invention. Included are 8 microfiche containing a total of 458 frames.

This application is related to U.S. Ser. No. 300,200 entitled, "Line to Line Voltage Reconstruction For Synchronizing Thyristor Power Converter", filed on Sept. 8, 1981 in the names of Paul M. Espelage, et al. This application is assigned to the assignee of the present invention and is herein meant to be incorporated by reference

The present invention relates generally to firing circuits for thyristor power conversion systems and more particularly to an improvement for controlling the commutation of a load commutated inverter which supplies a synchronous machine from a polyphase alternating current source.

Many circuits and systems are known for controlling the conductivity of controlled rectifiers utilized in various types of converters for supplying electrical power to a load such as an AC motor, from a polyphase alternating current (AC) source. The type of rectifier used will, of course, control to some degree the type of control utilized, but by far the most common control rectifier used today is a thyristor of the silicon controlled rectifier type which becomes conductive with the simultaneous application of a forward bias voltage and a signal applied to its gate electrode and which thereafter remains conductive until the anode current falls below the value required to hold the thyristor in the conductive state.

With respect to the load commutated inverter for a three phase (3.phi.) AC motor drive, control of the inverter supplying the synchronous motor is normally based upon a thyristor firing strategy of firing the thyristor as late as possible. To "fire as late as possible" is to render the thyristors conductive at the commutation limit point; i.e., at a power factor angle just sufficiently leading to provide the volt-seconds necessary to safely commutate the current from one thyristor to the other. It is to this aspect that the present invention is directed.

It should also be pointed out that whereas motor control systems employing thyristors have been implemented using analog control techniques, a typical example being U.S. No. 4,230,979, entitled, "Control Current Inverter And Motor Control System," Paul M. Espelage, et al., which issued on Oct. 28, 1980, attention has been and is presently being directed to digital type of control techniques, examples of which are disclosed in: U.S. Pat. No. 3,601,674, "Control System For Firing SCR's In Power Conversion Apparatus", John A. Joslyn, et al., which issued on Aug. 24, 1971; U.S. Pat. No. 4,263,557, "Power Converter Control", Willard B. Jarvinen, which issued on Apr. 21, 1981; and U.S. Pat. No. 4,276,505, "Microcomputer-Based Control Apparatus For a Load-Commutated Inverter Synchronous Machine Drive System", Bimal K. Bose, which issued on June 30, 1981. The teachings of these patents are also intended to be incorporated herein by reference.

In any phase control system, whether it be an analog or digital type system, the AC terminal voltage is a prime feedback signal employed for the thyristor bridge control. Typically, the AC terminal or phase voltages, referred to a fictitious neutral, are coupled from the high voltage thyristor bridge through a high impedance resistor attenuator string into differential amplifiers in the control circuitry and to other related circuitry to further derive various signals for a variety of purposes such as thyristor state detectors and voltage regulation. The principal use of the terminal voltage, however, is in a phase lock loop firing control circuit wherein synchronizing signals are generated from processed line voltages, typically involving integration of the AC line to line voltages. In such applications, the zero voltage commutation notches appearing in the line-to-line voltages generate flat spots in the integrated output voltage with the positioning of the notches being dependent upon the actual firing angle and the duration of the notches being dependent upon the line current and the inductive reactance in the commutation path. Typically, the zero crossings of the integrated line to line voltages are determined by comparators which are utilized to form a synchronizing pulse train at six times line frequency. Since the aforementioned flat spots can occur at the zero crossings, the stability of the phase lock loop can be undesirably affected. To overcome this deleterious effect, the above cross referenced application, U.S. Ser. No. 300,200 entitled, "Line to Line Voltage Reconstruction For Synchronizing Thyristor Power Converter", discloses an improved technique for removing the commutation notches by summing the integrated output of the corrupted line to line voltage with a signal proportional to the commutating inductance multiplied by the fictitious "delta" current which is derived by taking the difference between the actual line currents in a manner well known to those skilled in the art. The resultant or composite voltages are the primary feedback control signals for synchronizing either a fixed frequency source side converter or a variable frequency load side converter or both.

It is therefore an object of the present invention to provide an improved system for controlling a polyphase power converter.

It is a further object to provide an improved system for controlling commutation of a polyphase power converter.

It is still a further object of the present invention to provide an improved system for controlling the commutation of a load side converter powering a synchronous motor.

It is still another object to provide an improved system for commutating a load commutated inverter for maximizing the torque of an AC motor for a given current.

It is a further object to control a synchronous machine without requiring a position sensor for the machine rotor.

The foregoing and other objects are achieved by a control system primarily for a polyphase load side power converter or inverter utilized to power an AC motor load. The inverter is self commutated above a predetermined motor speed. Control of the commutation of current from one inverter thyristor to another is determined by the amplitude of motor pseudo flux waves which comprises the integral of the line to line voltages between the inverter and the motor load. In the self-commutating mode of operation, a firing strategy is implemented based on the premise that the thyristors should be fired at late as possible while still providing enough time to permit commutation to be completed and yet not sooner than necessary to avoid loss of torque. In the subject invention an optimum firing point is achieved by firing each inverter thyristor prior to the peak of the next pseudo flux wave, which point defines an amount of volt-seconds necessary to effect commutation in view of the load commutating impedance and load current present plus a nominal safety margin. The peak of the forthcoming flux wave is determined from the magnitude of the most recent peak or an average of a selected number of previous consecutive peak values. This determination and firing control is implemented preferably in sofeware, but can, when desirable, be implemented in hardware.

While the present invention is described in particularly in the claims annexed to and forming a part of this specification, a better understanding of the invention can be had by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a major block diagram illustrative of an AC motor drive system incorporating the present invention;

FIG. 2 is a simplified block diagram illustrative of circuitry for generating one of six integrated line to line voltages used for commutation of the inverter powering the AC motor shown in FIG. 1;

FIG. 3 is a set of time related waveforms helpful in understanding the operation of the subject invention;

FIG. 4 is an electrical block diagram illustrative of an analog embodiment of the subject invention;

FIG. 5 is a set of time related waveforms illustrative of the commutation provided by the subject invention;

FIG. 6 is an electrical block diagram illustrative of a digital embodiment of the subject invention; and

FIGS. 7A and 7B comprise a flow chart illustrative of the software for implementing commutation of a load commutated inverter with the embodiment shown in FIG. 6.

Considering the overall operation of an AC motor drive system including the invention, reference is now made first to FIG. 1 which illustrates in major block diagram form a system for controlling a load 10, comprising a synchronous motor from a three phase (3.phi.) power source coupled to line terminals L.sub.1, L.sub.2, L.sub.3 in accordance with the operation of a source side converter 12 and a load side converter 14. The source side converter 12 operates to convert the three phase AC power into a source of variable direct current (DC) which is coupled by way of a DC link circuit 16 including an inductor 18 to the load side converter 14, hereinafter referred to as the inverter, which in turn operates to generates an AC current of variable magnitude and frequency which is supplied to the motor 10 by means of the three phase lines L.sub.a, L.sub.b and L.sub.c. These basic power components are set forth in greater detail in the aforementioned Bose patent U.S. Pat. No. 4,276,505.

Both the source side converter 12 and the load side inverter 14 are implemented by means of well known phase controlled thyristor bridge circuits, as basically illustrated, whose conductivity is controlled by means of respective phase-lock loop (PLL) firing control circuits 18 and 20. The firing angles of the thristors in the converter 12 are primarily controlled by the output of a current regulator 22 while the firing angles of the thyristors in the inverter 14 are primarily controlled by the output of a load angle regulator 24. A typical example of the manner in which the torque command signal is generated is shown and described in U.S. Pat. No. 4,230,979 entitled, "Controlled Current Inverter and Motor Control System", issued in Paul M. Espelage, et al. on Oct. 28, 1980.

The firing of the thyristors included in the converter 12 and the inverter 14, moreover, is synchronized with respect to the three phase voltages on lines L.sub.1, L.sub.2 and L.sub.3 and L.sub.a, L.sub.b and L.sub.c utilizing a waveform comprising the integration of the AC line to line voltage, the zero crossings of which are used to form a synchronizing pulse train having a frequency six times the fundamental frequency. A preferred form of apparatus utilized for implementing the integration of the line to line voltages is designated by the units 26 and 28 and comprises circuitry shown and described in the above cross referenced application, U.S. Ser. No. 300,200 entitled, "Line to Line Voltage Reconstruction For Synchronizing Thyristor Power Converter". Such circuitry operates to reconstruct the line to line voltage waveforms which become corrupted by the commutation notches appearing in the waveforms of the phase voltages during the time each phase current transfers from an outgoing phase to an oncoming phase by the appropriate firing of the individual thyristors. The line to line voltage reconstruction preferred by the subject invention consists of a composite waveform developed by summing at least one integrated line to line voltage containing commutation notches with a signal corresponding to at least one "delta" current which is derived from the difference of two phase currents and multiplied by a factor representative of the commutation inductance.

Referring now to FIG. 2, there is shown in its simplest form, the manner in which one of the above mentioned reconstructed waves is generated. There, v.sub.a and v.sub.b represent two of the three phase voltages v.sub.a, v.sub.b and v.sub.c which are referenced to neutral while i.sub.a and i.sub.b represent the two line currents for the phases a and b. A line to line voltage v.sub.ab is developed by differencing the phase voltages v.sub.a and v.sub.b at a summing junction 30 while a "delta" current i.sub.ab is developed by differencing the line currents i.sub.a and i.sub.b in a summing junction 32. The line to line voltage v.sub.ab is fed to a signal integrator 34 whose output corresponds to a pseudo flux wave .psi..sub.ab. This flux wave is applied to a summing junction 35 along with a signal Ki.sub.ab which corresponds to the delta current i.sub.ab which has been appropriately scaled by the commutation inductance L.sub.c. The output of the summing junction 35 comprises the waveform .psi.'.sub.ab =.psi..sub.ab +Ki.sub.ab and consists of a generally sinusoidal waveform having well defined zero crossings notwithstanding the occurrence of commutation notches in the phase voltages v.sub.a, v.sub.b and v.sub.c. By connecting a zero crossing detector circuit 38 to the summing junction 35, one of a set of synchronizing signals can be generated for operating either of the phase lock loops 18 and 20 (FIG. 1) which are preferably of the digital type, typical examples of which are shown and described in the above referenced U.S. Pat. No. 4,263,557 "Power Converter Control", by W. B. Jarvinen, as well as in U.S. Pat. No. 4,090,116, "Closed Loop Digital Control System and Method for Motor Control" by D. L. Lippitt, issued May 16, 1978, and U.S. Pat. No. 4,201,936, "Motor Speed Regulator and Control System" by P. J. Roumanis, issued May 6, 1980.

Referring now to FIGS. 3 and 5, in a load commutated inverter system the motor load 10 is normally operating as a motor as opposed to a generator and the load side converter 14 is operating in the inverting mode, hence the name inverter. Under such conditions, the inverter thyristors are fired between the angles .alpha.=90.degree. and .alpha.=180.degree. where .alpha.=0 is defined with respect to one thyristor in FIGS. 3 and 5 by the crossings of the line to neutral voltages v.sub.a and v.sub.c. If the inverter firing occurs at .alpha.=180.degree., the motor 10 would be operating at unity or slightly lagging power factor; however, in a self-commutation mode, the inverter is operated at a leading power factor to provide the leading KVAR necessary for commutation. In order to obtain maximum torque for a given motor current, however, and still provide commutation capability, it becomes desirable to minimize the leading KVAR to that just sufficient to insure reliable commutation. Typically, the firing angle of the inverter 14 is in the region of .alpha.=150.degree. to 160.degree. to insure that the commutation is completed prior to the subsequent intersection of the waveforms v.sub.a and v.sub.c but preferably about 15.degree. prior to this intersection to provide adequate commutation margin. Having noted that synchronization of both the load side converter 12 and the source side inverter 14 can be effected by use of integrated line to line source and load voltages, after modification by the voltage reconstruction units 26 and 28 shown in FIG. 1, these units provide pseudo flux output waveforms .psi.'.sub.ab, .psi.'.sub.bc and .psi.'.sub.ca which are shown by the waveform set B of FIG. 3. While these waveforms are in timed relationship with the waveform set A, it should be noted that the respective crossover points of the line to neutral voltages v.sub.a, v.sub.b and v.sub.c intersect at a time where either a positive or negative flux wave peak occurs and wherein .alpha.=180.degree. for a particular thyristor cell of six cell firing group arranged in a bridge circuit, not shown. It is also significant to note that the flux waves .psi.'.sub.ab, .psi.'.sub.bc and .psi.'.sub.ca are defined in units of volt-seconds, which units correspond to those required to commutate a current through an inductance as determined by the equation:

from which there is obtained the expression:

wherein E is the source voltage, .DELTA.t is the commutation time, L is the commutation inductance and .DELTA.i is the current being commutated.

The present invention is directed to means for particularly determining the appropriate firing angle for the thyristors of the inverter 14 during self commutation from the peak value of the respective previous flux wave. Then by knowing the motor current and commutating impedance, the necessary volt-seconds necessary for commutation are determined and subtracted from this peak value after which, when the actual plus or minus amplitude of appropriate flux wave reaches this amplitude, the next cell firing is initiated. Alternatively, an average of a selected number of consecutive peak values of flux waves are determined from which the necessary volt-seconds are subtracted to determine the appropriate point for the next cell firing.

Referring now to FIG. 4, there is disclosed an analog embodiment of a circuit for implementing this type of commutation control. As shown, six pseudo flux waves -.psi.'.sub.ca, -.psi.'.sub.ab . . . .psi.'.sub.ab and .psi.'.sub.bc which are derived from circuits as shown in FIG. 2 are respectively fed to the non-inverting inputs of six signal comparators 42, 44, 46, 48, 50 and 52. The comparators have their respective inverted inputs commonly connected to signal line 54 which connects to the output of a clamp or limiter circuit 56 which receives an input signal on signal line 58 and which corresponds to the desired firing angle command signal .angle.* from the load angle regulator 24 as shown in FIG. 1. The maximum output of the limiter circuit 56 provides either a retard limit command or an advance limit command for firing the inverter thyristors by the output of the comparators 42 . . . 52. The peak flux wave amplitude .psi..sub.max is determined by means of a three phase rectifier 60 coupled to the six lines 62 of the flux waves which is also fed to a peak detector circuit 64. The output of the three phase rectifier 60 is fed to a sample and hold circuit 66 which is triggered by a peak signal TP whereupon the peak flux wave value .psi..sub.max is applied to the scaling circuit 68 which provides a multiplication factor of approximately 0.97 to define the advance limit command as being 0.97 times the peak flux wave .psi..sub.max. The output line 70 of the sample and hold circuit is also coupled to summing junction 72 which has applied thereto a scaled value of the motor current I.sub.dc obtained, for example, from the current sensor 19 in the DC link circuit 16 shown in FIG. 1. A scaling circuit 76 is adapted to multiply the line current I.sub.dc by a factor K proportional to the commutating inductance L.sub.c, which is subtracted from the peak flux signal appearing on line 70 by being applied to a subtracting input (-) of the summing junction 72. In addition, another term proportional to a desired safety margin applied from circuit block 78 is subtracted from the peak flux value .psi..sub.max by being applied to a subtracting input (-) of the summing junction 72. The resultant signal output from the summing junction 72 corresponds to a signal .psi..sub.max -KI.sub.dc -MARGIN which comprises the retard limit signal for the next cell firing. Accordingly, when the flux wave amplitudes successively exceed the angle command signal from the advance/retard limit circuit 56, the appropriate next thyristor is gated on by means of the comparators 42, 44, 46, etc. while the gate enable is removed from the appropriate previously conducting thyristor.

This operation can be understood with reference to the waveforms of FIG. 5 wherein, for example, the waveform set A is illustrative of the time relationship of the three line to neutral voltages v.sub.a, v.sub.b and v.sub.c. Also illustrated are two 180.degree. time periods for the firing angles .alpha. for cells 1 and 3 with the commutation process of cells 5 to 1 and 1 to 3 being shown by reference numerals 84 and 86. The waveforms of set B are indicative of the thyristor currents in thyristors 1 and 3. The waveform of set C of FIG. 5 is illustrative of the two line to line voltages v.sub.ac and v.sub.ba while the single waveform D is illustrative of the integrated waveform of v.sub.ba which corresponds to the flux wave .psi..sub.ba. It can be seen that waveform D lags the waveform v.sub.ba by 90.degree. and accordingly the peak of the waveform D which corresponds to the time TP occurs at the crossover of the line to neutral voltages v.sub.b and v.sub.c. The amplitude as indicated by reference numeral 88 of waveform D of FIG. 5 illustrates the retard firing limit which is comprised of the KI.sub.dc term 90 and the margin 92. Thus in normal operation, the firing angle command is at the retard limit except in instances where motor deceleration is occurring or when the inverter 14 is being phased forward for some other control purpose.

While the circuitry shown in FIG. 4 discloses an implementation of the subject invention in analog form, FIG. 6 discloses a digital implementation thereof which includes an Intel 8086 microprocessor 94 programmed in PLM 86 language having self contained interrupt programs under the control of an Intel 8259 interrupt controller 96. The controller 96 generates interrupts in a well known fashion which causes the microprocessor 94 to execute some task or calculation and typically store the time to execute some future event into a downcounter. When the down counting reaches zero, the counters generate another interrupt which initiates the event, after which the counter is reloaded for the time to execute the next event.

With respect to FIG. 6 a software phase locked loop configuration is shown wherein four counters are utilized, namely a phase lock loop counter 98, a time counter 100, a fire counter 102 and the pulse train limit counter 104. In operation, a variable frequency source is created by the phase lock loop counter 98 by dividing a 4.9152 MHz output pulse train from a clock oscillator 106 by a value N set by a signal "PRESET N" from the microprocessor 94 on a data bus 108. The output of the counter 98 is adapted to be maintained at a frequency 512 times the frequency of the individual flux waves -.psi.'.sub.ca . . . .psi.'.sub.bc in the following manner. The time counter 100 is initially set to 512 and decremented by one each clock pulse from counter 98. When counter 100 is decremented to zero it resets to 512. Thus counter 100 gives a measure of phase angle relative to the flux waveforms. The count value in the time counter 100 is fed to the microprocessor 94 via data bus 101 where it is used for phase reference for firing the inverter cells, not shown, through a digital I/O port 110. Synchronization is first achieved by passing the pseudo flux waveforms -.psi.'.sub.ca . . . .psi.'.sub.bc through a zero crossing detector circuit 112 which generates a synchronizing pulse every time a flux wave passes through zero. These pulses are fed to the interrupt controller 96 on signal line 97 which interrupts the microprocessor 94 and initiates a crossover service program. The zero crossing detector 112 also generates a three bit number indicating the relative signs of the motor flux waveforms, which number is fed to and read by the microprocessor 94 and is used to identify which zero crossing has caused the interrupt pulse. The zero crossover service program reads the value in the time counter 100 and compares it to the correct value for the particular flux wave crossing to generate a phase error between the counter 100 and the flux waves. This error is used to calculate a new "PRESET N" value which is then loaded into the phase lock loop counter 98.

As shown by the waveforms A and B of FIG. 3, the peak values of the flux waveforms .psi.'.sub.ca, .psi.'.sub.ab and .psi.'.sub.bc occur at an interval of 30.degree. following zero crossings of the line to neutral phase voltages v.sub.a, v.sub.b and v.sub.c. The zero crossover interrupt also initiates the countdown of the pulse train limit counter 104 which had been set with 30.degree. of count. When counter 104 decrements to zero, it causes an interrupt to occur which is at the time the next flux wave peak .psi..sub.max value occurs. Thus the pulse train limit interrupt program reads the peak value of the appropriate flux wave appearing at the output of a multiplexed analog to digital converter 114 whose input is coupled to three flux waves -.psi.'.sub.ca . . . .psi.'.sub.bc.

The timing of the firing of each thyristor cell in the inverter 14 is accomplished by means of the fire counter 102. After a cell firing, the microprocessor 94 computes the time to fire the next cell. This time is compared to the value in the time counter 100 which corresponds to current time. The difference to "time to go" is then loaded into the fire counter 102 via the data bus 116, which then decrements to zero causing a yet another interrupt through the interrupt controller 96 which initiates a cell firing program.

The software required for the embodiment illustrated in FIG. 6 is represented by the flow chart shown in FIG. 7. As shown, the routine for effecting commutation in accordance with the invention begins by synchronizing the phase lock loop to the zero crossings of the pseudo flux waveforms. Next the software determines the time each pseudo flux waveform is at a peak value, both positive and negative, followed by a measurement of that particular peak value. Next a computation is made of the value IVOLT$MAX which corresponds to the magnitude of the most recent peak or alternatively an average value of a selected number, for example the last six consecutive peak values. Following this, a value VOLT$SEC$MTR is computed where VOLT$SEC$MTR=IVOLT$ MAX-LOAD IMPEDANCE*LINK CURRENT-MARGIN. Once the VOLT$SEC$MTR has been computed, a firing angle .alpha. is computed according to the expression ##EQU1##

Following this computation, a "time to fire" a particular cell is computed from the firing angle .alpha. whereupon the time is compared against the current time in the time counter 100, which time corresponds to the "time to go" (TGO). If the "time to go" is negative, this means that it is already too late to fire and the next thyristor pair is fired immediately. If the "time to go" is too short to allow another regulator calculation, the fire counter is loaded with the "time to go" and the fire counter preset is loaded with the equivalent of 60.degree. of count. By this means the next thyristor pair is fired after the "time to go" count is decremented in the fire counter and then the 60.degree. of count is loaded into the fire counter such that if the next regulator calculation is not completed within 60.degree. the time for firing the next thyristor pair defaults to 60.degree. after the last firing.

If the "time to go" calculated above is long enough to run another regulator calculation, then the fire counter is loaded with some count, "next time", and the fire counter preset is loaded with "time to go-next time". By this means after" next time "decrements to zero another regulator calculation is made to determine a new "time to go". If however this new calculation is not ready the time for firing the next thyrister pair defaults to "time to go-next time".

In order to more fully understand the operation of the microprocessor 94 as it relates to control of the load side inverter 14, the interrupt programs for this microprocessor will be briefly considered. Although some redundancy will result in view of the preceding description, in their descending order of priority, the programs consist of: (1) the fire counter service program, (2) the crossover service program, (3) the pulse train limit service program, (4) the phase lock loop correction program, and (5) the inverter control program.

The fire counter service interrupt program is initiated every time the fire counter 102 times out. The fire counter service interrupt program also checks to see if the inverter is in a self commutation mode. If it is, it sets up the next fire counter load output from the microprocessor for a count of 60.degree. so that barring later information, the next fire counter service interrupt will occur at 60.degree.. The fire counter service interrupt program then checks to see if a new cell firing is to occur during this pass through the program; if so, the cell firing algorithm is called. Then the fire counter service interrupt generates an interrupt to initiate the inverter control interrupt program which is of the lowest lvel of priority.

The second highest priority interrupt program is the crossover interrupt which as previously noted is generated at every zero crossing of the reconstructed flux waves that occur six times per cycle of fundamental frequency and from which are generated the synchronizing signals for the software phase lock loop shown in FIG. 6. The crossover interrupt program, moreover, reads the time counter 100 which is clocked from the phase lock loop counter 98. As already indicated, the clock rate is 512 pulses for fundamental frequency. Thus the fundamental frequency period is divided by 512 giving the time counter an angle resolution of 360.degree. divided by 512, which is equal to 0.703.degree.. The crossover program also reads the pulse train limit counter which started counting down from a count equivalent to 30.degree. when the zero crossing interrupt was generated. This enables a correction of the time counter reading by the amount of time that the higher priority fire service interrupt program may have held off the crossover interrupt program. The crossover program then generates an interrupt calling for the phase lock loop correction interrupt program. The phase lock loop correction program next determines the angular error between the synchronizing crossover interrupt pulses outputted from the zero crossing detector 112 and the actual corrected time counter reading from counter 100 whereupon a new .div.N is loaded into the PLL counter 98 and which operates to nullify this error.

Next the pulse train limit service program, which is third in priority, occurs when the pulse train limit counter 104 decrements to zero. This occurs twice per 60.degree. of fundamental frequency. A first pulse train limit interrupt occurs 30.degree. of fundamental frequency after a flux wave zero crossing. After this interrupt, the pulse train limit interrupt program reloads the pulse train limit counter 104 with 15.degree. of count and starts the pulse train limit counter 104 decrementing. On reaching a zero count, a second pulse train limit interrupt occurs. In accordance with this second pulse train limit interrupt, the pulse train limit counter is reloaded with 30.degree. of fundamental frequency count, but the counter doesn't initiate countdown until the occurrence of the next flux wave zero crossover. The second pulse train limit interrupt which occurs 15.degree. after the first is used to check commutation failure and if so, to initiate an algorithm to recover from this commutation

The fourth highest priority interrupt program is the phase lock loop correction interrupt program and is called once for each crossover interrupt program. The phase lock loop correction interrupt program calculates the value of the divider (.div.N) for the PLL counter 98 to maintain synchronism between the pulse output of the counter and the zero crossings of the flux waves.

The load side inverter control interrupt program is the lowest is priority but contains the bulk of the mode determination, regulator, thyristor firing angle determination functions and accordingly calls the appropriate algorithm. While the inverter control interrupt program is lowest in priority, it is called by the highest priority fire service interrupt program.

Accordingly, the present invention discloses a technique whereby the optimum time to fire the inverter cells in a self commutating adjustable speed synchronous motor drive is determined in a simple but elegant manner by the motor's own back emf from which the pseudo flux waveforms are derived.

While there has been shown and described what are at present considered to be the preferred embodiments of the invention, modifications thereto will readily occur to those skilled in the art. It is not desired, therefore, that the invention be limited to the specific methods and logic structure shown and described, but it is intended to cover all such modifications, changes and alterations as fall within the true spirit and scope of the invention as defined in the appended claims.