Buffer Circuit for Generating Output Signals Having Short Recovery Time

1. Field of the Invention

The present invention relates to a buffer circuit. The buffer circuit of the present invention is used as, for example, an inverter circuit which employs FETs.

In general, in order to reduce the power dissipation in a static memory circuit, the standby mode method is adopted in which zero or only a minimum current flows in portions of the static memory circuit in the standby mode. However, in prior art buffer circuits used in static memory circuits, it is difficult to realize such zero or only a minimum current state since a certain amount of current flows in the buffer circuit which receives a chip-select signal. Examples of such prior art buffer circuits are illustrated in FIGS. 1A through 1D.

2. Description of the Prior Art

The prior art buffer circuit of FIG. 1A comprises a depletion type FET 32 and an enhancement type FET 33. The input signal S.sub.in , such as a chip-selected signal, is supplied to the gate 1 of FET 33 and the output signal S.sub.out is produced at the point 6 at which the source and the gate of FET 32 and the drain of FET 33 are connected.

In the buffer circuit of FIG. 1A, when the input signal S.sub.in is at a high potential, FET 33 is in the ON state, and hence the output signal S.sub.out reaches a low potential. In this state, FET 32 continues to transmit the current, and hence the level of the low potential of the output signal S.sub.out does not decrease to V.sub.ss. Under this condition, if the input signal S.sub.in changes to a low potential, FET 33 turns OFF, and hence the output signal S.sub.out reaches a high potential. Thus, the memory chip related to this buffer circuit is selected to become active. As described above, in the standby mode in which the input signal S.sub.in is at a high potential although the output signal S.sub.out is at a low potential, the current flows through V.sub.cc, FET 32, FET 33 and V.sub.ss with the result that power down, i.e. the reduction of power dissipated, in the standby mode is not achieved.

The prior art buffer circuit of FIG. 1B comprises enhancement type FETs 32 and 33, a capacitor 4 for bootstrap action and a diode connection FET 36.

In the buffer circuit of FIG. 1B, when the input signal S.sub.in is at a high potential, FET 33 is in the ON state, and hence the output signal S.sub.out reaches a low potential. In this state, FET 32 is supplied with a gate potential through FET 36 from the source V.sub.cc and hence does not attain the complete OFF state and, accordingly, the reduction of the level of the low potential of the output signal S.sub.out is limited.

Under this condition, if the input signal S.sub.in changes to a low potential, FET 33 turns OFF, and hence the output signal S.sub.out reaches a high potential. In this operation, high potential is supplied to the gate of FET 32 due to the bootstrap effect of the capacitor 4, and hence FET 32 reaches the complete ON state and, accordingly, the level of the high potential of the output signal S.sub.out attains V.sub.cc. As described above, in the standby mode in which the input signal S.sub.in is at a high potential although the output signal S.sub.out is in the low state, the current flows through V.sub.cc, FET 32, FET 33 and V.sub.ss with the result that power down, i.e. the reduction of power dissipation, in the standby mode is not achieved.

The prior art buffer circuit of FIG. 1C comprises an enhancement type FET 33, the gate of which receives an input signal S.sub.in, and another enhancement type FET 32, the gate of which receives the inverted signal S.sub.in of the signal S.sub.in. In the buffer circuit of FIG. 1C, although the current in the standby mode is made zero, the potential of the output signal S.sub.out is reduced by the amount of V.sub.th, which is the threshold voltage of FET 32, with the result that the desired level of the high potential of the output signal S.sub.out cannot be attained.

The prior art buffer circuit of FIG. 1D comprises FETs 31, 32 and 33, a capacitor 4 and an inverter 51. The input signal S.sub.in is supplied to the source of FET 31 and the input terminal of the inverter 51. The gate of FET 32 is connected to the drain of FET 31 and one electrode of the capacitor 4 while the gate of FET 33 is connected to the output terminal of the inverter 51. In the circuit of FIG. 1D, when the buffer circuit is in the standby mode in which the input signal S.sub.in is at a low potential, FET 32 is in completely in the OFF state, FET 33 is in the ON state, and no current flows through V.sub.cc, FET 32, FET 33 and V.sub.ss, and hence the potential of the low output signal S.sub.out becomes equal to V.sub.ss. The operation is described as follows. When the potential of the input signal S.sub.in is low, the output signal S.sub.51 of the inverter 51 is at a high potential, and hence FET 33 is in the ON state, FET 32 is in the OFF state, the potential of the output signal S.sub.out is at a low level, and accordingly, no current flows through V.sub.cc, FET 32, FET 33 and V.sub.ss . When the potential of the input signal S.sub.in is high, the output signal S.sub.51 of the inverter 51 is at a low potential, and hence FET 33 is in the OFF state, FET 32 is in the ON state, the potential of the output signal S.sub.out becomes equal to V.sub.cc (FIG. 2, (4)) because FET 32 is in the completely ON state due to the bootstrap effect of the capacitor 4. Due to the bootstrap effect, the level of the potential "V.sub.cc -V.sub.th31 " is increased to the higher level of the potential "V.sub.cc +.alpha." (FIG. 2, (2)), where V.sub.th31 is the threshold voltage of FET 31 and .alpha. is the difference between the gate voltage V.sub.g32 of FET 32 and V.sub.cc.

However, in the buffer circuit of FIG. 1D, there is a disadvantage in that the recovering rise of the potential S.sub.out is slow in the case where a short duration pulse P occurs in the input signal S.sub.in at the time t3 and hence the potential S.sub.31 of the gate of FET 32 is lowered, as is illustrated in FIG. 3, which illustrates the operation of the buffer circuit of FIG. 1D. In FIG. 3, (3) and (4), the high level (H.L.) of S.sub.51 and the low level (L.L.) of S.sub.out are indicated by the broken lines.

Such a short duration pulse P may occur in the following cases. For example, in the case where either the fall of the trailing edge of a first input signal of a two-input NAND gate circuit is too late or the rise of the leading edge of a second input signal of the two-input NAND gate circuit is too early. Also, for example, in the case where, as is usual in static memory circuits, the width of the signal pulse is not a predetermined amount in order to achieve simplification of the structure and the operation of the device.

As is illustrated in FIG. 3, when a short duration pulse P occurs in the input signal S.sub.in, the charges on the gate of FET 32 are discharged through FET 31 during the falling portion of the pulse P. In the recovering rise portion of the pulse P, the potential S.sub.51 does not reach the complete high level (FIG. 3, (3)), and hence FET 33 is in either the OFF state or the incomplete ON state, and accordingly, the capacitor 4 is not sufficiently charged. Thus, the bootstrap operation of the capacitor 4 is not satisfactorily carried out and hence the recovering rise portion of the output signal S.sub.out is slow. Also, the potential of the high output signal S.sub.out cannot attain V.sub.cc. Accordingly, the operation of the buffer circuit of FIG. 1D has these disadvantages. Such disadvantages are aggravated in the case where the logical operation of the subsequent circuit receiving the output signal S.sub.out of the buffer circuit is correctly achieved only when the rise of the leading edge of the output signal S.sub.out is quick. In this case, if the rise of the leading edge of the output signal S.sub.out is slow, the subsequent circuit receiving the output signal S.sub.out of the buffer circuit may operate erroneously with the result that correct operation of the static memory circuit using the buffer circuit may not be ensured.

The prior art circuit of FIG. 1D is described in, for example, U.S. Pat. No. 3,774,055.

It is an object of the present invention to provide an improved buffer circuit in which the quick rise of the leading edge of the output signal is ensured, and accordingly, the subsequent logic circuit is prevented from operating erroneously.

In accordance with the present invention, there is provided a buffer circuit comprising a first transistor, the source or the drain of which receives an input signal, a second transistor, the gate of which is connected to the drain or the source of the first transistor, the second transistor being adapted to carry out the bootstrap function, a third transistor which is connected in series with the second transistor, a signal which has the reverse phase of the phase of the input signal and is slightly delayed from the input signal being supplied to the gate of the third transistor, and an inverter connected to the output point at which the second and the third transistors are connected in series, the inverter inverting the potential of the output point and supplying the inverted potential to the gate of the first transistor.

These together with other objects and advantages which will become subsequently apparent reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout.

FIGS. 1A, 1B, 1C and 1D illustrate prior art buffer circuits,

FIGS. 2 and 3 illustrate the operation characteristics of the buffer circuit of FIG. 1D,

FIG. 4 illustrates a buffer circuit in accordance with an embodiment of the present invention,

FIGS. 5 and 6 illustrate the structures of the inverters in the buffer circuit of FIG. 4, and

FIGS. 7 and 8 illustrate the operation characteristics of the buffer circuit of FIG. 4.

A buffer circuit in accordance with an embodiment of the present invention is illustrated in FIG. 4. The circuit of FIG. 4 comprises an input terminal 1, a first FET 31, a second FET 32, a third FET 33, a fourth FET 34, a fifth FET 35, a capacitor 4 for bootstrap effect, a first inverter 51, a second inverter 52, and an output terminal 6.

FET 31, FET 32 and FET 33 are FETs of the enhancement type. When high potential is applied to the gate of FET 33, FET 33 turns ON and hence low potential is produced at the output terminal 6. When low potential is applied to the gate of FET 33, FET 33 turns OFF and hence high potential is produced at the output terminal. At that moment, a high potential is applied to the gate of FET 32 due to the bootstrap effect of the capacitor 4 and FET 32 attains the completely conductive state. Thus high potential of the output signal S.sub.out at the output terminal 6 can attain the potential V.sub.cc.

To the gate of the third FET 33 a signal S.sub.51, which has the reverse phase of the phase of the input signal S.sub.in and is slightly delayed from the input signal S.sub.in, is supplied.

The output signal S.sub.out is applied to the input terminal of the second inverter 52. The output signal S.sub.52 is the inverted signal of the signal S.sub.out. The signal S.sub.52 is applied to the gate of the first FET 31. The fourth FET 34 is connected between the power source V.sub.cc and the gate circuit of the second FET 32. The fourth FET 34 operates to precharge the gate circuit of the second FET 32 when the power supply to the buffer circuit of FIG. 6 is switched on. The fifth FET 35 operates to supply charges to the output terminal 6 in order to prevent the potential of the output terminal 6 from being reduced due to a junction leakage.

The operation of the buffer circuit of FIG. 4 is illustrated in FIGS. 7 and 8. The normal operation of the buffer circuit of FIG. 4 is illustrated in FIG. 7.

The operation of the buffer circuit of FIG. 4 in the case where a short duration pulse P occurs in the input signal S.sub.in is illustrated in FIG. 8. As is illustrated in FIG. 8, even when a short duration pulse P occurs in the input signal S.sub.in at the time t3 (FIG. 8, (1)), the charge at the gate circuit of the second FET 32 is not discharged and the potential of the gate circuit of the second FET 32 is maintained at a constant potential (FIG. 8, (2)), because the first transistor FET 31 is in the OFF state due to the low S.sub.52 signal applied to the gate of the first FET 31.

Accordingly, the potential S.sub.51 varies from low level to high level and again to low level for a short period (FIG. 8, (3)). When the potential S.sub.51 again reaches a low level at the time t4 (FIG. 8, (3)), the FET 33 turns OFF and the potential S.sub.out rises immediately to the potential V.sub.cc due to the normal bootstrap effect (FIG. 8, (4)). Thus the short pulse P which occurs in the input signal S.sub.in does not exert a substantial influence on the waveform of the output signal S.sub.out (FIG. 8, (4)). Also, it should be noted that, similar to the case of FIG. 1D, there occurs hardly any power dissipation in the standby mode in the circuit of FIG. 4 in the case where a chip-select signal is used as an input signal.

An example of the structure of the inverter 51 in the circuit of FIG. 4 is illustrated in FIG. 5. The inverter 51 comprises FET 511 and 512 connected in series. The input signal is supplied to the gate of FET 512. The output signal is produced at the terminal where the source and the gate of FET 511 and the drain of FET 512 are connected.

An example of the structure of the inverter 52 in the circuit of FIG. 4 is illustrated in FIG. 6. The inverter 52 comprises FET 521 and 522 connected in series. The input signal is supplied to the gate of FET 522. The output signal is produced at the terminal where the source and the gate of FET 521 and the drain of FET 522 are connected.

Athough a preferred embodiment has been described hereinbefore with regard to the drawings, it can be understood that various modified embodiments of the present invention are possible. For example, although in the circuit of FIG. 4 the second input signal S.sub.51 is the signal which is obtained by means of an inversion action on the first input signal S.sub.in of the inverter 51 and has a delay with respect to the input signal S.sub.in, it is also possible to provide a first input signal S.sub.in and a second input signal S.sub.51 which independently have the same relationship to the first input signal S.sub.in as in the circuit of FIG. 4.

Also, although the above-mentioned embodiments are described with regard to a chip selection type buffer circuit, the present invention is also applicable to general buffer circuits such as an address inverter.

Also, although FET 34 and FET 35 are provided in the circuit of FIG. 4, it is possible to constitute embodiments of the present invention without FET 34 and FET 35.