Power Supply for Low-Voltage Incandescent Lamp and Like Load

U.S. patent application Ser. No. 379,410, Paul T. Cote', filed concurrently herewith, for "Power Supply For Low Voltage Incandescent Lamp" and assigned the same as this invention.

The present application relates to low-voltage power supplies and, more particularly, to a novel line-frequency power supply for energizing a low-voltage load.

It is often desirable to operate a low-voltage load from a relatively higher voltage A.C. source. In particular, there exists a class of low-voltage lamps having an improved efficacy due to operation of the lamp filament at a lower voltage than has been traditionally used for lamp operation. Many circuits for providing such operation either exhibit undesirably high levels of electromagnetic interference or require components having relatively high current and/or voltage ratings. In particular, previous attempts at providing low voltage power sources for incandescent lamps have utilized magnetic components for voltage transformation purposes. The cost of such magnetic components has prevented the resulting power supplies from being economical. Other power supplies have utilized phase-control waveforms, in which very narrow pulses are required, with high surge currents being provided across the load; reliability is frequently reduced in this manner. It is therefore highly desirable to provide a power supply for a low-voltage incandescent lamp and the like load, having relatively low cost, high reliability and in which components of relatively small current rating can be utilized.

In accordance with the invention, apparatus for supplying line-frequency current to a low-voltage load from a higher voltage A.C. source, includes a main capacitor in series with the load across the source, and an auxiliary capacitor connected across the main capacitor by a switching device for a selected portion of each source waveform cycle, responsive to a control signal provided by control logic means. A diode is connected to conduct in shunt with, and for opposite conduction polarity to, the control conduction path of the switching device. The total variation of load current is controlled by the ratio of the main capacitor value to the total capacitance (the sum of the auxiliary and main capacitor values) in the circuit. The switching device is preferably switched to its conductive condition either when the shunting diode is conductive, or at a positive peak voltage across the main capacitor, if the shunting diode is nonconductive.

In a presently preferred embodiment of our invention, the control logic means monitors the voltage across the main capacitor and across the load, to determine the time instant for triggering a monostable multivibrator which turns on the device for a time interval set by the multivibrator output-pulse control.

Accordingly, it is an object of the present invention to provide a novel power supply, operating at line frequency, for controlling the power to a low-voltage incandescent lamp and a like load.

This and other objects of the present invention will become apparent upon consideration of the following detailed description, when read in conjunction with the drawings.

FIG. 1 is a schematic block diagram of the novel low-voltage load power supply of the present invention;

FIGS. 1a, 1b, 1c, 1d, 1e, 1f and 1g are time-coordinated graphical representations of the main capacitor voltage, load current, auxiliary capacitor current, switching device drive signal and intermediate control logic means voltages for illustrative load currents over the total adjustment range of the supply, and useful in understanding the principles of the present invention; and

FIG. 1h is a schematic diagram of a control logic means utilizable in the circuit of FIG. 1.

Referring now to FIGS. 1, 1a, 1b, 1c and 1d the novel power supply 10 is utilized for controlling the magnitude of power applied to a load 11 from an A.C. source 12. Load 11 can be a low-voltage incandescent lamp, for example, operating at a voltage V.sub.L of between about 24 volts and about 36 volts. The power supply 10 enables the lamp to operate at a selectable fixed output power in a relatively small range of brightness; in such application, a relatively small range of lamp voltage V.sub.L is required, while the lamp current I.sub.L is variable over a predetermined, e.g. about 20%, range.

Source 12 is connected to a pair of power supply terminals 10' and 10", respectively connected to circuit nodes A and C. The load (lamp) 11 is connected between node A and a circuit common node B. A first capacitive element, hereinafter the main capacitor, C.sub.1 is connected between nodes B and C. Switching means 14 is connected between node B and one terminal of a second capacitive element, hereinafter the auxiliary capacitor, C.sub.2. The remaining terminal of auxiliary capacitor C.sub.2 is connected to node C. Terminals A, B and C, as well as the switching means control input 14a, are connected to a logic control means 16. Switching means 14 may be any device capable of controllably providing a low resistance path, between node B and that terminal of auxiliary capacitor C.sub.2 furthest from node C, responsive to a signal at its control input 14a, such that a current can flow toward or away from the auxiliary capacitor with respect to common node B. In a preferred embodiment, switching means 14 comprises a unipolar switching device, in parallel with a diode D, having the anode thereof connected to node B and the cathode thereof connected to the auxiliary capacitor C.sub.2. Advantageously, the switching means 14 is a power MOS field-effect transistor (MOSFET) S in which diode D is formed as a parasitic device between the drain electrode 14b and the source electrode 14c thereof.

Power supply 10 forms a dynamic parallel-switched capacitive voltage converter in which the minimum current I.sub.L flowing through the load resistance R.sub.L is the main capacitor current I.sub.1. An additional component of load current I.sub.L is due to the current I.sub.2 flowing through auxiliary capacitor C.sub.2. Thus, minimum load current and power occurs if current does not flow through auxiliary capacitor C.sub.2 at any point during a cycle of the source 12 waveform. Conversely, maximum load current and power occurs if the auxiliary capacitor current I.sub.2 flows for an entire source waveform cycle. A median magnitude of load current and power (and load lamp brightness) is obtained if the auxiliary capacitor current I.sub.2 flows for approximately one-half the source waveform cycle. Thus, by changing the percentage of a source waveform cycle during which auxiliary capacitor current I.sub.2 flows, the load current and power are adjusted. Switching device S is an active turn-off device, allowing conduction of current therethrough to be actively terminated some time after the device has been turned on. The interval between power switching device S turn-on and turn-off establishes the load current and power magnitude within the adjustment ranges thereof. To prevent undue stress on switching device S, it is desirable to control the switching of auxiliary capacitor C.sub.2 such that circulating current is not allowed to flow between auxiliary capacitor C.sub.2 and main capacitor C.sub.1. Therefore, control logic means 16 is utilized to turn "on" power switching device S for conduction when the voltages V.sub.1 and V.sub.2 across the pair of capacitors are substantially equal, i.e. during conduction of diode D, or at a positive peak of the main capacitor voltage V.sub.1, if diode D is non-conductive.

The operation of circuit 10 may be best understood by consideration of the main capacitor voltage V.sub.1 and auxiliary capacitor current I.sub.2 waveforms, in the median, substantially-maximum and substantially-minimum load current conditions. At some time t.sub.0, the main capacitor voltage V.sub.1 (FIG. 1a) is at a positive peak and the main capacitor current I.sub.1, because of the low power factor, is substantially 90.degree. out-of-phase with voltage V.sub.1, or substantially at zero magnitude. Switching device S is turned on, at time t.sub.o, by application of an appropriate voltage V.sub.14a to gate electrode 14a, with regard to common node B, by control logic means 16 (FIG. 1c). The switching device S remains conductive until time t.sub.1. In this time interval, from time t.sub.0 to time t.sub.1, the current through auxiliary capacitor C.sub.2 begins to decrease toward a negative-polarity peak, which is reached at time t.sub.1 (FIG. 1b). The auxiliary capacitor current I.sub.s flows from capacitor C.sub.2, through the "on" channel of device S (from drain electrode 14b to source electrode 14c,) and adds to the instantanenous main capacitor current I.sub.1 then flowing (toward load 11). Thus, the load current I.sub.L =I.sub.1 +I.sub.2.

At time t.sub.1, the gate electrode drive terminates, device S is turned off and current I.sub.2 ceases to flow. The auxiliary capacitor C.sub.2 voltage V.sub.2 has discharged substantially to zero volts, although the main capacitor C.sub.1 voltage V.sub.2 continues to decrease toward a negative peak, as the line voltage V.sub.IN approaches a negative peak value. Thereafter, voltage V.sub.1 begins to increase until a zero crossing is reached at time t.sub.2. During the time interval from time t.sub.1 to time t.sub.2, diode D is reverse-biased and device S is turned off, whereby only the main capacitor current I.sub.1 flows through the load 11. Thus, I.sub.L =I.sub.1 in this interval.

At time t.sub.2, the main capacitor voltage V.sub.1 becomes positive and greater than the substantially zero voltage remaining on auxiliary capacitor C.sub.2 ; diode D becomes forward-biased and diode current I.sub.D flows through auxiliary capacitor C.sub.2, the diode and load 11. Thus, during the time interval between time t.sub.2, when voltage V.sub.1 crosses the zero axis, and time t.sub.3, when voltage V.sub.1 attains a peak positive value, the diode conducts and the additional current I.sub.D flows as auxiliary capacitor current I.sub.2, whereby the load current I.sub.L =I.sub.1 +I.sub.2. At time t.sub.3, the diode current is essentially zero, and diode conduction ceases. It will thus be seen that in the single-cycle time interval between time t.sub.0 and time t.sub.3, auxiliary capacitor current I.sub.2 flows, in phase with main capacitor current I.sub.1, for one-half of the cycle, establishing a median load current value.

In the substantially-maximum load current condition, illustrated for the single-cycle time interval between time t.sub.3 and time t.sub.6, the auxiliary capacitor current I.sub.2 flows for the majority of the cycle (and flows for the entire cycle at the maximum load current condition). Thus, auxiliary capacitor current I.sub.2 is caused to flow, starting at time t.sub.3, by applying the switching device S driving waveform (FIG. 1c), until turn-off time t.sub.4. Therefore, at time t.sub.3, device S is rendered conductive at the main capacitor voltage V.sub.1 peak (substantially corresponding to the main capacitor current I.sub.1 being of zero magnitude). As the main capacitor voltage V.sub.1 decreases toward a negative peak, the main capacitor current I.sub.1 also decreases toward a negative peak value, attained at the zero crossing of voltage V.sub.1 in the t.sub.3 -t.sub.4 interval, and then increases. The auxiliary capacitor current I.sub.2 also decreases toward a negative peak and thereafter increases until time t.sub.4, at which time the switching device is turned off and the switching device current I.sub.S (essentially equal to the auxiliary capacitor current I.sub.2) ceases. There is no current surge through switching device S at turn-on or turn-off, as the voltages across the capacitors are equal. At time t.sub.4, the voltage across auxiliary capacitance C.sub.2 is at a relatively high negative value, which is more positive than the main capacitor voltage V.sub.1 in the time interval t.sub.4 -t.sub.5 ; diode D is reverse-biased. At time t.sub.5, the main capacitor voltage V.sub.1 again becomes more positive than the auxiliary capacitor voltage V.sub.2 and diode D conducts. Diode current I.sub.D increases, until the main capacitor voltage V.sub.1 passes through the positive-going zero crossing in time interval t.sub.5 -t.sub.6, and thereafter decreases. The diode current I.sub.D reaches essentially zero magnitude at t.sub.6, when the capacitor voltage reaches a positive peak value, and diode D ceases to conduct. Therefore, the load current I.sub.L is the sum of the in-phase main and auxiliary capacitor currents I.sub.1 and I.sub.2, in the time intervals t.sub.3 -t.sub.4 and t.sub.5 -t.sub.6 ; the load current is equal to the main capacitor current I.sub.1 only in the relatively small time interval t.sub.4 -t.sub.5. As the auxiliary capacitor current I.sub.2 flows for a longer portion of the cycle in time interval t.sub.3 -t.sub.6 than in time interval t.sub.0 -t.sub.3, it will be seen that greater load current (and therefore greater load power and load lamp brightness) occurs during the latter time interval.

In the substantially-minimum load current case, illustrated in the time interval t.sub.6 -t.sub.9, the switching device S is again turned on while the main capacitor voltage is at a peak, at time t.sub.6, and is only kept on for a relatively short time, being turned off at time t.sub.7. Therefore, the auxiliary capacitor current I.sub.2 flows through switching device S (as device current I.sub.S) only in the relatively short time interval t.sub.6 -t.sub.7. At time t.sub.7, when device S is turned off, a relatively high positive voltage V.sub.2 remains across auxiliary capacitor C.sub.2. As main capacitor voltage V.sub.1 decreases thereafter, diode D is reverse-biased and neither the diode nor the switching device conduct, until time t.sub.8. At time t.sub.8, the main capacitor voltage V.sub.1 again reaches a positive voltage equal to the positive voltage left across the auxiliary capacitor, and diode D conducts until the end of the cycle, at time t.sub.9, when the diode current falls to zero and diode D is about to become reverse biased. It will be seen that the load current I.sub.L, in the time interval t.sub.6 -t.sub.9, is equal to the sum of the in-phase main and auxiliary capacitor currents I.sub.1 and I.sub.2 in the time intervals t.sub.6 -t.sub.7 and t.sub.8 -t.sub.9, and is equal only to the main capacitor current I.sub.1 in the time interval t.sub.7 -t.sub.8, which forms the major portion of time interval t.sub.6 -t.sub.9. As the time intervals t.sub.6 -t.sub.7 and t.sub.8 -t.sub.9 become progressively smaller, the load current also becomes progressively smaller, reaching the minimum load current, established by the main capacitor current I.sub.1, when these time intervals become essentially zero.

It will now be seen that the total adjustment range of the load current I.sub.L is established by the relative contribution of auxiliary capacitor current I.sub.2 and the portion of each cycle during which that current I.sub.2 flows, with respect to the main capacitor current I.sub.1. By suitable choice of the capacitance of capacitor C.sub.2, with respect to the capacitance of main capacitor C.sub.1, the total range of load current variation is established.

Referring now to all of the Figures, and particularly FIG. 1h, control logic means 16 provides the switching device S gate electrode 14a drive signal to turn on the switching device during the conduction interval of diode D or at the positive peak voltage on main capacitor C.sub.1 if diode D is not immediately-previously conducting current. Control logic means 16 also turns off switching device S with the proper timing to establish the total load current magnitude. Circuit 16 includes first and second inverters 20 and 22, each having an input 20a or 22a respectively coupled through first and second resistance elements 28a and 30a, or 28b and 30b, to the associated one of the respective C and A nodes of the power supply. Limiting diodes 32a and 34a are connected to the junction C' between resistances 28a and 30a, and limiting diodes 32b and 34b are connected to the junction A' between resistances 28b and 30b, to limit, commonly referred to in the art as hard limit, the junctions C' and A' voltages, respectively, to be never less than one diode drop below the common node B potential and never greater than one diode drop above a positive voltage logic supply rail 24 (which voltage can be provided by known techniques). The inverter outputs 20b and 22b are each connected to a different one of the pair of inputs of a NAND gate 36. The output 36a of gate 36 is connected to the negative-going trigger input 38a of a one-shot multivibrator means 38, which may be provided as an integrated circuit monostable multivibrator. The positive-going trigger input 38b and the common supply input 38c of means 38 are connected to common node B, while the positive supply input 38d is connected to positive voltage rail 24. An output-pulse time-duration-establishing input 38e is connected to a timing capacitor 40, having the remaining terminal thereof connected to common node B, and also to positive supply rail 24 through the series-connected combination of a first, fixed timing resistance 42a and a variable timing resistance 42b. The multivibrator means output 38f is connected to the switching device input 14a, e.g. to the gate electrode of the power MOSFET device S. The value of fixed resistance 42a is selected to provide a minimum "on" time for the switching device S, and to limit the maximum current drawn by multivibrator means input 38e. The resistance magnitude of variable resistor 42b is selected to achieve a maximum "on" time for the switching device, dependent upon the ratio of maximum to minimum load current/power/brightness required.

In operation, control logic means 16 provides an open-loop control means, in which the voltage across main capacitor C.sub.1 is sensed by the hard-limiting inverting means formed by inverter 20, resistances 28a and 30a, and limiting diodes 32a and 34a. As the main capacitor voltage V.sub.1 becomes positive, the inverter output 20b falls from a high to a low voltage. Conversely, as V.sub.1 becomes negative, the inverter output 20b rises from a low to a high voltage. Thus, output 20b has a low output level for positive voltages across the main capacitor and a high output level for main capacitor negative voltages. Second inverter 22, in association with resistances 28b and 30b and diodes 32b and 34b, also forms a hard-limiting inverting means sensing the voltage V.sub.L across load 11. Therefore, the state of second inverter output 22b is an inverse measure of the load current I.sub.L. The voltage output of 20b and 22b are shown in FIGS. 1d and 1e respectively. As shown in FIG. 1f, the output 36a of the NAND gate will have a negative-going transition at the peak of the main capacitor voltage. This negative-going transition triggers one-shot multivibrator means 38, to produce the positive-going gate electrode signal V.sub.14a, with respect to common node B, having a time duration determined by the magnitude of capacitance 40 and the total resistance of the series-connected resistors 42a and 42b.

While control logic means 16 is shown as an open-loop means, wherein the load current/power/brightness is established by manual adjustment of a variable resistance 42b, it should be understood that a closed-loop control logic means may be equally as well utilized, with a feedback signal being applied, as a current into capacitor 40 or a voltage into charging resistors 42a and 42b, to the monostable multivibrator to vary the conduction time interval of switching device S.

While the present invention has been described with respect to one presently preferred embodiment thereof, many variations or modifications will now become apparent to those skilled in the art. It is out intent, therefore, to be limited only by the scope of the appending claims and not by the specific details and instrumentalities described by way of example herein.