CVSD Transmission With Improved Intelligibility of Voice Signals

This invention relates to the encoding of voice signals by differential modulation such as differential pulse-code modulation (DPCM), delta modulation, or continuously variable-slope data (CVSD) modulation. In particular, it relates to a method and means of improving the intelligibility of voice signals that are subjected to differential modulation.

CVSD modulation is a well-known system for producing digitally encoded signals from analog signals. To perform the encoding, the analog signal is sampled at spaced intervals. In each of these intervals a reconstructed signal is compared with the analog signal. If the analog signal is bigger, a logical one is generated; if the analog signal is smaller, a logical zero is generated. The resulting bit stream is integrated in time to determine the signal that is compared to the analog signal. As described so far, the system is Delta Modulation which features integration with a constant slope. When that slope is made variable according to a rule, the result is CVSD modulation. The rule is normally applied to cause a change in the slope of the comparison curve after a predetermined consecutive number of intervals indicate a change in the same direction.

The principal objective of using CVSD modulation is to encode voice signals for broadcast at relatively low bit rates. In such a system, the bit rate is normally fixed, and it is necessary to design the operating characteristics of the system to deal effectively with a desired dynamic range and a desired frequency spectrum. It is evident that for a fixed signal level the maximum slope of an audio signal is a function of the high-frequency components in the signal and for a given audio waveform the maximum slope is a function of the strength of the signal. This is summarized in the statement that CVSD modulation has a decrease in the usable dynamic range with an increase in frequency, and vice versa. In contrast, there is no particular correlation between the loudness or softness with which a speaker addresses a microphone and the frequency content of the signal that he or she delivers to the microphone.

It is an object of the present invention to match the characteristics of different speakers more closely to the characteristics of CVSD modulation.

It is a further object of the present invention to improve the intelligibility of voice signals that are subjected to CVSD modulation.

Other objects will become apparent in the course of a detailed description of the invention.

A voice signal in electrical analog form is differentiated, clipped, integrated and applied to a CVSD modulator.

FIG. 1 is a functional block diagram of a circuit for the practice of the present invention.

FIG. 2 is a circuit diagram of a circuit for the practice of the present invention.

FIG. 1 is a functional block diagram showing the circuit functions that combine to form the present invention. In FIG. 1 an AC electrical signal that carries voice information from a microphone or the like enters at terminal 10 and is applied to a differentiator 12. The output of differentiator 12 is connected to clipper 14 which limits peaks of the signal from differentiator 12 to a maximum value. The output of clipper 14 is applied to integrator 16 which integrates the clipped signal to provide a processed signal that is then coupled to CVSD modulator 18. It has been observed that the processed signal is more intelligible to a listener than the same signal without such processing.

FIG. 2 is a detailed circuit realization of the present invention. In FIG. 2, terminal 10 receives voice signals from a microphone or other source. The signal at terminal 10 is applied to differentiator 12 which is a series combination of a resistor 24 and a capacitor 26 that comprises a high-pass filter with a crossover near the upper end of the desired voice band. Differentiator 12 may be a network installed especially for the purpose or it may be a pre-emphasis network of the type that is normally used in processing voice signals for FM broadcasts. The output of differentiator 12 is taken to clipper 14 which is an operational amplifier 28 with a feedback resistor 30 that comprises an amplifier. The gain of the amplifier is chosen so that the amplifier saturates on peaks, clipping them. The clipped output of clipper 14 is applied to integrator 16 which includes blocking capacitor 32 and series resistor 34 in cascade with the input to operational amplifier 36. Integrating capacitor 38 and its paralleled resistor 40 are placed in a feedback configuration around operational amplifier 36. If necessary to maintain band limitations, a low-pass filter could be placed between clipper 14 and integrator 16. A chip boundary 42 is shown here to indicate that certain of the components in FIG. 2 are well adapted to be included in an integrated circuit. The resistors 24, 30, 34 and 40, and capacitors 26, 32 and 38 are most easily realized as discrete components, and they are therefore shown as being outside the chip boundary 42. Operational amplifier 28 is here shown off the chip because it has been built and operated that way. A designer might equally as well choose to include operational amplifier 28 on the chip.

The remaining components in FIG. 2, together with integrator 16, constitute a CVSD modulator with a rule of three. This means that three consecutive pulses in the same direction call for an increase in the magnitude of the slope. The output of operational amplifier 36 is taken as an input to limiter 44. The output of limiter 44 is taken as an output to the first of three cascaded flip-flops 46, 48 and 50, each of which is clocked by a pulse from clock source 52. Outputs from each of the flip-flops 46, 48 and 50 are taken as inputs both to a NAND gate 54 and to a NOR gate 56. The outputs of NAND gate 54 and NOR gate 56 are applied as inputs to EXCLUSIVE-OR gate 58 which operates analog switch 60 whenever there are three consecutive pulses in the same direction. When the three consecutive pulses indicate that the CVSD slope is too low, analog switch 60 connects the voltage V.sub.ss through a resistor 62 to capacitor 64 to increase the voltage on capacitor 64 to a higher value. On the other hand, if three consecutive pulses in flip-flops 46, 48 and 50 indicate that the CVSD slope is too high, then analog switch 60 connects a ground at one end of resistor 62, tending to discharge capacitor 64 and reduce the integrating slope. The voltage on capacitor 64 is also determined partly by the voltage divider of resistors 66 and 68 on voltage V.sub.ss. Resistor 66 sets the minimum slope, and resistor 68 sets the maximum.

The output of flip-flop 46 is the CVSD signal which appears at terminal 70. That signal is also applied to analog switch 72 to select a feedback voltage as an additional input to integrator 36 through a series capacitor 74 and resistor 76. When the output of flip-flop 46, the CVSD signal, is high, analog switch 72 is connected to apply the voltage of capacitor 64 as an input to integrator 36 through series capacitor 74 and resistor 76, causing the circuit to integrate down. When the output of flip-flop 46 is low, analog switch 72 is grounded, causing the circuit to integrate up. Operational amplifier 36 and integrating capacitor 38 thus do double duty, serving both as an integrator for processing the audio signal and as a CVSD integrator with a variable slope that is determined by the controlled voltage across capacitor 64.

Balancing resistors 78, 80 and 82 and by-pass capacitor 84 are shown here because they are useful for equalizing DC potentials in the circuit. A common reference source 86 applies an appropriately chosen reference voltage to one terminal of each of the operational amplifiers 28 and 36 and limiter 44. Reference source 86 is assumed to have adequate filtering to decouple the operational amplifiers from each other.

The values of resistors and capacitors are not shown in FIG. 2 because their selection is believed to be obvious to a skilled designer who is aware of their functions. However, the values actually used in a realization of the circuit are listed in the Table. Those values were used in a circuit that was designed to process speech in a frequency band from 300 Hz to 3 kHz. The corner frequency for differentiator l2 was set at 5 kHz, and clock source 52 was operated at 12 kHz. The operational amplifiers, flip-flops, and gates were custom-designed in complementary metal-oxide semiconductor (CMOS) circuits.