Programmable Fuse Circuit

1. Field of the Invention

The present invention relates to the field of programmable fuse circuits. More specifically, the present invention relates to a programmable fuse circuit which allows a packaged integrated circuit to be programmed without the need for an extra package pin to control the programming function.

2. Brief Description of the Prior Art

It is common in the manufacture of the integrated circuit memories to have a defect occur in one portion of the memory array. It is desirable to use the functional portion of these memories as partial memories having total memory sizes smaller than the size of the original memory. Specifically, 8K Rams having defects in one portion of their memory array can often be used as 4K RAMS. However, it is necessary to specify which pin or which side of the partially functional memory is defective so that only the functional side of the memory array is used. Typically it is necessary to specify that one of the address pins of the partially functional memory is to be held at a specific voltage level to select the functional portion of the memory array.

In another type of semiconductor circuit a metal mask option can be applied as the last step in the manufacture of a semiconductor memory to provide connections which selectively activate desired circuit functions. For example, by proper design of the memory circuitry and the interconnects formed by the metal mask options, the memory can be selectively configured in either a 1K by 4-bit format or a 4K by 1-bit format. However, it would be desirable to be able to make a single part which could be selectively programmed to the desired memory format without the need for alternative metal masks. This would eliminate the need for separate metal masks and the need to inventory either partially completed memory circuits or two different types of memory circuits.

Similarly, mask options are often used to code select addresses into comparators of memories with multiple chip-select inputs. However, this requires the sorting and separate storing of memories programmed with each of the possible chip addresses. Again, it is desirable to have a single memory circuit which can be programmed to have any of the desired chip select addresses.

The preferred embodiment of the present invention has a transistor fuse circuit adapted to selectively program a fuse and a corresponding output signal in response to a reversal of the polarity of the power supply inputs. In the preferred alternative embodiment, this fuse circuit is incorporated in a programmable partial memory circuit which is programmed to address only selected addresses of a partially functional memory chip. In another preferred alternative embodiment the fuse circuit may be incorporated in a reconfigurable memory circuit which is programmable to reformat input and output lines. For example, the fuse circuit may be used to reformat a memory circuit normally having a 4-bit parallel output so that two of the original data lines are used as address inputs to select one of the four output bits, converting the memory to a one-bit output format with two additional address lines. Finally, in yet another preferred alternative the fuse circuit may be incorporated in a chip select circuit for selectively activating a designated circuit in response to selected chip address signals.

FIG. 1 is a detailed schematic diagram of a programmable fuse circuit in accordance with the preferred embodiment of the present invention.

FIG. 2 is a detailed schematic diagram of the programmable fuse circuit of FIG. 1. The circuit has been inverted to illustrate the inversion of the voltages applied to terminals V.sub.SS and V.sub.CC.

FIG. 3 is a waveform diagram illustrating the signals used to program the programmable fuse circuit of FIGS. 1 and 2.

FIG. 4 is a waveform diagram illustrating signals and voltages characteristic of the normal circuit operation of the programmable fuse circuit of FIGS. 1 and 2.

FIG. 5 is a block diagram of a partial memory select circuit having programmable fuse circuits for selecting active portions of the memory.

FIG. 6 is a block diagram of a reconfigurable memory select circuit having a programmable fuse circuit for selecting memory input/output format.

FIG. 7 is a block diagram of a chip select circuit having three programmable fuse circuits.

FIG. 8 is a detailed schematic diagram of a partial memory select circuit.

FIG. 9 is a dimensional view of a polysilicon fuse.

FIG. 1 is a detailed schematic diagram of a programmable fuse circuit in accordance with the preferred embodiment of the present invention. A voltage supply terminal V.sub.SS, preferably coupled to an operating voltage equal to ground, is coupled to the gate of a transistor T1, one terminal of resistor R1 and one terminal of a polysilicon fuse F1. The other terminal of resistor R1 is coupled to a gate of a transistor T2 and to a first terminal of transistor T1. The other terminal of transistor T1 is coupled to an address line A.sub.X. The other terminal of polysilicon fuse F1 is coupled to a first terminal of transistor T2 and a first terminal of resistor R2. This terminal provides an output control signal which is the programmable control signal generated by the programmable fuse circuit. The other terminal of transistor T2 and the other terminal of resistor R2 are coupled to a voltage supply terminal V.sub.CC, which is preferably coupled to an operating voltage equal to 5 volts.

In the preferred embodiment of the present invention resistor R1 is 10K ohms, resistor R2 is 1M ohm, transistor T1 is an N-channel field effect transistor having a width to length ratio (W/L) of 100/4, transistor T2 has a W/L=400/4, and polysilicon fuse F1 has a resistance of 50 ohms. Further, polysilicon fuse F1 has a current handling capability of approximately 10 milliamps and blows, causing an open circuit, if a larger current is applied for more than approximately 1 second.

In the normal mode of operation, terminal V.sub.SS is coupled to a ground voltage and terminal V.sub.CC is coupled to a positive voltage of approximately five volts. In this mode, transistors T1 and T2 are both nonconductive. The level of output control signal is determined by the ratio of the resistances of resistor R2 and fuse F1. The resistance of resistor R2 is approximately 1M ohm and the resistance of the fuse F.sub.1 is approximately 50 ohms. Thus, in this "unprogrammed" state, the output control signal is approximately equal to the ground voltage applied to terminal V.sub.SS. In the normal mode of circuit operation an address signal is applied to address line A.sub.X. This address signal is unaffected by the programmable fuse circuit.

In some applications it is desirable to program the level of the output control signal V.sub.CONTROL. In the present invention, the output control signal V.sub.CONTROL is programmed by applying a normally illegal condition to the inputs of the programmable fuse circuit. Specifically, as illustrated in the detailed schematic diagram FIG. 2 the power supply voltages are inverted, a voltage of approximately five volts is applied to terminal V.sub.SS and terminal V.sub.CC is coupled to ground. Address line A.sub.X is brought a few volts negative to insure that transistor T1 turns on as soon as the voltage on terminal V.sub.SS goes positive to avoid any possible programming errors.

This sequence of signals is shown in waveform diagram FIG. 3. The voltage applied to terminal V.sub.SS is raised to a voltage of approximately five volts. To progam the fuse a voltage of approximately 5 volts is applied to address line A.sub.X. The application of a five volt address signal to address line A.sub.X and the application of a five volt signal on terminal V.sub.SS causes the gate of transistor T2 to charge to 5 volts, enabling transistor T2 and causing it to conduct an additional current through polysilicon fuse F.sub.1. Transistor T.sub.2 has an on resistance of approximately 75 ohms which draws an additional current through polysilicon fuse F.sub.1 of approximately 40 milliamps. Polysilicon fuse F1 is designed to blow at a current of approximately 20 millamps. This, causes transistor T1 to conduct which results in an open circuit between terminal V.sub.SS and terminal V.sub.CONTROL. This results in an output control signal having a voltage of approximately 5 volts, the voltage normally applied to terminal V.sub.CC, in a subsequent normal mode of circuit operation.

FIG. 4 is a waveform diagram of signals and supply voltages characteristic of the normal operation of the preferred embodiment of the present invention. A supply voltage of preferably five volts, is applied to terminal V.sub.CC and a supply voltage of 0 volts is applied to terminal V.sub.SS. The output control signal provided by the programmable fuse circuit on terminal V.sub.CC is approximately equal to the voltage applied to terminal V.sub.CC if the circuit has been programmed, that is, if polysilicion fuse F1 has been blown, and is approximately equal to the voltage applied to terminal V.sub.ss if the circuit has not been programmed.

In the preferred embodiment of the present invention, the substrate of the circuit is floating or is coupled to a terminal separate from terminals V.sub.ss and V.sub.cc. It should be noted that present embodiment of the present invention does not program properly if the substrate is coupled to terminal V.sub.ss.

One use of the preferred embodiment of the present invention is in the selection of partial memories by selectively programming programable fuse circuits. A block diagram of a partial memory select circuit 500 is illustrated in FIG. 5. As illustrated, output control signals V.sub.C1 and V.sub.C2 provided by programmable fuse circuits 510 and 520 are logical zeros if the polysilicon fuses of programmable fuse circuits 510 and 520 are intact and logical ones if the polysilicon fuses are blown. Partial memory select circuit 500 has three different states depending on the status of the output control signals provided by programmable fuse circuits 510 and 520. Table 1 illustrates the values of the output control signals and the corresponding output of a one-of-four decoder 530. If the output of decoder 530 is equal to a zero, corresponding to output line 0 having a high voltage level, transistor T51 is conductive and the most significant bit address line A10 is coupled to memory 540 and memory 540 is configured as fully functional memory having a capacity of 2,048.times.8-bits. If the signal on the 1 output line of decoder 530 is a high voltage, transistor T52 is conductive, a high voltage is applied to address line A10, and memory 540 is coupled as a partial memory where the "bottom" 1024.times.8-bits, corresponding to A10=a logical one, are addressed in response to signals on address lines A0-A9. If the signal on the 2 output line of decoder 530 is a high voltage, transistor T53 is conductive, a ground voltage is applied to address line A10, and memory 540 is coupled as a partial memory where the "top" 1,024.times.8-bits corresponding to A10=a logical 0, are addressed in response to signals on address lines A0-A9.

The condition where the signal on the 3 output of decoder 530 is a high voltage in an unused state.

FIG. 6 is a block diagram illustrating the use of a programmable fuse circuit 600 in a reconfigurable memory select circuit 610. Specifically, if the value of output control signal V.sub.CB is a logical zero, a memory 620 is configured in a format of 4,096.times.4-bits. That is, a memory having 4,096 4 bit memory locations. If programmable fuse circuit 600 is programmed so that control bit V.sub.CB is a logical one, then memory 620 is configured in a format of 16,384.times.1-bit. It should be noted that in the 4K.times.4 bit format terminals 630, 640, 650 and 660 are all input/output data terminals. However, in the 16K.times.one bit embodiment, terminals 630 and 640 are both used as additional address input terminals, terminal 650 is used as a data input/output terminal and terminal 600 is no longer functional. Specifically, 1 or 4 decoder 670 multiplexers one of the 4 data bits from memory 620 onto terminal 650 in response to the values of signals applied to terminals 630 and 640 and an output control signal on line V.sub.CB corresponding to a logical one.

FIG. 7 is a block diagram illustrating three programmable fuse circuits 700, 710 and 720 implemented in a chip select circuit 730. Chip select circuit 730 compares signals on input terminals C.sub.S1, C.sub.S2 and C.sub.S3 against a previously programmed code. Specifically, if the input signals applied to terminals C.sub.S1, C.sub.S2 and C.sub.S3 match the output control signals V.sub.C1, V.sub.C2 and V.sub.C3 provided by programmable fuse circuits 700, 710 and 720, comparator 740 will provide a chip select signal and 16K memory array 750 will be actively coupled so as to be responsive to signals on address lines A.sub.0 -A.sub.13 and a data input/output line D. For all other conditions of the signals on terminals C.sub.S1, C.sub.S2, and C.sub.S3 the memory 750 is unresponsive to signals on the address lines.

FIG. 8 is a detailed schematic diagram of an address buffer for the MSB, A.sub.1, of an 8K.times.8 pseudostatic RAM having two programmable fuse circuits in accordance with the preferred embodiment of the present invention. This address buffer can be programmed in response to address signals or address lines A.sub.1 and A.sub.2 as described above. Address signal A.sub.1 and a reference voltage V.sub.REF are clocked to a comparison circuit 820 by a series of clocking transistors T1, T3, T4, T5, T29, T28, and T27 under the control of clock signals CLK1, CLK1, CLK2, CLK3 and CLK4. If polysilicon fuses F1 and F2 are intact, nodes 830 and 840 of comparison circuit 820 are coupled to ground through the 50 ohm polysilicon fuses. If it is desired to force one of the address signals to a logical one or a logical zero, the polysilicon fuses can be selectively blown. For example, if polysilicon fuse F1 is blown, node 830 goes to a high voltage level which forces node 840 to a low voltage level.

The address buffer controls the most significant bit (MSB) of the 8K.times.8 pseudostatic RAM, thus programming the MSB selects either a top or bottom partial memory having a 4K.times.8 format. When programmed, the MSB input terminal becomes a "don't care," and only the portion of the memory corresponding to the programmed value of the MSB is operative.

The differential output of comparison circuit 820 is applied to the gates of transistors T17 and T18 which comprise a part of a second latch 850. This second latch is conventional in that the terminals 860 and 870 are grounded. The outputs CA, and CA, of latch 850 are coupled to the memory circuit to select the MSB of the memory address.

FIG. 9 is an illustration of the polysilicon fuse of the preferred embodiment.

While the invention has been particularly taught and described with reference to the preferred embodiments, those versed in the art will appreciate that minor modifications in form and detail may be made without departing from the spirit and scope of the invention. Accordingly, all such modifications are embodied within the scope of this patent as properly come within my contribution to the art and are particularly pointed out by the following claims.