SMSK and MSK Demodulator

Minimum shift keyed (MSK) modulation has received considerable attention over the past decade due to its potential as a bandwidth and power efficient constant envelope modulation technique. Two generic techniques for the modulation and demodulation of MSK signals are referred to as the parallel and serial methods. Both are completely equivalent in terms of bandwidth occupancy and bit error rate (BER) performance.

With the series approach, the MSK modulated signal is produced from a bi-phase modulated signal by filtering it with an appropriately designed conversion filter. This method is described in detail in a copending application entitled "Serial Minimum Shift Keyed Modulator", assigned to the same assignee and filed of even date herewith. Since the advent of serial minimum shift keyed (SMSK) modulation, the general trend has been to construct single channel demodulators which operate essentially in the reverse of the SMSK modulators. See, for example, F. Amoroso and J. A. Kivett, "Simplified MSK signaling Technique", IEEE Transactions on Communications, Volume Com-25, pp. 433-441, April 1977. All of the single channel SMSK demodulators require a matched filter which is relatively difficult to construct and there is no indication if the output is locked or coherent.

The present invention pertains to a demodulator for use with SMSK or MSK signals, which demodulator incorporates a Costas type closed loop wherein the reference oscillator is offset from the apparent center frequency of the input signals and a network of filters is utilized so that an in-phase channel provides data at the output thereof and a quadrature phase channel provides an indication of lock as well as a control signal for the VCO.

It is an object of the present invention to provide a new and improved SMSK or MSK demodulator utilizing a Costas type control loop.

It is a further object of the present invention to provide an SMSK or MSK demodulator utilizing a Costas type control loop including an in-phase channel for providing a data output and a quadrature channel for providing an indication of lock.

It is a further object of the present invention to provide an SMSK or MSK demodulator utilizing a simplified filtering network.

These and other objects of this invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims and drawings.

Referring to the drawings,

FIG. 1 is a block diagram of a prior art SMSK demodulator;

FIG. 2 is a block diagram of a generalized embodiment of an SMSK or MSK demodulator incorporating the present invention;

FIG. 3 is a block diagram of a specific embodiment of an SMSK or MSK demodulator constructed in accordance with the generalized embodiment of FIG. 2;

FIG. 4. is a schematic/block diagram of a specific embodiment of an SMSK or MSK demodulator constructed in accordance with the generalized block diagram of FIG. 2, and

FIG. 5 is a graph showing the relative degradation versus tracking error for the demodulators of FIGS. 1 to 4.

In 1976, Amoroso and Kivett (see the above referenced article) introduced a simplified means of generating an MSK signal by using a conventional bi-phase modulator followed by a linear time invarient filter. This means of generating an MSK signal has been given the name serial minimum shift keyed (SMSK) because it generates the MSK signal from a serial bit stream. The SMSK signal can be demodulated by a conventional MSK demodulator, which uses two phase detectors to detect the in-phase and quadrature signals. The output of the conventional MSK demodulator consists of two data streams, each at a data rate of R=1/2T or a total data rate of R.sub.T =1/T.

Amoroso and Kivett (see the above referenced article) also proposed a simplified MSK demodulator, a block diagram of which is illustrated in FIG. 1. This simplified MSK demodulator includes a matched filter 10 through which the input signal is supplied to a single phase detector 12. A local oscillator 14 supplies a reference frequency for demodulation and the output signal is supplied through a low pass filter 15 to a data output terminal 17. Both the conventional MSK demodulator and the simplified MSK demodulator of FIG. 1 have the disadvantage of not being able to indicate when the demodulator is locked onto the desired signal and they require relatively complicated matched filters, which must be matched to the modulated signal.

Referring specifically to FIG. 2, a block diagram of a generalized embodiment of an SMSK or MSK demodulator incorporating the present invention is illustrated. An input terminal designated 20 is adapted to receive an input signal, which may be an MSK or SMSK signal, and is connected to an input of a first demodulator 22 and a second demodulator 23. It will of course be understood by those skilled in the art that the demodulators 22 and 23 are also commonly referred to as phase detectors, multipliers, or mixers and circuits or devices which perform these functions may be substituted therefor. A voltage controlled oscillator 25 provides a reference frequency which is supplied to a 90.degree. hybrid circuit 26. The hybrid circuit 26 supplies an in-phase reference signal to the demodulator 22 and a quadrature reference signal (shifted 90.degree. from the in-phase signal) to the demodulator 23. It will of course be understood that many types of circuits might be utilized to provide the in-phase and quadrature reference signals and a 90.degree. hybrid circuit is simply one example of a circuit which will provide the desired signals. The output of the demodulator 22 is supplied to a pair of filters 30 and 31. Similarly the output of the demodulator 23 is supplied to a pair of filters 33 and 34. The output of the filters 31 and 33 are supplied to a combining, or summing, circuit 37 to form an in-phase arm or channel. The outputs of the filters 30 and 34 are supplied to two inputs of a combining, or summing, circuit 39 to form a quadrature arm or channel. The output of the combining circuit 37 is coupled through a low pass filter 41 to an output terminal 42 and to one input of a combining circuit 45. The output of the combining circuit 39 is coupled through a low pass filter 47 to a second input of the combining circuit 45. In general, the combining circuit 45 will be a multiplier type of circuit although other types of circuits might be utilized to perform the required functions. The output of the combining circuit 45 is supplied to the VCO 25 as a control signal.

For the serial MSK demodulator, illustrated in FIG. 1, the bandpass filter 10 matched to the transmitted signal is followed by the coherent demodulator 12 which is ideally frequency and phase locked to the carrier frequency of the data m(t). The actual data detection is, thus, accomplished by sampling at t-second spaced intervals and deciding that a "1" was sent if a given sample is greater than 0 and a "0" was sent otherwise. It can be shown that such a procedure results in a bit error rate performance, under ideal conditions, which is the same as that for a parallel MSK implementation; as a point of reference, a bit error rate of 10.sup.-6 requires a signal-to-noiseratio of about 10.6 dB.

FIG. 2 is an implementation of the bandpass conversion and matched filters of the serial MSK demodulator as low pass equivalents. To this end, the serial demodulator structure of FIG. 1 is replaced with the in-phase/quadrature mixer, low pass filter structures of FIG. 2. From an implementation standpoint, this approach has the following advantages features:

(1) The low pass filters may be easier to realize at high data rates than bandpass filters;

(2) Monolithic mixers can be used in the quadrature arms;

(3) The sensitivity to hardware impairments of the structure of FIG. 2 is not as great as for the conventional parallel demodulators; and

(4) The demodulator can be implemented as a Costas loop type of structure, as illustrated in FIG. 2, and carrier synchronization is provided.

The impulse responses of the in-phase and quadrature arm matched filters 30, 31, 33 and 34 of FIG. 2 are

and

where h(t) denotes the complex envelope of the matched filter impulse response referenced to f.sub.1, where f.sub.1 =f.sub.o -1/4T. Thus, the real impulse response ##EQU1##

The spectrum of the complex envelope of an MSK signal, when referenced to the mark frequency, is ##EQU2## Therefore, the transfer function of the low pass equivalent MSK matched filter is

where T.sub.d is an arbitrary time delay. Using the Fourier transform pair ##EQU3## the complex envelope of the matched filter impulse response is found to be ##EQU4## where T.sub.d has been arbitrarily taken as zero. Separating (7) into its real and imaginary parts, we find that the impulse responses of the in-phase and quadrature channel filters are:

and

The transfer functions of the in-phase and quadrature channel filters, which are the Fourier transforms of (8) and (9), are ##EQU5## respectively, where sinc(u).DELTA.(sin .pi.u)/(.pi.u). The transfer function of the low pass equivalent matched filter can be found from

and, as a check, shown to be the same as (4) with T.sub.d =0. H.sub.1 (f) is even and real, H.sub.2 (f) is imaginary and odd, and their quadrature sum is offset 0.25/T Hz from f.sub.1, which is the reference frequency used for the low pass equivalent representation. Furthermore, the low pass transfer functions which are 2R wide between mainlobe zeros, add in phase quadrature to produce a bandpass (or low pass equivalent) transfer function which is 1.5R wide, where R=1/T is the data rate.

The block diagram of FIG. 2 illustrates a general embodiment of a demodulator employing a Costas loop type of structure to provide carrier synchronization. The matched filters 30, 31, 33 and 34 can be formed in a variety of embodiments which fulfill the requirements set forth above. As an example, the matched filters can be implemented from open/shorted transmission lines, quadrature hybrids, (to be described in conjunction with FIG. 3) and lumped element filters (to be described in conjunction with FIG. 4). Many other types of filters might be implemented by those skilled in the art and the specific filters described herein are simply for purpose of example.

The frequency of VCO 25 is offset from the apparent carrier of the input or received signal by some predetermined amount. In the disclosed embodiments VCO 25 operates at the frequency f.sub.1, which is equal to f.sub.o -1/4T. Since f.sub.o is the apparent carrier of the input or received signal, VCO 25 is offset by a frequency of -1/4T. This offset of VCO 25 produces an asymmetry in the matched filters resulting in the demodulated data appearing only at output terminal 42. The quadrature channel provides an indication of whether the loop is locked on the correct frequency. That is, if VCO 25 is at the correct frequency, the signal at the output of low pass filter 47 is substantially zero. The output of low pass filter 47 is combined with the output of low pass filter 41 to produce a control signal that is used to adjust VCO 25 to the correct frequency and phase.

Referring specifically to FIG. 3, a specific embodiment of the demodulation system illustrated generally in FIG. 2 is disclosed. An input terminal 50 is adapted to receive MSK or SMSK signals and is connected to an input of each of a pair of demodulators 52 and 53. A VCO 55 supplies a reference frequency signal by way of a 90.degree. phase splitting circuit 56 to a second input of each of the demodulators 52 and 53. The circuit 56 supplies an in-phase reference frequency signal to the demodulator 52 and a 90.degree. shifted or quadrature reference frequency signal to the demodulator 53. The outputs of the demodulators 52 and 53 are coupled through low pass filters 58 and 59, respectively, to a quadrature hybrid circuit 60. A first output of the quadrature hybrid circuit 60 is connected through a filter 62 to an output terminal 63 and to one input of a combining, or multiplying, circuit 65. A second output of the quadrature hybrid circuit 60 is connected through a second filter 67 to a second input of the combining circuit 65. The output of the combining circuit 65 is connected to a control input of the VCO 55.

The matched filter implementation of FIG. 3 makes use of an approach similar to an image rejection mixer, except that the frequency response charactristics of the quadrature hybrid circuit 60 have been chosen to give the required matched filter response for the low side of the demodulated spectrum. The low pass filters 58 and 59 provide a necessary high side noise rejection. The frequency response of the low pass filters 58 and 59 and the quadrature hybrid circuit 60 are ##EQU6## where

f is the instantaneous frequency of m(t),

f.sub.o is the apparent carrier frequency of m(t), and

f.sub.m is the center frequency of quadrature hybrid 60.

The H.sub.I (f) response and the H.sub.Q (f) response each have a gain of -3 dB at the reference frequency of f.sub.o +1/4T, but one peaks on the high side of this reference at a frequency of f.sub.o -1/4T+f.sub.m and nulls at f.sub.o -1/4T-f.sub.m. A corresponding response for the other signal is obtained. The filters with the above frequency characteristics have the desired image rejection properties as required for optimum system performance, as well as providing the desired quadrature signal or controlling VCO 55 and the resulting carrier tracking.

FIG. 4 illustrates a second specific embodiment of the general embodiment illustrated in FIG. 2. An input terminal 70 is adapted to receive an MSK or SMSK signal and is connected to first inputs of each of a pair of demodulators 72 and 73. A VCO 75 is connected through a quadrature circuit 76 to second inputs of each of the demodulators 72 and 73. As previously explained, the quadrature circuit 76 supplies reference signals to the demodulators 72 and 73 which are 90.degree. out of phase. The output of the demodulator 72 is connected to a junction 78 which is in turn coupled through a capacitor 79 to a junction 80 and through an inductance 81 to a junction 82. The output of the demodulator 73 is connected to a junction 84 which is coupled through a capacitor 85 to the junction 82 and through an inductance 86 to the junction 80. The junction 82 is coupled through an inductance 90 to an output terminal 91 and to one input of a combining circuit 93. The junction 80 is coupled through an inductance 95 to a second input of the combining circuit 93. A capacitance 96 and resistor 97 are connected in parallel between the output end of the inductance 90 and a reference potential, which in this instance is ground 98. A capacitance 100 and a resistor 101 are connected in parallel between the output end of the inductance 95 and ground 98. The output of the combining circuit 93 is connected through a loop filter 105 to the control input of the VCO 75.

The embodiment illustrated in FIG. 4 is a means for realizing an I/Q form of matched filter at lower data rates, and is commonly referred to as a lumped element circuit. The criss-crossed inductances 81, 86 and capacitors 79, 85 realize the large central lobe of the MSK spectrum, while the output low pass filters composed of inductances 90 and 95, capacitors 96 and 100 and resistors 97 and 101 attenuate the higher frequency lobes. While tedious to analyze, computer simulations have shown that very good approximations to the MSK matched filter are obtained.

A cascade of three one pole filters follow the criss-crossed LC filter of FIG. 4. This cascade represents the low pass filters inherent in monolithic mixers, summers and isolation amplifiers. The degradations for each bandwidth of this one pole cascade are tabulated below:

Other parameter values and configurations result in comparable degradations. For example, a double criss-cross section filter gives about the same degradation as a single criss-cross section when the parameters of both are optimized. Because of the lower number of elements, the single criss-cross is preferable.

Referring specifically to FIG. 5, graphs of the relative degradation in dB versus the tracking error, or phase error, in degrees are illustrated. In a demodulation system such as that shown in FIG. 1, phase error also perturbes the zero crossings of the output of phase detector 12; if the bit sink loop (not shown) is designed to follow this perturbation, sampling occurs at approximately nT-.theta.T/.pi.. In other words the bit sink loop would automatically tend to partially adjust the sampling time to correct for phase errors. The resulting effect on the bit error rate is illustrated in curve A of FIG. 5. In order to achieve the performance of curve A, the exact phase error must be known. Curve B illustrates the resulting effect on the bit error rate of an SMSK demodulator with tracking by bit sink loop, as illustrated in FIGS. 2, 3 and 4. Curve C illustrates the bit error rate for an SMSK demodulator without tracking by a bit sink loop and curve D illustrates the bit error rate of a QPSK conventional demodulator. It can be seen from FIG. 5 that the present SMSK demodulator with tracking loop has substantial advantages over conventional demodulators and, in addition, the circuitry is much simpler and the components can be constructed with a greater tolerance. In addition, the circuit automatically indicates when the system is locked onto the correct signal.

While I have shown and described specific embodiments of this invention, further modifications and improvements will occur to those skilled in the art. I desire it to be understood, therefore, that this invention is not limited to the particular forms shown and I intend in the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.