Sample and Hold Circuit With Improved Offset Compensation

This invention is related to sample and hold circuits useful in metal oxide semiconductor (MOS) integrated circuit data acquisition systems such as digital-to-analog converters.

High resolution metal oxide semiconductor (MOS) integrated circuit data acquisition systems such as digital-to-analog converters require sample-and-hold circuits with input voltage offsets in the low microvolt range and gain accuracy better than 0.01%. Such sample-and-hold circuits comprise a differential amplifier which has an inherent offset between its positive and negative input, giving rise to a permanent offset output voltage which is present even in the absence of an input signal, a significant disadvantage. Conventional techniques for minimizing the output offset voltage require the use of a large, off-chip, compensating capacitor to achieve the required levels of performance.

One conventional technique for minimizing the offset output voltage of a differential amplifier is to store the initial amplifier output offset voltage on the compensating capacitor by connecting the capacitor between the amplifier output and ground. Thereafter, the compensating capacitor is connected between the negative input of the differential amplifier and the output, so that a voltage having the same magnitude and opposite polarity as the amplifier output offset voltage is applied as negative feedback to the amplifier, thus approximately cancelling the offset output voltage of the amplifier. This technique is sometimes referred to as auto-zeroing.

Unfortunately, conventional auto-zeroing suffers from the limitation that the parasitic capacitance between the negative differential amplifier input and ground is charged during the reconnection of the compensating capacitor, which induces a gain inaccuracy in the amplifier output proportional to the parasitic capacitance at the amplifier input divided by the sum of the parasitic capacitance and the capacitance of the compensating capacitor. Accordingly, in order to maintain 0.01% gain accuracy, the capacitance of the compensating capacitor must be on the order of 1,000 pF, which is too large to be included on the integrated circuit, a significant disadvantage.

Another conventional auto-zeroing technique is to first store the offset voltage on the compensating capacitor in the manner previously described, but, instead of connecting the capacitor as an element in the negative feedback loop of the amplifier, the compensating capacitor is instead connected between the positive amplifier input and ground, after which the input signal is applied to the negative differential amplifier input so that the amplifier functions as a negative gain inverting stage. This latter auto-zeroing technique suffers from the disadvantage that the amplifier offset output voltage is not quite zeroed, the offset output voltage merely having been reduced by a factor proportional to the parasitic capacitance at the positive amplifier input divided by the sum of the parasitic capacitance and the capacitance of the compensating capacitor. Accordingly, a very large compensating capacitor must be used in both autozeroing techniques described here in order minimize gain inaccuracies in the first technique or minimize offset output voltages in the second technique, a significant disadvantage.

The effect of parasitic capacitance at the amplifier inputs on offset voltage and amplifier gain accuracy is minimized or removed in the auto-zeroing technique of the present invention. Specifically, the auto-zeroing technique of this invention comprises two steps. In the first step, the differential amplifier output and negative input are shorted together and the resulting amplifier offset output voltage is stored across an input capacitor and a feedback capacitor. The input capacitor is connected between the amplifier negative input and a voltage source to be sampled, and the feedback capacitor is connected beween the amplifier negative input and ground. In the second step, the direct connection between the amplifier output and negative input is removed and the feedback capacitor is reconnected between the amplifier output and negative input in a feedback loop. At this time, a voltage of the same magnitude and opposite polarity as the original amplifier offset output voltage is applied as negative feedback across the amplifier, so that the amplifier offset output voltage is precisely zeroed. The parasitic capacitance at the positive and negative inputs of the differential amplifier do not induce any inaccuracies in the auto-zeroing technique of this invention because the positive and negative input potentials of the amplifier remain unchanged during both the first and second steps so that none of the parasitic capacitances is charged or discharged. Accordingly, the amplifier gain is unaffected by the parasitic capacitances at the amplifier inputs, and so the amplifier offset output voltage is set precisely to zero volts with an accuracy virtually independent of the magnitude of the parasitic input capacitances of the amplifier, a significant advantage.

Thereafter, the voltage source connected to the input capacitor may be sampled at the amplifier output by disconnecting the input capacitor from the voltage source to be sampled and connecting it instead to ground. This produces a voltage at the output of the amplifier which is equal to the ratio of the capacitances of the input and feedback capacitors multiplied by the voltage of the source to be sampled at the time the input capacitor was disconnected from it. The gain of the amplifier is accurately determined by the selection of the input and feedback capacitors and is virtually unaffected by parasitic capacitance.

The invention is best understood by reference to the accompanying drawings, of which:

FIGS. 1a and 1b are simplified schematic diagrams illustrating a first conventional auto-zeroing technique of the prior art;

FIGS. 2a and 2b are simplified schematic diagrams illustrating a second conventional auto-zeroing technique of the prior art;

FIGS. 3a and 3b are simplified schematic diagrams illustrating the auto-zeroing technique of the present invention, in which FIG. 3a illustrates the sample step and FIG. 3b illustrates the hold step of the invention; and

FIG. 4 is a simplified schematic diagram illustrating the preferred embodiment of the present invention.

FIGS. 1a and b illustrate a first conventional auto-zeroing technique for minimizing the offset output voltage of a differential amplifier 10 having positive and negative inputs 10a, 10b and an output 10c. The problem is that if the differential amplifier 10 is to be used in a precision sample-and-hold circuit, an offset voltage V.sub.o will always be present at the output 10c even in the absence of any voltages applied to the inputs 10a, 10b due to an inherent voltage difference between the positive and negative inputs 10a, 10b within the amplifier 10. The object of conventional auto-zeroing techniques is to minimize the offset output voltage V.sub.OUT at the amplifier output 10c so that, ideally, in the absence of any input voltages applied to the inputs 10a, 10b, the offset output voltage V.sub.OUT at the output 10c is equal to zero.

In the first conventional auto-zeroing technique illustrated in FIGS. 1a and b, a compensating capacitor 12 having a capacitance C.sub.0 is connected to the output 10c while the output 10c and the negative input 10b are shorted directly to one another by a direct connection 14. The positive input 10a is grounded. As a result, the offset voltage V.sub.OUT is stored across the compensating capacitor 12. Thereafter, as illustrated in FIG. 1b, the short connection 14 between the output 10c and input 10b is removed and, instead, the compensating capacitor 12 is connected therebetween. However, FIG. 1b shows that the polarity of the capacitor 12 has been reversed with respect to the output 10c. Specifically, whereas plate 12a of the capacitor 12 is connected to the output 10c in FIG. 1a, the opposite capacitor plate 12b is connected to the output 10c in FIG. 1b. Accordingly, the capacitor applies a feedback voltage to the negative input 10b having the opposite polarity and same magnitude as the original offset voltage V.sub.OUT. Therefore, the voltage at the amplifier output 10c is, in the ideal case, zero after the step illustrated in FIG. 1b has been accomplished. However, a parasitic capacitance 16 between the negative input 10b and ground is charged immediately upon reconnection of the capacitor 12 in the step of FIG. 1b. Accordingly, when the positive amplifier input 10a is disconnected from ground and is instead connected to an input voltage source 18 which is to be sampled, the amplifier 10 produces an output voltage V.sub.out which is proportional to the voltage V.sub.in of the source 18 with a gain error on the order of C.sub.p /(C.sub.0 +C.sub.p). This error arises from the fact that the capacitors 12 and 16 function as a voltage divider feedback loop which determines the gain of the differential amplifier 10 in accordance with the formula stated above. The gain error, C.sub.p /(C.sub.0 +C.sub.p) may be minimized by selecting a compensating capacitance C.sub.0 to be extremely large (on the order 1,000 pF). This would make it difficult to place the compensating capacitor 12 on the same integrated circuit with the amplifier 10, a significant disadvantage.

In a second conventional auto-zeroing technique, gain errors are avoided by reconnecting the compensating capacitor 12 between the positive amplifier input 10a and ground and connecting the input voltage source 18 to the negative input 10b. Specifically, the second auto-zeroing technique comprises two steps illustrated in FIGS. 2a and 2b. The first step illustrated in FIG. 2a is fundamentally the same as the step illustrated in FIG. 1a wherein the output 10c and negative input 10b are shorted together while the compensating capacitor 12 is connected between the output 10c and ground and the positive input 10a is also connected to ground. A voltage dividing feedback loop 20, 22 having constant impedances Z.sub.f, Z.sub.n, respectively, may be used to determine the gain of the amplifier 10. In the second step illustrated in FIG. 2b, the compensating capacitor 12 is reconnected between the positive input 10a and ground with its polarity reversed so that a voltage of opposite polarity and same magnitude as the original offset voltage V.sub.OUT is applied to the positive input 10b in the step of FIG. 2b so that the offset voltage at the output 10c is minimized. There is no gain error because the gain has been set by the selection of the impedances Z.sub.n, Z.sub.f. However, parasitic capacitance 16' between the positive input 10a and ground is charged immediately upon the reconnection of the compensating capacitor 12 in the step of FIG. 2b. Accordingly, it may be shown that the new offset voltage present at the output 10c in the step illustrated in FIG. 2b is equal to V.sub.0 C.sub.p /(C.sub.0 +C.sub.p). Accordingly, the offset voltage at the output 10c is not precisely zeroed and can only be minimized by the use of a compensating capacitor 12 having an extremely large capacitance C.sub.0 (on the order of 1,000 pF). Such a capacitor requires a large area on the integrated circuit substrate on which the differential amplifier is formed, a significant disadvantage.

In the present invention, the foregoing disadvantages are overcome in the novel auto-zeroing technique illustrated in FIGS. 3a and 3b. FIG. 3a illustrates the sampling step of the auto-zeroing technique of this invention in which the voltage V.sub.in of the input source 18 is sampled. During the sample step illustrated in FIG. 3a, the offset voltage V.sub.o of the amplifier 10 is stored across an input capacitor 40 of capacitance C.sub.in and a feedback capacitor 42 of capacitance C.sub.f, the input capacitor being connected between the amplifier negative input 10b and the input source 18 and the feedback capacitor 42 being connected between the amplifier output 10c and ground. At the same time, the output 10c and the negative input 10b are shorted together by a direct connection 44 while the positive input 10a is connected to ground. During the step illustrated in FIG. 3a, the offset voltage V.sub.0 is present at both the output 10c and the output 10b by virtue of the direct connection 44 between them. Furthermore, during the sampling step of FIG. 3a, the offset voltage V.sub.0 is stored across the feedback capacitor 42.

Subsequently, a hold-step is performed which is illustrated in FIG. 3b. In this step, plate 42a of the feedback capacitor 42 remains connected to the negative input 10b while opposite plate 42b of the feedback capacitor 42 is disconnected from ground and reconnected instead to the amplifier output 10c. As a result, the feedback capacitor 42 applies the offset voltage V.sub.0 as negative feedback from the output 10c to the negative input 10b. Accordingly, the voltage at the amplifier output 10c at this time is precisely equal to zero. The parasitic capacitance 16" present at the negative input 10b has virtually no effect because the offset voltage V.sub.0 present at the input 10b during the sample step of FIG. 3a remains unchanged in the hold step of FIG. 3b, so that no charging or discharging of the parasitic capacitance 16 occurs during these steps. There is no charging or discharging of the parasitic capacitance 16 because the capacitor plate 42a is never disconnected from the negative input 10b. As a result, the accuracy with which the offset voltage at the output 10c is zeroed is virtually unaffected by parasitic capacitance in the present invention, a significant advantage.

Thereafter, a switch 50 may be used to disconnect the input capacitor 40 from the input voltage source 18 and reconnect the input capacitor 40 instead to ground. The voltage across the input capacitor 40 is reduced by a voltage -V.sub.in determined by the voltage +V.sub.in of the input voltage source 18 at the time the switch 50 was actuated. Accordingly, the output voltage V.sub.out at the amplifier output 10c becomes V.sub.in (C.sub.in /C.sub.f). The ratio (C.sub.in /C.sub.f) is the gain of the amplifier and is determined by the capacitances C.sub.in and C.sub.f which function as a voltage dividing negative feedback loop in the manner well-known to those skilled in the art. If the capacitance C.sub.in and C.sub.f are selected to be equal to one another, the voltage V.sub.out will be precisely equal to the voltage V.sub.in when the switch 50 is moved to the solid-line position illustrated in FIG. 3b. Significantly, the amplifier gain is set precisely by selection of the capacitances C.sub.in and C.sub.f so that gain inaccuracies are effectively minimized or removed in the auto-zeroing technique of the present invention illustrated in FIGS. 3a and 3b. Accordingly, the invention realizes two advantages, namely, the elimination of gain error due to parasitic capacitance and the precise zeroing of the output offset voltage V.sub.o independently of the magnitude of the parasitic capacitance C.sub.p.

FIG. 4 is a simplified schematic diagram illustrating the preferred embodiment of the invention, which is a metal oxide semiconductor circuit formed on a semiconductive substrate and has the capability to perform the sample and hold steps illustrated in FIGS. 3a and 3b. Specifically, the switch 50 permits alternate connection of the input capacitor 40 to the input voltage source 18 and ground, as mentioned previously. The switch 52 permits the alternate connection of the amplifier output 10c to the amplifier negative 10b and to plate 42b of the feedback capacitor 42. The switch 54 permits connection of the feedback capacitor 42b to ground. In the sample step of FIG. 3a, the switch 50 is connected between the input voltage source 18 and the input capacitor 40, and the switch 52 is connected between the output 10c and the negative input 10b while the switch 54 is closed to connect the feedback capacitor plate 42b to ground. During the hold step of FIG. 3b, the position of all of the switches 50, 52, 54 is reversed so that the switch 50 connects the input capacitor 40 to ground, the switch 52 connects the amplifier output 10c to the feedback capacitor plate 42b while the switch 54 disconnects the feedback capacitor plate 42b from ground.

An additional feature of the invention is a switch 56 and capacitors 60 and 62 having capacitance C.sub.in' and C.sub.f', respectively. The switch 56 is operated during the hold step of FIG. 3b to disconnect the positive amplifier input 10a from ground and connect it instead to the capacitors 60, 62. The capacitances C.sub.in' and C.sub.f' are selected to be proportional to the capacitances C.sub.in and C.sub.f of the input and feedback capacitors 40, 42, respectively. The purpose of the capacitors 60, 62 is to provide compensation for the leakage currents I.sub.in- and I.sub.in+ which leak through the switches 56 and 52, respectively, during the hold step of FIG. 3b. Typically, each of the switches 52, 56 is formed as a metal oxide semiconductor field effect transistor (MOSFET). Such a switch typically has junction leakage which is a well-known problem in the art and causes the leakage currents I.sub.in- and I.sub.in+.

In the preferred embodiment of FIG. 4, the amplifier output 10c is connected to a channel charge compensated switch 70 which is described in U.S. Patent application Ser. No. 316,175, filed herewith by Lanny L. Lewyn and Charles H. Lucas and entitled "Channel Charge Compensated Switch with First Order Process Independence" and assigned to the assignee of the present invention. Use of the channel charge compensated switch 70 in place of conventional switches prevents the voltage V.sub.out stored on the amplifier output node 10c in the hold-step of FIG. 3b from being distorted by charge stored in the source-to-drain channel of the switched MOSFET's. Of course, a channel charge compensated switch of the type described in the above-referenced application by Lewyn and Lucas may also be used in place of each of the switches 50, 52, 54, 56 in the preferred embodiment of FIG. 4.

The switch 54 in FIG. 4 may be omitted, and the switches 50, 52 may be operated as described previously, but in synchronism with a clock signal .PHI. of frequency F.sub.c derived from a clock signal generator 80. In this case, the circuit of FIG. 4 becomes a switched capacitor integrator or typical filter element with scale factor .tau.=C.sub.F /(F.sub.c C.sub.in). In this switched capacitor integrator, the switches 50, 52 are operated at the frequency F.sub.C in synchronism with the clock signal .PHI.. During a first phase (or a "reset" phase), the switch 50 is connected to the input voltage source 18 while the switch 52 is connected to the negative input 10b. In a second phase (or an "output" phase), the switch 50 is connected to ground while the switch 52 is connected to the feedback capacitor plate 42b. The output voltage V.sub.out at the amplifier output 10c corresponds to the time domain integral of the signal represented by the voltage V.sub.in of the source 18 with the scale factor .tau. defined previously. Stated mathematically, if the switches 50, 52 are operated in synchronism with the clock signal .PHI., the following obtains: ##EQU1## where

In the switched capacitor integrator of this invention, a major source of dynamic range limitation, mainly 1/f noise of the type well-known in the art, is considerably reduced when the clock frequency f.sub.C is chosen near or above the peak 1/f noise frequency of the amplifier 10. As is well known in the art, the term "1/f noise" refers to that type of noise which is proportional to the reciprocal of the frequency. Although the output voltage of the amplifier 10 is not usable during the reset phase (that is to say, the foregoing equation does not apply during the reset phase) it is a simple matter to follow the amplifier output 10c with a sample-and-hold device (such as the sample-and-hold circuit of the present invention) which retains the previous voltage V.sub.out of the switch capacitor integrator during the reset phase. However, this may not be necessary because, in some application, an output voltage V.sub.out is not required during the reset phase.

In summary, the auto-zeroing sample-and-hold circuit of the present invention stores a sample voltage V.sub.out on its output node 10c which is precisely equal to the amplifier gain (C.sub.in /C.sub.f) multiplied by the voltage V.sub.in of the input source at the precise time that the source was sampled. The voltage V.sub.out at the output node 10c is proportional to the input voltage V.sub.in with a precision virtually unaffected by parasitic capacitance at the amplifier inputs 10a and 10b and with an offset voltage (or bias) which has been zeroed with a precision similarly unaffected by parasitic capacitance.