Method of Selecting PROM Data for Selective Mapping System

This application is related to "SELECTIVE MAPPING SYSTEM AND METHOD," by Thomas J. Gilligan, Ser. No. 279,204, filed June 30, 1981.

1. Field of the Invention

This invention relates to a method or program for assigning data to translation control stores in a mapping system.

2. Discussion of the Prior Art

An advantageous mapping system separates input codes defining input elements of a first set into an A input group and a B input group orthogonal to the A group. Each group is in turn mapped into a K by T map in which the T or translation state partially defines the output mapping state of each mapped element. All of the T states in combination uniquely define the output mapping state. The K or key states in turn uniquely identify each of the elements within an input group which have been assigned to a given T state. A relationship detector in the form of a fault store is addressed by the T states and at each address location stores the key states corresponding to that address. A comparator receives the outputs of the fault store and key stores storing the assigned K states and upon the occurrence of a match indicating that a T code combination corresponds to a current input state of the first set outputs a command causing the current input state to be mapped to an element of a second set defined by the T codes that are generated.

However, the number of mapped states associated with an input code of a first input group cannot exceed the number of T codes associated with the second group. Also, the total number of mapped states assigned to a given T code state of a first group cannot exceed the number of T code states of the second group and once an input group state having given mapped states associated therewith is assigned to a particular T state, another input group state cannot be assigned to the same T state if it has any mapped state in common with a mapped state of an input group state previously assigned to the particular T state.

These restrictions limit the assignment of input group states to K and T codes and hence the utilization of the maximum capacity of a mapping system. For example, in a mapping system with a capacity of 4096 mapped states, the restrictions may prevent the actual mapping of more than 3500 states. The present methods of assigning K and T codes to input group code states helps optimize the probability that a given number of mapped states can be accommodated by a given capacity mapping system.

A mapping system divides encoded input signals identifying elements in a first set, some of which are mapped states which are to be mapped by the system, into an A group and a B group orthogonal thereto. The A group of input signals selects a particular A group superstate from a plurality of A group superstates while the B group of input signals selects a particular B group superstate from a plurality of B group superstates. A and B stores provided for the A and B group respectively output key (K) codes and translation (T) codes upon being accessed by a group of input signals. The A store and B store T code signals define in combination a state or element within a second set to which selected elements of the first set are to be mapped. The K codes identify a particular element in the first set which is to be mapped to a particular element of the second set.

A program in accordance with the invention for assigning K and T codes to the A and B store address locations includes the steps of assigning a B group of input states, each having mapped states associated therewith, to a BK by BT B map in even packing order by maintaining the number of mapped states associated with the input states assigned to each BT state approximately equal; and assigning an A group of input states, each having mapped states associated therewith, to an AK by AT A map in close packing order by maximizing the number of mapped states associated with the input states assigned to the AT state having the most mapped states associated with the input states previously assigned thereto. The input states of the A and B groups are each assigned in sequential order of the number of mapped states associated therewith from most to least. The BT states are arranged in sequential order of the number of available mapped states from most to least and the order is updated after each new assignment of a B input state to the B map. Input states are assigned preferentially to the highest permissible BT state in the sequential order. The AT states are arranged in sequential order of the number of available mapped states from least to most and the order is updated after each new assignment of an A input state to the A map. A input states are assigned preferentially to the highest permissible AT state in the sequential order.

In an alternative program the input states of the A group are first assigned to the A map with even packing and then the input states of the B group are assigned to the B map with even packing. In still another program the input states of the B group are first assigned to the B map and then the input states of the A group are assigned to the A map, both assignments being made with even packing.

Once the input groups are assigned to the A and B maps, the input group states represent the respective A and B address states while the K and T map states corresponding thereto represent the data stored at the corresponding address states.

A better understanding of the invention may be had from a consideration of the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of a data processing system utilizing a data store with an address translator in accordance with the invention;

FIG. 2 is a schematic representation of a selective mapping system in accordance with the invention implemented as a memory address translator;

FIG. 3 is a schematic representation of an alternative embodiment of a memory address translator in accordance with the invention;

FIG. 4 is a schematic representation of an alternative embodiment of a memory address translator in accordance with the invention;

FIG. 5 is a schematic representation of an alternative embodiment of a memory address translator in accordance with the invention;

FIG. 6 is a schematic representation of a three-dimensional alternative embodiment of a memory address translator in accordance with the invention;

FIG. 7 is a two dimension memory map illustrating addresses to be translated for an example in accordance with the invention;

FIG. 8 is a two dimension B Key Data and B Translation Data map for the example in accordance with the invention;

FIG. 9 is a two dimension A Key Data and A Translation Data map for the example in accordance with the invention; and

FIG. 10 is a flow chart illustrating an algorithm for assigning data states to data stores in the mapping system shown in FIG. 2.

Referring now to FIG. 1, a data processing system 10 in accordance with the invention includes a central processing unit 12 connected by a CPU bus 14 to a controller 16. The controller 16 is in turn connected by a peripheral bus 18 to a data store 20. In a conventional manner the CPU bus 14 may also connect to additional controllers or peripheral devices, I/O devices, on memory units. Similarly, the peripheral bus 18 may conventionally connect to other data storage units such as a disk drive or other data store such as the data store 20.

In general, the data store 20 need not be connected through a controller to the CPU bus but could be connected directly to the CPU bus or could otherwise be connected directly to CPU 12 or through a cache memory to CPU 12. However, the address translation feature of the present invention is particularly advantageous for use with a very large data store such as a large core memory manufactured by Ampex Corporation and sold under the trademark "MEGASTORE" for use as a head per track disk replacement or substitute. When so used, the data store 20 is coupled through a peripheral bus such as bus 18 to a disk drive controller such as controller 16. The data store then includes a bus interface circuit 22 which particularly adapts the data store 20 to connection to the particular configuration and signal requirements of the peripheral bus 18. Advantageous embodiments of the data store 20 are described in U.S. Pat. No. 4,238,838 and in U.S. Pat. No. 4,096,583 which has been reissued as U.S. Pat. No. Re. 30,395. A further improvement has been described in application Ser. No. 269,474, filed June 2, 1981 for "RUGGED, VIBRATION RESISTANT MAGNETIC CORE STACK HAVING LOW MASS" by Thomas J. Gilligan.

The data store 10 further includes a bus interface 22, a data storage module 23 having a 512K word by 18 bit main storage module 24 and a 4K word by 18 bit target storage module 26, an address translator 28, and timing and control circuitry 30. The main and target storage modules 24, 26 are advantageously manufactured as a single core memory or other form of data store with a 20th address line A19 causing the selection of address locations within main storage module 24 when at logic 0 and the selection of address locations within the target storage module portion 26 when at logic 1. The main storage module portion 24 of data storage module 23 responds to 19 binary encoded address inputs designated A0-A18 to select one of the 512K words in response to a memory access. Similarly, when address input A19 causes the selection of target storage module portion 26 of data storage module 23, address inputs A0-A18 cause the selection of one of 4K words within target storage module 26. It will be appreciated that address bits A12-A18 are forced false and that only the least significant 12 address inputs A0-A11 plus A19 are effective in the addressing of target storage module 26 since this is all that is required to select one word out of 4K words. The data storage module 23 and timing and control circuitry 30 are generally conventional in nature and respond to signals from peripheral bus 18 communicated through the interface circuit 22 to perform data storage and retrieval operations at address locations indicated by address data bits A0-A19.

Bus interface circuit 22 is conventional in nature and in particular will depend upon the configuration of peripheral bus 18. It operates to provide the necessary signal and timing relationships to meet the bus protocol required for communication on peripheral bus 18 and also to communicate data store access signals received over peripheral bus 18 to appropriate portions of data store 20.

In normal operation data store 20 appears to controller 16 as a 512K by 18 bit data store which is randomly accessible in response to 19 input address bits AI0-AI18. Address translator 28 receives these 19 input address bits or signals and in response thereto outputs 20 memory address bits A0-A19. Most of the time address translator 28 merely operates to convert input addresses AI0-AI18 into corresponding memory addresses A0-A18 with address line A19 at logic 0 to address an indicated word within main storage module 24. However, address translator 28 is arranged to cause the diversion of addresses identifying selected locations within main storage module 24 to addresses identifying corresponding translated address locations within target storage module 26, with address output line A19 at logic 1 to indicate the selection of target storage module 26.

The address translator 28 is thus advantageously utilized to divert addresses selecting a defective word location within main storage module portion 24 to a corresponding nondefective word location within target storage module 26. The correspondence between defective locations within main storage module 24 and nondefective locations within target storage module 26 is preestablished in address translator 28 with the translation being transparent to controller 16 and CPU 12. That is, as far as controller 16 is aware it has sent to data storage 20 an address for a location within main storage module 24 with the corresponding data being accessed. Controller 16 is unaware that the actual address has been diverted or translated to an operable storage location within target storage module 26.

Although the data store 20 responds to only 19 input address lines AI0-AI18 under normal operation, the 20th input address line AI19 corresponding to output line A19 is also connected to bus interface circuit 22 so that it may be driven by an external device. This 20th input address line and the signal thereon is utilized primarily in conjunction with a fault override* (*indicates a logically inverted signal level) signal which is also presented to external components through bus interface circuit 22 to permit the selective addressing of all addresses within data storage module 23. That is, with the fault override* signal at logic 0 the address translator 28 is effectively overridden to produce a direct correspondence between address inputs AI0-AI19 and A0-A19. Data storage module 23 thus appears as a 516K word by 18 bit memory any of the words therein being addressable by the 20 address bits. During the testing phase it thus becomes possible for every word of the data storage module 23 to be written and read for testing purposes without the address translator 28 introducing an uncertainty as to exactly which word location within data storage module 23 is being accessed. Defective word locations within main storage module 24 can thus be logged along with defective word locations that might occur within target storage module 26. This unambiguous detection of defective word locations thus permits address translator 28 to be arranged to translate addresses for defective word locations within main storage module 24 into valid address word locations within target storage module 26 while avoiding defective address word locations within target storage module 26.

The data storage module 23 may be tested in a conventional manner to detect and log defective word locations as well as to establish optimum drive current and sense amplifier threshold operating points and margins therefor. Once the data store 20 is tuned or set to the optimum operating conditions, all defective word locations are noted or logged for use in arranging address translator 28 to divert addresses for defective word locations within main storage module 24 to addresses for valid word locations within target storage module 26.

In one specific example utilizing 9 mil ungraded cores with no rework after wiring, it was found that the optimum nominal threshold was 3.05 millivolts with Y read current set at 180 milliamps and all other drive currents at 200 milliamps. With the sensing threshold margins established between 2.2 millivolts and 3.9 millivolts there were approximately 2262 defective word locations within main storage module 24 which required translation or mapping into valid word locations within target storage module 26. That is, as the actual sensing threshold was varied between the upper and lower margins there were 2262 addresses at which either a 1 was stored and read back as a 0 or a 0 was stored and read back as a 1 under worst case pattern conditions. It naturally happens that as the lower margin is decreased or as the upper margin is increased additional storage locations fail to operate properly. The present example was found to present an acceptable compromise between a reasonable number of errors and adequate operating margins to accommodate aging, temperature changes, and other factors which might affect operation of the memory.

Two power up PROM enable signals PPU 1 and PPU2 are generated by timing and control circuit 30 in response to a conventional module select signal which indicates the addressing of the particular main storage module 24. These signals are peripheral to the actual operation of address translator 28 and merely enable it during periods that it is actually receiving and translating or passing through input addresses and disable PROMs within address translator 28 when not actually being used in order to reduce power consumption. At the expense of greater power consumption the PROMs could be continuously enabled with the signals PPU1 and PPU2 being eliminated.

Referring now to FIG. 2, the address translator 28 includes a 1K word by 4 bit A key PROM 40, a 1K word by 6 A translation PROM 42, a 512 word by 6 bit B translation PROM 44, a 512 word by 3 bit B key PROM 46, and a 4K word by 8 bit fault PROM 48. These PROMs 40-48 store the data required to detect the occurrence of an incoming address for a defective word location in main storage module 24 as well as the data for translating the address to an address for a valid word location within target storage module 26. Since the data is unique for each data store 20 and must be retained throughout the operating life of the data store 20, PROMs provide a convenient and relatively inexpensive apparatus for receiving and permanently retaining this data. It will be appreciated that subject to cost or system application considerations other forms of data storage such as E-PROM, ROM and RAM could be substituted for the PROMs 40-48. In the event that a volatile type of storage is used, it will be apparent that it will be necessary to provide a means of preserving the data during times of shutdown for data store 20 or of writing the required data into the PROM substitutes as part of an initialization procedure upon reactivating data store 20 following a shutdown. This problem is of course avoided by utilizing the permanent, nonvolatile storage characteristics of a PROM.

A first multiplexer 50 receives the least significant input address signals AI0-AI5 at its B input and the six translated address output data bits of PROM 42, AT0-AT5 at its A input. Similarly, multiplexer 52 receives the six input address signals AI6-AI11 at its B input and the six output translated address data bits from translation PROM 44 at its A input. A translate command signal TRANSEN* is normally high to drive the select B inputs of multiplexers 50 and 52 to cause the incoming address signals AI0-AI5 to be output as memory address signals A0-A5 and to cause the incoming address signals AI6-AI11 to be output as memory address signals A6-A11. Upon the occurrence of an active low translate enable signal TRANSEN*, the A inputs of multiplexers 50, 52 are activated to cause the data stored by A translation PROM 42 to drive the least significant memory address bits A0-A5 and to cause the data stored by B translation PROM 44 to drive the memory address bits A6-A11. A multiple input AND gate 54 receives address input signals AI12-AI18 and outputs them as A12-A18 in response to a logic 1 state of signal TRANSEN*, which occurs when no translation is to take place. Consequently, in the absence of a translation, input address signals AI12-AI18 are passed through as memory address signals A12-A18 corresponding thereto and in the event that an address is being translated the translated addresses A12-A18 are output at logic 0. These logic 0 address bits, in conjunction with address bit A19, properly point to the 4K word target storage module 26 and only the lowest order 12 bits are required to identify a word location within module 26.

It can thus be seen that in the event that an address translation is to occur, the six data bits output by A translation PROM 42 and the six data bits output by B translation PROM 44 combine to form the 12 memory address bits A0-A11 required to select a designated word location within target storage module 26. Simultaneously, these 12 address bits are communicated as address inputs to fault PROM 48 to select one of 4K word locations within fault PROM 48. Each word within fault PROM 48 thus corresponds on a 1 to 1 basis with a word within target storage module 26. The 8 bits of an addressed data word within fault PROM 48 are communicated to one set of inputs of a comparator 56 with four bits designated FK0-FK3 being compared to the four data bits designated AK0-AK3 output by A key PROM 40, with three data bits designated FK4-FK6 being compared to three data bits designated BK0-BK2 output by B key PROM 46 and with the eighth data bit designated FK7 being compared to a logic 1 voltage level of +5 V. Upon the occurrence of an identity among the eight pairs of data bits, comparator 56 generates an output designated Fault which indicates that the incoming address has selected a defective location within main storage module 24 and that an address translation is to occur.

Since in any given data store 20, a full 4K defective word locations are not likely to be found within main storage module 24, all 4K word locations within fault PROM 48 and target storage module 26 will not usually be utilized. The eighth bit of fault PROM 48 designated FK7 is thus utilized to indicate whether or not an addressed word location within fault PORM 48 is an address which is actually being utilized for translation. When an address input to fault PROM 48 is one which corresponds to an actual translation word location, the eighth data bit FK7 is set to logic 1 so that it can be successfully compared to the corresponding logic 1 input to comparator 56. This assumes that fault PROM 48 is manufactured with no data or "unburned" data outputs of all 0's. For other types of PROMs which are manufactured with an initial data state of all 1's it would be desirable to change the eighth bit to a 0 to indicate a defective address state so that an affirmative change in the PROM data would be required to indicate a defective address state requiring translation.

Since A translation PROM 42 receives ten binary encoded address bits AI0-AI9 corresponding to 1K words or states and outputs only six binary encoded translated data bits, there are 16 address states (four binary encoded bits) corresponding to each translated address state output by A translation PROM 42. A key PROM 40 receives the ten input addresses and in response generates four binary encoded key data bits which define 16 states to permit the assignment of each of the 16 input addresses corresponding to each translated address state of A translation PROM 42 to one of the 16 states definable by A key PROM 40. Between them, the A key PROM 40 and A translation PROM 42 thus receive ten binary encoded input address bits and output ten binary encoded bits which permit a unique one to one and onto mapping of the 1024 states defined by the input address bits AI0-AI9 to 1024 states defined by the binary encoded output data bits AK0-AK3 and AT0-AT5 of A key PROM 40 and A translation PROM 42.

In a similar manner, the B translation PROM 44 and B key PROM 46 receive 9 binary encoded input address bits AI10-AI18 and provide a unique one to one end onto mapping of 512 states defined by these input address bits to 512 states defined by 9 binary encoded output bits designated BT0-BT5 and BK0-BK2. It will thus be appreciated that the translation PROMs 42-44 provide an address translation from the 19 input addresses AI0-AI18 to 12 output address bits A0-A11. That is, from the set of states defined by input addresses, the subset of states or word locations corresponding to memory defects, is translated or mapped into a second set of states corresponding to word locations within target storage module 26. It will further be apparent that there are 128 input address states (7 bits) for each of the 4K (12 bits) address states within fault PROM 48 and target storage module 26. The A and B key PROMs 40, 46 store 7 bits of key data which permit unique identification of one of the 128 address states corresponding to each combined output of the translation PROMs to be selected as a defective address location and translated to the target storage module 26.

For example, if address 0 is a defective address and is to be translated to the lowest order address within target storage module 26, the A and B translation PROMs 42, 44 would store all 0's at input address words 0 therein. Twelve bits of 0 translated address would thus cause a translation to the lowest order word location within target storage module 26 and also within fault PROM 48. 127 nondefective input address locations would also be assigned to the all 0 translated address state of translation PROMs 42, 44. However, each of these 127 nondefective addresses plus the one defective address would be assigned a unique combination of key data codes amongst the A and B key PROMs 40, 46. The 0 word of fault PROM 48 would then have stored therein the unique combination of seven fault key data bits which match the combination of seven key data bits stored within A and B key PROMs 40, 46 which correspond to the one of 128 input address locations corresponding to translated address state all 0's of the translation PROMs which actually represents a defective storage location. Upon the occurrence of this address, comparator 56 detects a match between all eight pairs of inputs and generates the output signal fault.

This fault signal is coupled as one input to a NAND gate 60 whose output generates the translate command signal TRANSEN* which drives the select B inputs to multiplexers 50 and 52. This signal is also communicated to a NAND gate 62 whose output generates the 20th address signal A19 which determines the selection of either main storage module 24 at logic 0 or target storage module 26 at logic 1.

The FAULT OVERRIDE* signal is received from the bus interface for data store 20 and coupled to selectively disable NAND gate 60 when at logic 0. It is also inverted and coupled to a NAND gate 64 which receives as a second input and input address signal AI19 from the bus interface. The output of NAND gate 64 is coupled as a second input to NAND gate 62 so that upon the occurrence of a logic 0 for signal FAULT OVERRIDE* , the memory address signal A19 is generated in direct correspondence to the input address signal AI19 received at the bus interface circuit 22. It will be apparent that the occurrence of the logic 0 FAULT OVERRIDE* signal will cause the occurrence of a logic 1 TRANSEN* signal which will further cause the memory address bits A0-A13 to be generated in direct correspondence to the incoming address signals AI0-AI18 to permit addressing of all locations within data storage module 23 without interference by address translator 28.

While the address transistor 28 theoretically accommodates 4K errors, there are certain restrictions upon the way in which translation address can be assigned to incoming addresses for defective locations. As a result, the probability of being able to properly assign address translations to accommodate all errors drops significantly when the number of errors exceeds approximately 3500 out of 4096. This results because there are a number of restrictions on the manner in which addresses for defective words within main storage module 24 are translated to addresses for words within target storage module 26. For example, dividing the input addresses AI0-AI9 into an A group and input addresses AI10-AI18 into a B group can be conceptualized as creating a two-dimensional matrix of word locations with the A addresses representing one dimension and the B addresses representing the second dimension. For every A dimension address state there are 9 bits or 512 B dimension address states and the A dimension address states can be thought of as 1024 lines, each representing an A address state, which intersect 512 B dimension lines, each representing a different unique B address state. It is thus possible that there will be up to 512 errors associated with each A dimension address. However, each A dimension address must be assigned a single unique 6 bit translation address by A translation PROM 42 and the multiple defective word locations which may be associated therewith must be uniquely distinguished by assigning each one a different translation address within B translation PROM 44. For example, if 6 defective word locations are associated with a given A dimension address, A translation PROM 42 may store data assigning the translated address of all 0's to that A dimension address. However, each of the associated B dimension addresses which represent defective word locations must be assigned a different B translation address within PROM 44. For example, if the B dimension defective addresses associated with the given A dimension address are 1, 10, 20, 33, 44, and 56, then the corresponding word locations within B translation PROM 44 would be assigned the respective data state 0, 1, 2, 3, 4 and 5. It is thus apparent that even though multiple error locations may be associated with a given A dimension address, that by assigning different data states within B translation PROM 44 to the different associated B dimension addresses, a unique 1 to 1 translation can be made from each incoming address which identifies a defective word location to a translated address within the target storage module 26. However, B translation PROM 44 outputs only 6 bits which define 64 unique states. It is thus possible to accommodate a maximum of 64 defective word locations associated with a given A dimension address line. Furthermore, for each B dimension translated address within B translation PROM 44 there can be associated only 8 different B dimension addresses which are distinguished by the three bits of B key PROM 46. Consequently, as the number of total defective word locations increases toward the maximum capacity of 4096, the probability of having available states within the B PROMs 44 and 46 to accommodate multiple errors associated within a given A dimension address decreases. Similarly, the probability of having available states within the A dimension PROMs 40, 42 to accommodate multiple defective word locations associated with a given A dimension address decreases. A statistical study has indicated that for the arrangement shown in FIG. 2 the probability of being able to accommodate a translation of all defective word locations decreases sharply as the number of defective word locations approaches 3500.

There are a number of restrictions on the assignment of data states to the A and B PROMs 40-46, which effect the accommodation of the theoretical maximum number of errors. These restrictions are that:

1. No more than 64 errors can be associated with each A dimension translate state or corresponding translation address code.

2. No more than 64 errors can be associated with each B dimension translate state or corresponding address code.

3. The assignment of an A dimension address code associated with a defective word location to a translated address within the A PROMs 40, 42 must be a 1 to 1 mapping.

4. The assignment of a B dimension address code associated with a defective word location to a translated address within the B PROMs 44,46 must be a 1 to 1 mapping.

5. The assignment of translated addresses within the A translation PROM 42 to the A dimension addresses and of the translated addresses within the B translation PROM 44 to B dimension addresses must be in such a way that no more than 1 input address defining a defective word location is associated with each combination of an A translation PROM 42 data state and a B translation PROM 44 data state.

An alternative arrangement of an address translator 70 which affords more flexibility in the assignment of translation addresses to input addresses for defective word locations is illustrated in FIG. 3. Although represented in a slightly simplified form, the address translator 70 is essentially the same as address translator 20 shown in FIG. 2 except that an addressable data store referred to as a cross-PROM 72 is inserted between some of the data outputs of A translation PROM 42 and B translation PROM 44 and 6 of the address inputs to fault PROM 48. Cross-PROM 72 is a 128 word by 6 bit store which receives four of the output data bits designated AT3-AT6 from A translation PROM 42 as a first part address input and three of the output data bits designated BT0-BT2 from B translation PROM 44 as a second part address input. The remaining output data bits BT3-BT5 are coupled as address inputs to fault RPOM 48. Cross-PROM 72 thus receives a total of 7 bits of address input which permit unique selection of the 128 words stored therein, only half of which will actually be used.

In general, the 12 bit input and 7 bit output of fault PROM 38 creates a two dimensional array of 4K by 128. Each of the 4K input address states or words must have mapped onto it 128 of the 512K system input address states, not more than one of which is to be translated. The 7 bit key data output determines which one is to be translated.

However, grouping of the input address bits into an A group (AI0-AI9) and a B group (AI10-AI19), while reducing the size of the first stage code assignment PROMS 40, 42, 44, 46, imposes restrictions on the assignment of input address states or words to memory address states or words. The FIG. 2 arrangement in effect creates two, two dimensional arrays, (AK0-AK3).times.(AT0-AT5) and (BK0-BK2).times.(BT0-BT5). Now instead of the freedom to arbitrarily assign the input address states corresponding to defective word locations to one of 4K translation addresses or states, the A group must be assigned to a 64.times.16 array and the B group must be assigned to a 64.times.8 array. Preservation of uniqueness requires that each of the 64 AT states (AT0-AT5) correspond to a maximum of 64 defects which must be distinguished by assigning each to a different one of 64 BT states (BT0-BT5). Similarly each 64 BT states (BT0-BT5) must correspond to a maximum of 64 defects which must be distinguished by assigning each to a different one of 64 AT states (AT0-AT5). These restrictions result in the difficulty of actually assigning more than 3500 errors out of a full capacity of 4096.

The use of cross-PROM 72 in FIG. 3 adds an additional dimension or degree of freedom to the assignment of input addresses to fault addresses that eases these restrictions. The statistical probability is that close to full error capacity can be mapped from the B input address group into the (BT0-BT5).times.(BK0-BK2) second stage array. The limit on successful mapping will most likely occur upon the subsequent mapping of the A address group into the (AT0-AT5).times.(AK0-AK3) second stage array.

In the arrangement of FIG. 3, a 7th output bit is added to A translation PROM 42, thus creating a 128.times.16 (AT0-AT6).times.(AK0-AK2) array into which the A input lines or states may be mapped with relative statistical ease, leaving half of the output states unfilled.

The cross-PROM 72 now creates a set of five third stage arrays or dimensions, (AK0-AK3), (AT0-AT2), (CT0-CT5), (BT3-BT5) and (BK0-BK2).

Each A input address state corresponding to a defective memory location must be definable by a unique combination of (AK0-AK3), (AT0-AT2) and (CT0-CT5) while each B input address state corresponding to a defective memory location must be simultaneously definable by a unique combination of (CT0-CT5), (BT3-BT5) and (BK0-BK2). Cross-PROM 72 thus eliminates the strict requirements of a 64.times.64 array defined by the translation address (AT0-AT5) by (BT0-BT5) and adds additional flexibility which permits a given A or B input state to correspond to more than 64 fault locations or the assignment of input states for defective word locations that might not otherwise be possible to assign because of restrictions.

FIG. 4 illustrates an arrangement of an address translator 80 in which a 512K by 1 fault PROM 82 receives all 19 bits of input address information, AI0-AI18, and outputs a single bit defining translated address bit AT19 and controlling a multiplexer 84. A logic 1 data output from fault PROM 82 accesses the target storage module 26 and causes multiplexer 84 to select the A inputs consisting of translated address bits AT0-AT5 from A translation PROM 42 and translated address bits BT0-BT5 from B translation PROM 44. The remaining A inputs corresponding to outputs A12-A18 are presumed to be logic 0. Multiplexer 84 outputs the low order 19 bits of the translated address, A0-A18. In this arrangement, fault PROM 82 stores a one bit word for each addressable data store word. If the word is defective, a translated address is assigned thereto by the translation PROMs 42, 44 and a one is stoed by fault PROM 82. If the location for a given input address is not defective, a 0 is stored by fault PROM 82. This arrangement is more flexible than the arrangements of FIGS. 2 and 3 in that it imposes no constraints upon the assignment of translated addresses to input addresses for defective word locations. The full capacity 4K words of translated storage in target storage module 26 can always be used. At the same time, the separation of the input addresses into two dimensions significantly reduces the size of the A and B translation PROMs 42, 44. The disadvantage of the arrangement of FIG. 4 is, of course, the large size of the fault PROM 82. 1981 prices for data storage elements implementing the fault PROM 82 render the arrangement of FIG. 4 less economical than the arrangements of FIGS. 2 and 3.

FIG. 5 illustrates an address translator 90 which is still another arrangement of an address translator in accordance with the invention which separates the incoming address signals into multidimensional fields. In the arrangement of FIG. 5, incoming addresses associated with a defective word location are translated to a location within target storage module 26 by the A and B translation PROMs 42, 44. A 4K by 19 fault PROM 92 stores the full 19 bit input addresses for the defective word locations which are being translated. A comparator 94 receives the 19 input address bits or signals as well as the 19 bits of data from fault PROM 92 and upon attainment of a full comparison generates an output signal designated fault which drives the most significant translated address bit A19 and also drives a select A input to a multiplexer 96. Multiplexer 96 receives translated address bits AT0-5 from A translation PROM 42 and translated address signals BT0-BT5 from B translation PROM 44 at its A inputs and the input address signals AI0-AI18 at its B input.

Consequently, each time the translated address output of the A and B translation PROMs 42, 44 addresses a word location within fault PROM 92 which stores the current input address, comparator 94 generates an output indicating that an address translation should be made and causes multiplexer 96 to substitute the 12 bit output of the A and B translation PROMs 42, 44 for the input address. It thus becomes possible to accommodate all addresses by assigning 128 address states to each of the 4K translation states stored by translation PROMs 42, 44 with fault PROM 92 indicating which one of the 128 addresses corresponds to a defective word location which is to be translated with the other 127 addresses being passed through multiplexer 96 unchanged.

FIG. 6 illustrates an address translator 100 which is operationally similar to address translator 20 shown in FIG. 2 except that the input addresses are separated into three dimensions or groups designated A, B and C. Input addresses AI0-AI6 are communicated to a 128 word by 3 bit A key PROM 102 and also to a 128 word by 4 bit A translation PROM 104. The 7 data bits stored by the A PROMs 102, 104 provide a unique 1 to 1 and onto mapping of the input address bits AI0-AI6 into the data states defined by the 7 data bits of the A PROMs.

Input address bits AI7-AI12 are coupled to the address inputs of a 64 word by 2 bit B key PROM 106 and to a 64 word by 4 bit B translation PROM 108. The 6 data bits of the B key and translation PROMs 106, 108 provide a unique 1 to 1 and onto mapping of the 6 input address bits AI7-AI12 into the states defined by the 6 bits of data stored in the B PROMs. In a similar manner a C key PROM 110 and a C translation PROM 112 receive the remaining 6 input address bits AI13-AI18.

As with the arrangement of FIG. 2, the 12 data bits stored by the A, B and C translation PROMs 104, 108, and 112 are combined to generate the translated address signals AT0-AT11 which are communicated to a 4K by 8 fault PROM 114.

At each word location within fault PROM 114 there is stored 7 data bits identifying the particular key states identifying the one of a plurality of key states which are associated with the defective input address which is being translated to the particular word address within fault PROM 114. That is, three of the 7 data bits correspond to three bits stored by A key PROM 102, two of the data bits are associated with the two data bits stored by B key PROM 106 and the remaining two of the 7 data bits corresponds to the two data bits stored by C key PROM 110. The fault PROM 114 also stores an eighth data bit at each word location which indicates whether or not the particularly addressed word within fault PROM 114 represents a translation address or merely an unused address. This eighth bit is communicated as an enable signal to a comparator 116. Comparator 116, when enabled by an indication of a fault address from the eighth bit of fault PROM 114, compares the 7 bits from fault PROM 114 with the corresponding 7 bits from the key PROMs 102, 106, and 110 and generates at its output the most significant address translation signal AT19. This 20th bit is also communicated to the select B input of a multiplexer (not shown) which responds by outputting the 12 data bits from the translation PROMs as the memory address signals A0-A11. In the absence of a logic 1 output from comparator 116 the multiplexer merely passes through the input address signals AI0-AI18 as the memory address signals A0-A18 respectively.

Separation of the input addresses into three dimensions rather than two dimensions does not change the basic operation of the translator 100, but does reduce the total cumulative size of the translation and key PROMs and affect the assignment of translation addresses. For example, in the two dimensional arrangement such as as is shown in FIG. 2, an A address line may have a maximum of 64 defective word locations thereon out of a possible 512. In the arrangement shown in FIG. 6, the A dimension must be conceptualized as combining separately and independently with both the B dimension and the C dimension to define one of 128 BC planes. Each BC plane representing a defective address location must be assigned to one of 16, 16.times.16 BT CT planes, thus accommodating up to 256 errors in a single BC plane out of 4096 input address states. Similarly, each 128.times.64 AB plane representing a defective address location must be assigned to one of 16 AT BT planes and each 128.times.64 AC plane representing a defective address location must be assigned to one of 16 AT CT planes.

The manner in which data states are assigned to the word address locations of the PROMs for the embodiment of the invention shown in FIG. 2 may be better understood with reference to FIGS. 7-9. FIG. 7 illustrates the conceptualization of the separation of the incoming addresses into a first dimension A group and a second dimension B group. The result is a plane with the A group addresses incrementing horizontally from left to right and with the B group addresses incrementing vertically from top to bottom. Each A group address line intersects each B group address line and similarly each B group address line intersects each A group address line. Each of these intersection points represents an input state or word location within main storage module 24. A portion of these word locations are assumed to be defective and have been marked with an *. For convenience of illustration, the defective word addresses have been concentrated in the upper lefthand corner of the AB plane. However, in general it would be expected that the defective address locations would be distributed randomly over the entire AB plane.

In order to facilitate the assignment of translation and key data states to input addresses to the A PROMs and B PROMs it is helpful to list the lines intersecting defective word locations as in Table I and Table II. In Table I each of the B lines which intersects a defective word location is listed in column Bi. Opposite each listed line, there is indicated in column n(Bi) (later called SB) the total number of defective word locations which are intersected by the line. In the next column, designated ABi, there is listed the A line intersections of each of the defective word locations intersected by the given B line. That is, B line B4 corresponding to binary encoded input address 000000100 for address lines AI10-AI18 respectively has an intersection with four defective word locations which occur at A lines A4, A25, A30 and A35. The last, or map order column, lists the B lines sequentially in order of the number of defective word locations which are intersected thereby with the B lines intersecting the most defective word locations being ordered first.

In Table II, column Ai lists the A dimension lines which intersect defective word locations with column n(Ai) (later referred to as SA) listing the number of defective word locations which are intersected by the corresponding lines in column Ai. Column BAi lists the intersections with the B dimension lines at which defective word locations occur. The map order column provides a sequential numerical listing of the A lines which intersect defective word locations in order of the number of defective word locations which are intersected with the greatest number being ordered first.

It is also helpful to utilize the arrays shown in FIG. 8 and FIG. 9 in assigning data states to the A and B PROMs. These figures divide the data contents of the PROMs into a translation data dimension along the horizontal axis and an orthogonal key data along the vertical axis. The B PROMs shown in FIG. 8 have a 64 by 8 configuration and are shown in two sections, one above the other, to better conform the array to the shape of the available drawing space. FIG. 9 illustrates the 64 by 16 array of data states for the A translation PROM 42 and A key PROM 40.

For the present example, data states will be assigned to the translation and key PROMs with an even or level packing for the B PROMs and a close packing for the A PROMs. That is, referring to FIG. 8, an attempt will be made to fill the 64 possible error locations associated with each of the 64 B translation states evenly so that all of the B translation states are filled by an approximately equal amount as B lines are assigned to the FIG. 8 B map. For example, line B4 is assigned to BK0, BT0 and intersects 4 fault locations at A lines A4, A25, A30 and A35. Four of the 64 available fault states are thus cionsumed by this assignment. Until all of the other B translation states BT1-BT63 have at least four fault states mapped thereto there will not be another first attempt to map a second B line to B translation state BT0. The PROM mapping program discussed infra would subtract the four assigned faults from the 64 maximum to indicate 60 available states. Additional B lines are then mapped to B translation states on the basis of the most available fault states. If a conflict prevents mapping to the B translation state with the most available fault states, the B translation state with the second most available fault states is tried and so forth.

Instead of even packing, a close or maximum packing approach is preferred for assigning A lines to the A map as shown in FIG. 9. An attempt is made to first fill all 64 fault states of A translation state AT0, then AT1, then AT2 and so forth. If a conflict prevents mapping of an A line to AT0, an attempt is made to map it to AT1, then AT2 and so forth. The most dense assignment of faults to A translation states thus occurs at the lower numbered states with the possibility of the higher numbered states having no faults assigned to them. The encoded A translation bits are then made the most significant address inputs to the target storage module 26 and to the fault PROM 48. If, for example, the top eight A translation states AT56-AT63 remain empty, then the last 512 words of fault PROM 48 will never be addressed and need not be implemented, thus reducing the cost of the translator 28, which is implemented with 512 word by 8 bit modules. In general the amount of fault PROM 48 that can be eliminated, if any, will depend upon the number of input address states that must be translated and the efficiency with which they can be assigned to the lower ordered A translation states without conflict. If the last 16 A translation states AT48-AT63 were to be left empty, then the last 1K words of fault PROM 48 could be left unimplemented. In addition to the possible reduction in fault PROM 48 costs it is believed that even packing of the B lines into the B map increases the number of A lines that can be assigned to the A map without conflict, the mapping of A lines without conflict being the most likely limit upon the maximum number of fault states that can be mapped.

Although the A and B dimension lines which intersect no defective word locations are not explicitly shown in the tables and drawings, these are also assigned states in the A and B arrays in accordance with the one to one and onto mapping. However, because there is no problem of avoiding multiple B lines associated with A lines and multiple A lines associated with B lines in the assignment of nondefective addresses (there being no assignment of a corresponding key state in fault PROM 48) there will never be any problem assigning A or B lines which do not intersect a defective word location to its respective A or B array data state. These lines may simply be assigned last (they intersect 0 word locations) to any data state which is available after the assignment of address lines which do intersect defective word locations.

The A and B address lines which do not intersect defective word locations actually represent a don't care situation and alternatively all such A addresses could be assigned to a single data state within the A array and all such B addresses could be assigned to a single data state within the B array. It is simply necessary to assure, that in programming the fault PROM 48, that the corresponding word location therein is programmed to assure that comparator 56 does not produce a match so that no address translation occurs for these A and B lines which do not intersect a defective address location.

In the present example, after all of the B address lines have been assigned to the B array in FIG. 8, the A address lines will then be assigned to the A array in FIG. 9. While the above process is conceptualized as assigning A lines to the AK.times.AT A map and B lines to the BK.times.BT map, it should be remembered that actually the A lines are input address states or word locations for the A PROMs 40, 42 and the AK and AT states are the data assigned to the corresponding word locations in encoded form. Similarly, the B lines represent input address states or word locations for the B PROMs 44, 46 and the BK and BT states represent the data stored in the corresponding word locations in encoded form.

Referring now to Table I, the map order column indicates that B dimension line B4 is the first to be assigned. This being the first entry, there is no possible conflict and line B4 is assigned to data state 00. That is, B key data BK equals 0 and B translation data BT equals 0. Line B4 intersects four defective word address locations corresponding to A lines A4, A25, A30, and A35. This data along with the total number of errors is indicated in the array space provided in FIG. 8 for the B array at location 0,0.

The second entry in Table I in map order is B liine B17 which intersects four defective word locations at A lines A16, A29, A30 and A31. B line B17 is readily assigned data state 0,1 in the array shown in FIG. 8 and the associated total number of defective word locations and corresponding A line intersections are indicated therein. Since this is the first entry into BT1 there are no possible conflicts from the assignment of the same associated A line to BT1 twice.

Line B18 has associated therewith four defective word locations at intersections with lines A29, A30, A31, and A35. In accordance with the preestablished pattern of evenly filling the 64 fault states for each B translation state, line B18 is entered at B map location 0,2. The four defective word locations and corresponding A line intersections are indicated in the available space. Again, the first entry into a given translation state poses no conflicts unless the number of associated faults for a B line exceeds 64.

Table I indicates that the next B line to be assigned is line B19. Line B19 has associated therewith four defective word locations at the intersection with lines A27, A29, A30 and A31. Line B19 can be assigned data state 0,3 in the B array shown in FIG. 8. In a similar manner all of the B lines listed in Table II can be assigned a data state in the B array shown in FIG. 8 with care being taken that the B line is not assigned to a BT column such that the A lines associated therewith are also associated with a B line previously assigned to the same column.

In the present example there have not been a sufficient number of errors to provide entries in all of the BT columns. However, in an actual memory it would be expected that most of the 512 B lines would have at least one fault associated therewith. After the first 64 B lines have been located on the B map it will be necessary to map the 65th B line into a BT column already occupied by a B line. The BT column having the fewest number of fault states assigned thereto is selected first and will quite likely be column BT63. Deviating from the present example to illustrate the point, assume that BT63 has assigned thereto line B14 with four fault intersections at A10, A75, A76 and A200. Column BT62 might have line B510 assigned thereto with five fault intersections at A10, A35, A501, A729 and A1023. All other BT columns would have a B line mapped thereto with five or more associated faults.

The next or 65th B line to be mapped might be line B485 with four fault intersections at A25, A75, A501, and A842. Column BT63 would receive the first mapping attempt since it has the fewest number of fault states mapped thereto. However, fault A75 associated with line B485 conflicts with fault A75 associated with previously mapped line B14. The next least occupied BT column is then selected, which might be column 62. However, fault A501 associated with line B510 conflict with fault A501 associated with line B485 so column B62 cannot be used. Additional columns, such as BT61, are attempted until line B485 can be mapped without a conflict from the associated faults. A conflict would be equivalent to assigning the same translated address to two different input addresses identifying defective storage locations.

After completion of the B map, the A lines are assigned to the A map as shown in FIG. 9. The process is essentially the same except that each A line is assigned to an AT state with as low a number as possible of available fault vacancies instead of evenly to the AT state with the most available fault vacancies out of 64 possible.

Referring to Table II, line A27 is the first to be assigned with four faults at B19, B20, B21 and B22. It is assigned without conflict to location 0,0. Next is line A30 having four faults at B4, B17, B18 and B19. Fault B19 conflicts with fault B19 of line A27, forcing assignment to location 0,1. The third line to be assigned is A35 with three fault intersections at lines B4, B6 and B18. Line A35 can be assigned to location 1,0, the first location attempted. Next, A29 is assigned to location 0,2 and the process continues with each line being assigned to the lowest number nonconflicting AT state until all A lines have been assigned to the A map as shown.

After all of the A lines associated with faults have been mapped, the remaining lines, such as A0 can be mapped to the remaining available AK, AT states.

The arrays shown in FIGS. 8 and 9 now define the data which must be entered into the A and B PROMs. Referring to FIG. 8, it will be seen that address B4 is assigned data state 0,0 (modulo 64). Address word 4 within B translation PROM 44 is thus loaded with 0 (modulo 64) and address word 4 within the B key PROM 46 is loaded with data state 0 (modulo 8) also. Continuing with the B array it can be seen that address word 17 of B translation PROM 44 is loaded with data state 1 (modulo 64) while address word location 17 within B key PROM 46 is loaded with data state 0. Similarly, it will be seen that address locations 18, 19, 6, 3, 27 and 5 within B translation PROM 44 are loaded with data states 2, 3, 4, 5, 6 and 7 (modulo 64) respectively. Data state 0 is loaded into the B key PROM 46 for all of these address locations. Similarly, the A array shown in FIG. 9 shows the data states for the A translation PROM along the horizontal axis and the data states for the A key PROM 40 along the vertical axis with the corresponding A input addresses being indicated at the intersection areas. That is, data state 0,0 is loaded into the A key PROM 40 and A translation PROM 42 at address location 27. At A input address 30 data state 1 (modulo 64) is loaded into the A translation PROM 42 and data state 0 is loaded into the A key PROM 40. In a similar manner, the proper data state is loaded into the address word locations in the A PROMs 40, 42 for each input address.

The data contents of fault PROM 48 can be derived from the A and B arrays shown in FIG. 9 and FIG. 8. For example, fault PROM address 0,0 corresponds to A array column AT0 and B array column BT0. This corresponds to defective error location A35, B4. In the A array, address A35 corresponds to A key data 1 so that 1 (modulo 16) must be loaded into the first four bit positions of fault PROM address 0,0. Similarly, in the B array, line B4 corresponds to BK=0 so that 0 (modulo 8) must be loaded into the next three data bit positions of address 0,0. Finally, a 1 is loaded into the eighth bit position to indicate that this address corresponds to a defective word location which requires translation into the target storage module 26. For PROMs having an unburned state of all 1's, a 0 would probably be used to indicate a valid translation state.

Similarly, fault PROM address 0,1 corresponds to A array column AT0 and B array column BT1. Defective address location A16, B17 is common to these columns. Address A16 is assigned A key data state AK1 so that 0001 must be loaded into the first four bits of fault PROM address location 0,1 (modulo 64). Address line B17 corresponds to B key data state BK so that 000 is loaded into the next three bits of word location 0,1 (modulo 64) in fault PROM 48. The eighth bit of this word location is loaded with a 1 to indicate that it represents a defective address location requiring translation into target storage module 26. In similar manner, each defective word location corresponds to a unique combination of an A array column AT and a B array column BT. This combination defines an address in the fault PROM 48 with the data at the address being loaded with the corresponding four bits of A key data, three bits of B key data and a 1 to indicate the correspondence to an address for a defective word location which requires translation into the target storage module 26. Not all of the available 4K locations in fault PROM 48 are utilized and the unused locations such as address 0,8 (modulo 64) are loaded with a 0 in bit number 8 to indicate that an address translation is not to be made and to inhibit a fault output from comparator 56. Table III illustrates the data contents of the fault PROM 48 for each of the active addresses in the present example. The column labeled defective address indicates the intersection of the A line and B line to which the defective word location for the address being translated corresponds.

In operation of the address translator 28, assume that address 0000000100 000000100 corresponding to two dimensional address A4, B4 is received by data store 20 from controller 16 along with an appropriate read or write command. This causes address location 4 within A key PROM 40 and A translation PROM 42 to be accessed. These PROMs store 0001 and 000010 respectively at these locations. Similarly, this input address causes location 4 within B key PROM 46 and B translation PROM 44 to be addressed. These locations also store 000 and 000000 respectively. As a result, A translation PROM 42 presents the six bits 000010 to fault PROM 48 and to the A input of multiplexer 50. Similarly, B translation PROM 44 presents the six bits 000000 to fault PROM 48 and also to the A input of multiplexer 52. At the same time, A key PROM 40 presents the four bits 0001 to comparator 56 while B key PROM 46 presents the three bits 000 to comparator 56. The twelve bits of data provided to the address input of fault PROM 48 cause address location 2,0 (modulo 64) to be addressed and, as shown in Table III, fault PROM 48 responds by presenting the eight bits 10001 000 to comparator 56. These eight bits of data match the other eight bits of data received by comparator 56 causing comparator 56 to generate a logic 1 fault signal at its output. This signal is inverted by NAND gate 60 to a logic 0 level to cause multiplexers 50 and 52 to select their A inputs for output as translated memory address signals A0-A5 and A6-A11 respectively. The logic 0 output of NAND gate 60 is further inverted by NAND gate 62 to generate the twentieth memory address signal A19 at a logic 1 level to cause the data storage module to select the target storage module portion 26 thereof. The input address A4, B4 is thus translated to translated memory address location 2,0 (modulo 64) within the target storage module 26 which then proceeds to read or write data at that address location therein in a manner which is transparent to the controller 16 except for a slight time delay of approximately 1/4 microsecond which is required to accomplish the address translation.

The data assignment program must operate to assign the A input line states to the A map (FIG. 9) and the B input line states to the B map (FIG. 8). Once these assignments are made the data content of the A, B, and fault PROM are inherently defined and the lists required for programming or "blowing" these PROMs are readily derived. The assignment of A and B input states to the A and B map must be consistent with the following rules:

1. No more than 64 (NBT) errors (mapped element) can be associated with each A input code. This is because a single A input code must be assigned to a single AT column in the A map and multiple errors associated therewith must be distinguished by assignment of the corresponding B input line states to different BT columns in the BT map. There are 64 BT columns in the B map in the present arrangement.

2. No more than 64 (NAT) errors (mapped element) can be associated with each B code. This is simply the converse of No. 1 above.

3. The assignment of an A input line state having a fault or mapped element associated therewith to the A map must be a one-to-one mapping.

4. The assignment of an input B line state having a fault or mapped element associated therewith to the B map must be a one-to-one mapping.

5. The A input line and B input line assignments to the A and B map must be in such a way that no more than one fault or mapped element is associated with each combination of a BT column and an AT column.

A statistical study has indicated that these restrictions limit the actual number of states that can be translated to something less than the actual hardware capacity (4096 in the present example). An algorithm that will map approximately 3500 elements out of a maximum capacity of 4096 with a probability in excess of 99%, is illustrated by the program flow chart shown in FIG. 10. A listing of a corresponding program in the BASIC programming language is set forth in Table V hereafter. Table IV provides a definition of important terms used in the algorithm flow chart while Table VI provides a correlation between the terms defined in Table IV and the terms used in the program set forth in Table V. Limitations on the use of variable names inherent in the basic program language necessitated a substitution of terms in many instances.

The algorithm shown in FIG. 10 first assigns the B input codes to the B map in the order of the most to least fault states or mapped elements which are associated with each B code. The algorithm then assigns the A input codes to the A map in order of most to least fault states or mapped elements associated with each A input code. Because there are half as many B input lines as A input lines, there are twice as many fault states per line and the probability of a successful mapping of a large number of errors is therefore diminished. Mapping of the B lines first eliminates restrictions that might otherwise be imposed by the prior mapping of A lines and thereby increases the probability of successfully mapping a given number of B lines. The B lines are mapped within an even packing in which a next B line is preferentially assigned to a BT column state in the B map having the most available fault states, there being 64 total. The BT columns are listed in sequential order by number of available fault states and if a conflict prevents a mapping to the BT column with the most fault states, the next and then subsequent BT columns are attempted and until a successful mapping is achieved or all BT columns have been exhausted.

After the B input lines are mapped, the A input lines are mapped with a close packing. A input lines are also mapped in order of most associated mapped states to least. The A input lines are mapped with a close packing order in which an attempt is made to first fill the AT0 state, then the AT1 state, then the AT2 state and so forth. This close packing is believed to optimize the probability of successfully assigning all of the A lines to the A map where a large number of mapped states are involved. Close packing further has the advantage of potentially leaving the high numbered AT states with no mapped element or fault assignments empty in the event that less than the full capacity of mapped states are being mapped. It may then be possible to reduce the cost of the translator 28 by not having to physically implement the high order address locations of fault PROM 48.

A total of 2300 mapped elements can be accommodated relatively easily and the program has a provision to reduce running time by simply treating the AT elements in sequential order from AT0 to AT63 if the total number of errors to be mapped is less than 2300. However, if the total number of errors exceeds 2300 the sequential order of the AT elements is initialized at AT0 to AT63 and modified to reflect faults in target store 26, but is updated after each A line entry to maintain the sequential order from the greatest number of fault states or mapped elements to the least number of available fault states or mapped elements. The first alternative is in effect an approximation of the second, preferred alternative, which reduces program running time.

In the event that the program is unable to assign a given B line to the B map or a given A line to the A map because of a conflict, the preceding input line is deleted from the map assignment and interchanged in sequential order with the unassigned input line. If the unassigned input line is still unassignable, the next preceding input line is deassigned from its corresponding map and interchanged in the sequential order of assignments with the unassigned input line. This process continues until the unassigned input line is assigned without conflict. The normal assignment process then resumes with the input lines which had been deassigned being reassigned to the corresponding map.

The number of each unsuccessfully assigned line is stored in an array E1(I) to preclude an endless loop where each of two lines may be assigned only after the other has been deassigned.

Referring now to FIG. 10, it will be seen that the data assignment program is divided into three main parts designated ADTRAN I, II and III. The use of three parts is not related to the algorithm, but merely accommodates restrictions imposed by the particular computer from which the program has been run. The three parts are simply chained together to provide one total program.

The program begins by accessing the input file designated ADDR.U. which contains the list of defective addresses or mapped elements which must be mapped from the input set of addresses to the output set of addresses. This list is utilized to generate a first file for the B group of input addresses, designated B.FREQ.DAT and a second file for the A group input addresses designated A.FREQ.DAT. These files have the general form of the first three columns of Table I and Table II and for each record list the input line number (whether or not there is a defective address location associated with the line) the number of defective address locations or mapped elements associated with the line, and the A input line intersection with the given B input line at each defective address location.

The program next generates the working file BSEQ.DAT which is derived from the B.FREQ.DAT file and lists the input address lines in sequential order from the greatest number of associated defective addresses to the least number of associated defective addresses. That is, a line intersecting 4 defective address locations such as line B4 in FIG. 7 would be listed ahead of a line intersecting 3 defective address locations such as line B6. This completes the first portion of the program designated ADTRAN I.

The program then chains to ADTRAN II which proceeds to assign the B group of input addresses to the B map, a table TB(I,J) storing data similar to FIG. 8. The program obtains the next input B line from the BSEQ.DAT information and obtains the next BT state from a linked list FPBC(I) which maintains the BT states in order of most available vacancies for receiving mapped elements or faults. After checking to be sure that the number of defective address locations associated with the current B line does not exceed the maximum number which can be mapped (64), the program tests for conflicts with previous assignments. That is, the current B line cannot be mapped to the current BT state if a fault location associated with the current B line corresponds to a fault location associated with a B line which has been previously mapped to the same BT state. If a conflict exists, the program returns to point B where a next BT state is obtained from the FPBC(I) linked list and this BT state is tested for conflicts.

When a BT state with no conflicts is found, the current B input line is assigned to that BT state at a KB key state indicated by a variable IBR(J) which indicates the next available BK row in the B map for each BT column, J. After the assignment to the B map the IBR(J) variable is updated by incrementing the element corresponding to the BT column to which the B input line was assigned. A second variable, MBC(J) stores the number of available vacancies for receiving faults or mapped states associated with each BT column. This variable is initialized at 64 and upon entering a B line to the B map, is updated by subtracting the number of fault locations associated with the assigned B line from the element of MBC corresponding to the BT column to which the B line have been mapped. The FPBC(I) linked list is then updated to maintain the BT columns in order of most available vacancies for receiving faults (MBC) to least available vacancies for receiving faults and the program returns to point A where a next B is obtained and tested for conflicts.

In the event that the program is unsuccessful in assigning a given B input line to any of the 64 BT columns, the program branches to locate the most recently assigned B line in the B map, TB(I,J). After this most recently assigned B line is located, it is deassigned with the associated variables such as IBR and MBC being updated to reflect the deassignment and the deassigned line is interchanged in order with the unsuccessfully assigned B line in the BSEQ.DAT file. The program then returns to point A to start over in its attempt to assign the unsuccessful B line with the sequential order of the unassigned B line moved up by one. Upon completing the assignment of all B lines to the B map, the program proceeds to point 3 where PROM files BK(I) and BT(J) are written. The BK file merely provides a sequential list of key row assignments in the B map, TB(I,J), in order or the B input line number. The BT file provides a sequential listing of the BT column assignments associated with each B input line in the order of the B input line number. The second part of the program then terminates with the generation of an ASEQ.DAT file from the A.FREQ.DAT file information.

Part III begins by obtaining the next A input row, the next AT column in the A map, and the associated B and BT column for each fault associated with the current A input line. This information is utilized to access input data files to determine if the AT column has an available BK row state and a sufficient number of unassigned vacancies for receiving fault states, MAC(J), to receive the A line entry and whether the A line entry would result in translation to an address within target storage module 26 which is defective. If the address is defective the next AT column is selected. A test is also made for conflicts between the B lines associated with the current A line and those associated with A lines previously assigned to the proposed AT column. If there are no test failures, the B row file (BK) is read for each B line which intersects the A line at a fault location, the A line is assigned to the A map, and for each combination of AT, BT corresponding to an error on the A input line, the terms 1, BR, and AR are written into the fault array F. The one indicates that the associated address corresponds to a mapped element or fault state and is to be translated, B row is the BK row state to which the B line is assigned and AR is the AK row state to which the A line is assigned. The F array thus defines the content of fault PROM 48.

The program then continues to point 4 where the FPAC(I) linked list is updated to reflect the most recent A line assignment and a test is made for the assignment of all A lines. If no, the program continues to the beginning of ADTRAN III to assign the next A line. If the last A line has been assigned, the program continues to write PROM files AK, AT, Fault, and Statistics. The AK and AT files correspond to the BK and BT files to define the content of the A key PROM 40 and A translation PROM 42. The fault file corresponds to the content of the fault array and defines the data for fault PROM 48. The statistics file merely stores data relating to the execution of the program and is not a material part of the data assignment algorithm.

In the event that a conflict precludes the assignment of an A line to one of the 64 AT column locations in the A map, the program branches to deassign the most recently assigned A line and interchange it in sequential order with the unsuccessfully assigned A line. This procedure is essentially the same as that for an unsuccessfully assigned B line.

The above described arrangements operate by translating the address for a complete 18 bit word any time a defect occurs within any one or more of the bits of the word within the main storage module 24. This results in some inefficiency in that 18 bits must be reassigned or translated when even one of 18 bits of the original word location is defective. It would of course be possible to subdivide each addressed word into groups of one or more bits with additional address lines or bits being assigned to select only one of these groups for address translation to avoid having to provide 18 spare bits to accommodate a single defective bit. However, in the present example of a core memory it has been found practical and cost effective to translate a complete word of stored data any time a single bit within the word is found to be defective. This is particularly true in the case of a core memory where data is accessed on a word at a time basis and the separation of data for a single output word into two internal words would require two memory cycles to generate the single output word. This would significantly slow effective memory cycle time. It should be further appreciated that even though a 1/4 microsecond delay is associated with the address translator 28, where a plurality of memory cycles are to occur in succession, the delay for a next memory cycle can overlap the cycle time for a preceding memory cycle. When properly arranged, the 1/4 microsecond delay thus affects only access time and not the data transfer rate.

While there have been shown and described above various arrangements of systems for selectively mapping a subset of a first set into a second set in the form of memory address translators, it will be appreciated that the invention is not specifically limited thereto. Accordingly, all variations, modifications, and equivalent arrangements within the scope of the accompanying claims should be considered to be within the scope of the invention.