Frequency Demodulator Employing a Circuit Having a Delay Varying With the Received Frequency

The invention relates to a frequency demodulator comprising a first gate circuit having an "exclusive-OR" function and receiving at its two inputs square-wave signals having the frequency of the frequency-modulated signal, delay means for delaying one of said square-wave signals relative to the other, and a low-pass filter connected to the output of the first gate circuit.

A frequency demodulator is, for example, used to recover data transmitted by frequency shift keying a carrier.

A frequency demodulator of the above-defined type is disclosed in, for example, U.S. Pat. No. 3,778,727. In prior art demodulators of this type, a delay circuit is employed to produce a fixed delay of one of the square-wave signals applied to the "exclusive-OR" circuit. This fixed delay is equivalent to a phase shift of the delayed signal proportional to the frequency. A pulse-shaped signal formed by pulses appearing at the transition instants of the non-delayed signal and having a fixed duration is obtained at the output of the "exclusive-OR" circuit. The low-pass filter connected to the output of the "exclusive-OR" circuit supplies the average value of this pulse-shaped signal, which average value is proportional to the phase shift between the delayed and non-delayed signals and consequently proportional to the frequency of the modulated signal. The fixed delay can be realized by means of a shift register in accordance with the technique employed in the above-mentioned U.S. Pat. No. 3,778,727 or by means of any type of analog delay circuits.

Such a demodulator has a response which is basically linear if the delay .tau. is independent of the frequency F of the modulated signal, which however is not always easy to realize by means of delay circuits of an analog type. However, in view of the fact that its response is of necessity zero for F=0 and at its maximum for F=1/2.tau., it has the drawback that it only produces a relatively weak variation of its output signal as the frequency range .DELTA.F of the modulated signal is relatively narrow and far remote from the frequency F=0.

It is an object of the present invention to avoid this drawback by providing a demodulator, the response of which can easily be adapted to the frequency range of the frequency-modulated signal.

According to the invention, in said demodulator the delay means are arranged so as to produce a delay varying versus frequency in such a way that the absolute value of the phase difference between the square-wave signals varies at most from 0.degree. to 180.degree. inversely with respect to change in frequency.

The means producing a delay varying versus frequency can be realized in a simple manner and at relatively low cost by means of analog circuits. Two analog embodiments of the frequency demodulator in accordance with the invention will be described hereinafter.

The invention will now be further described in detail by way of non-limitative example with reference to the accompanying drawings, in which:

FIG. 1 is a basic circuit diagram of the type of frequency demodulator utilized in the invention;

FIG. 2 shows diagrams of the signals appearing in the circuit diagram of FIG. 1;

FIG. 3 is a circuit diagram of a first embodiment of the demodulator in accordance with the invention;

FIG. 4 shows diagrams of the signals appearing in the circuit diagram of FIG. 3;

FIG. 5 is a circuit diagram of a second embodiment of a demodulator in accordance with the invention; and

FIG. 6 shows diagrams of signals appearing in the circuit diagram of FIG. 5 .

FIG. 1 shows the basic circuit diagram of a frequency demodulator of the type utilized in the invention. By way of example it is assumed hereinafter that this demodulator is employed to recover data transmitted by means of frequency modulation of a carrier. The frequency modulated signal e(t) is applied to an amplitude limiting circuit 1, which produces a square-wave signal of amplitude U which has the frequency F of the modulated signal e(t). An "exclusive-OR" circuit 2, fed by the voltage U from a supply source, receives at one input the square-wave signal V.sub.a supplied by the limiting circuit 1 and at its other input the signal V.sub.r supplied by a delay circuit 3 which delays the signal V.sub.a by a time .tau.. The non-delayed signal V.sub.a, which has a period T=1/F, is shown in diagram 2a of FIG. 2. The signal V.sub.r, which is delayed by time .tau., is shown in diagram 2b of FIG. 2 for the case where 0<.tau.<T/2. The pulse-shaped signal V.sub.j, which is formed by pulses having an amplitude U and follows the transitions of the non-delayed signal V.sub.a, is obtained at the output of the "exclusive-OR" circuit 2, as shown in diagram 2c of FIG. 2. These pulses have a width .theta.=.tau.. Diagram 2d of FIG. 2 shows the delayed signal V.sub.r for the case where T/2<.tau.<T, and diagram 2e shows the pulse-shaped signal which is obtained at the output of the "exclusive-OR" circuit 2; in that case the pulses of the signal V.sub.j precede the transitions of the non-delayed signal V.sub.a and their width is .theta.=T-.tau.. It is obvious that in all cases the duration .theta. of the pulses of the signal V.sub.j is at least zero and does not exceed T/2. The pulse-shaped signal V.sub.j produced by the "exclusive-OR" circuit 2 is applied to the low-pass filter 4 which supplies the average value thereof. Said average value of the signal V.sub.j is the output signal U.sub.s of the demodulator, which is shown by means of dotted horizontal lines in the diagrams 2c and 2e of FIG. 2. It is easy to demonstrate that the signal U.sub.s has for its expression:

In the prior art frequency demodulators, the delay circuit 3 produces a delay .tau. of a fixed duration and said delay is produced, for example, by a shift register described in the above-mentioned U.S. Pat. No. 3,778,727. From formula (1) it will be seen that the output voltage U.sub.S of the demodulator is proportional to the frequency F of the frequency-modulated signal. In order to recover the data transmitted by assigning two frequencies F.sub.A and F.sub.B to a carrier, the signal U.sub.S is applied to the inverting input of an operational amplifier 5, whose non-inverting input receives the fixed voltage v.sub.o. Said amplifier 5 fed by the voltage U operates as a comparator which, by comparing the voltage U.sub.S with the threshold voltage V.sub.o, recovers the data corresponding to the frequencies F.sub.A and F.sub.B.

In order to judge the performances of said demodulator it is customary to define the variation .DELTA.U.sub.S of the output signal for a frequency shift from F.sub.A to F.sub.B of the modulated signal. It will be clear that then:

It is alternatively possible to define the average value V.sub.m of the output signal U.sub.S, it being assumed that the two possible values of said signal U.sub.S for the frequencies F.sub.A and F.sub.B are equally probable. This average value V.sub.m is written:

It is of course advantageous when the threshold voltage V.sub.O applied to the comparator 5 would be equal to said average value V.sub.m.

By introducing the center frequency F.sub.o =(F.sub.A +F.sub.B)/2, the variation U.sub.S of the output signal of the demodulator may be written in relation to its average value V.sub.m : ##EQU1##

This last formula reveals a characteristic of this prior art demodulator, namely that the relative value of its output voltage .DELTA.U.sub.S /V.sub.m only depends on the relative difference (F.sub.A -F.sub.B)/F.sub.o which is a drawback when said relative difference (F.sub.A -F.sub.B)/F.sub.o is rather weak. During data transmission the following frequency values are, for example, employed: F.sub.A =1850 Hz, F.sub.B =1650 Hz. Thus, .DELTA.U.sub.S /V.sub.m .apprxeq.11.4%. When V.sub.m =6 V, then .DELTA.U.sub.S .apprxeq.0.68 V. In this example the voltage U.sub.S therefore assumes, as a function of the data, in the adjusted operating mode, the two values U.sub.SA =6.34 V and U.sub.SB =5.66 V which in the comparator 5 must be compared with the voltage V.sub.o =V.sub.m =6 V. It will be obvious that noise and offset affecting the signal U.sub.S or generated in the comparator 5 may cause important bias distortions in the data recovered by said comparator.

The present invention provides a frequency demodulator which can be easily adapted to the frequency range of the modulated signal to obtain variations .DELTA.U.sub.S of the output signal which are much larger than in the prior art demodulator.

In accordance with the invention, the delay circuit 3 produces a delay .tau. varying versus frequency F in such a way that the absolute value of the phase difference between the square-wave signals V.sub.a and V.sub.r applied to the inputs of the "exclusive-OR" circuit 2 varies at most from 0.degree. to 180.degree. inversely with respect to the frequency F.

To show clearly the difference with the prior art demodulator, the output voltage U.sub.S of the demodulator can be expressed as a function of the phase difference .phi. between the two signals V.sub.a and V.sub.r applied to the two inputs of the "exclusive-OR" circuit 2, said phase difference .phi. always being counted in positive way and limited to 180.degree.. The formula (1) may be written as:

In the prior art frequency demodulator, the delay .tau., and consequently the pulse duration .theta., are fixed; the phase difference .phi. and consequently the output voltage U.sub.S of the demodulator are proportional to the frequency F.

In contrast therewith, in the frequency demodulator according to the invention, the delay .tau., and consequently the pulse duration .theta., are variable in such a way that the phase difference .phi. and consequently the output voltage U.sub.S vary in a sense which is inverse to the frequency F.

The variation .DELTA.U.sub.S of the demodulator output signal for a frequency shift from F.sub.A to F.sub.B of the modulated signal may be written as:

.theta..sub.A and .theta..sub.B being the pulse durations of the signal V.sub.j for the frequencies F.sub.A and F.sub.B.

The average value V.sub.m of the output signal U.sub.S for the frequencies F.sub.A and F.sub.B may be written:

These two formulae (5) and (6) clearly show that for two data frequencies F.sub.A and F.sub.B, the variation .DELTA.U.sub.S and the average value V.sub.m of the output signal U.sub.s may be controlled by acting on the pulse durations .theta..sub.A and .theta..sub.B, that is to say, on the values of the delay .tau. produced by the delay circuit 3 for the frequencies F.sub.A and F.sub.B.

In order to put the invention into effect, it is possible to produce the required variable delay .tau. by means of a shift register which is controlled by, for example, shift pulses having a variable frequency as a function of the frequency F. It is simpler to produce said variable delay .tau. by analog means, of the type as utilized in two embodiments of the invention which will now be described.

A first embodiment of the demodulator in accordance with the invention is shown in FIG. 3. A certain number of elements of the FIGS. 1 and 3 are identical and are given the same reference numerals. All the indicated active circuits are fed from one sole voltage source, not shown, which produces the voltage U. The voltage U/2, which is applied, as will be described hereinafter, to a high-impedance input of the comparison circuits, may advantageously be obtained by means of a voltage divider formed by resistors which are connected to the sole voltage source.

The frequency-modulated signal e(t) is applied to the inverting input of an operational amplifier 10 whose non-inverting input receives a voltage U/2. Said operational amplifier forms an amplitude-limiting circuit producing a square-wave signal V.sub.d having amplitude U and period T, which is shown in diagram 4a of FIG. 4. Said signal V.sub.d is applied to an input of an "exclusive-OR" circuit 11 whose other input receives the voltage U. Said circuit 11 thereby performs the function of an inverting circuit and the signal V.sub.e at its output is shown in diagram 4b. The signal V.sub.e constitutes the non-delayed signal V.sub.a which is applied to an input of the "exclusive-OR" circuit 2. This "exclusive-OR" circuit 2 is followed by low-pass filter 4 and comparator circuit 5, which have the same function as in FIG. 1.

In order to apply the signal V.sub.r delayed by a variable duration .tau. to the other input of the "exclusive-OR" circuit 2, the following elements are used. An "exclusive-OR" circuit 12 has an input which is connected to the output of the operational amplifier 10, its other input being connected to the output of the "exclusive-OR" circuit 2. The output of the circuit 12 supplies the square-wave signal V.sub.f which has the form shown in the diagram 4c and explained hereinafter. The output of the circuit 12 is connected, via the capacitor 13 having a capacitance C, to a terminal 14 which interconnects series resistors 15 and 16. The signal on said terminal 14 is designated V.sub.g and has the shape shown in diagram 4d and described hereinafter. The series arrangement of the two resistors 15 and 16 is connected between the output of the "exclusive-OR" circuit 11 and the inverting input of an operational amplifier 17. This operational amplifier performs the function of a comparator which compares the variable voltage applied to its inverting input with a voltage U/2 applied to its non-inverting input. It produces, as described hereinafter, the delayed signal V.sub.r which is applied to the other input of the "exclusive-OR" circuit 2. The delayed signal V.sub.r is shown in diagram 4e. It is easy to derive from the two signals V.sub.a and V.sub.r applied to the inputs of the circuit 2 and shown in diagrams 4b and 4e the output signal V.sub.j of this circuit 2, whose average value U.sub.S is obtained by means of filter 4.

With reference to the various diagrams of FIG. 4, it will now be explained how the circuit assembly for obtaining the pulse-shaped signal V.sub.j operates.

The starting point is the instant t.sub.1 at which the non-delayed signal V.sub.a has the value U and the increasing signal V.sub.g reaches the voltage U/2 which causes comparator 17 to change state. At this instant t.sub.1, the signal V.sub.r drops from U to 0 and the signal V.sub.j increases from 0 to U. As the signal V.sub.d is now equal to 0, the result is that the signal V.sub.f increases from 0 to U. As V.sub.f is applied to one terminal of capacitor 13, the signal V.sub.g at the other terminal of this capacitor increases suddenly from U/2 to 3U/2 at the instant t.sub.1. After the instant t.sub.1 the signal V.sub.g decreases exponentially with a time constant RC determined by the capacitor 13 having a capacitance C and the resistor 15 having a value R. The law which governs the decrease after the instant t.sub.1 is: ##EQU2## It is readily verified that for: ##EQU3## Diagram 4d shows the curve V.sub.g1 which is composed of a solid line portion extended by a dashed line.

At the instant t.sub.2 at which the signal V.sub.a drops to 0, the signal V.sub.j also drops to zero and, simultaneously, the signal V.sub.d increases to the voltage U, the signal V.sub.f remains at the voltage U. But the fact that the signal V.sub.e =V.sub.a has dropped to 0, causes the voltage V.sub.g to decrease exponentially after instant t.sub.2 in accordance with a law other than the law V.sub.g1 indicated by formula (7): after instant t.sub.2 the law governing the decrease of the signal V.sub.g is: ##EQU4## It is readily verified that for: ##EQU5## U.sub.o is a certain voltage comprised 0 and U/2. Diagram 4d shows the curve V.sub.g2 which is composed of a solid line portion extended by a dashed line.

At the instant t.sub.3 at which the decreasing signal V.sub.g reaches the voltage U/2 which causes comparator 17 to change state, the signal V.sub.r increases again from 0 to U, which also applies to the signal V.sub.j. The result is that the signal V.sub.f drops from U to zero and that the voltage V.sub.g decreases suddenly from +U/2 to -U/2. After this instant t.sub.3 the voltage V.sub.g increases exponentially in accordance with the law: ##EQU6## and it is verified that for: ##EQU7## The curve V.sub.g3 is shown in diagram 4d; but for the direction in which it varies it has the same form as the curve V.sub.g1.

At the instant t.sub.4 at which the signal V.sub.a increases from 0 to U, the signal V.sub.j drops from U to 0. As the signal V.sub.d also drops from U to 0, the signal V.sub.f remains at zero. As the signal V.sub.e =V.sub.a increases from 0 to U, the signal V.sub.g increases after instant t.sub.4 in accordance with a law other than the law governing V.sub.g3 and which is: ##EQU8## It is verified that for: ##EQU9## The curve V.sub.g4 is shown in diagram 4d; but for the direction in which it varies it has the same shape as the curve V.sub.g2.

At the instant t.sub.5 at which the signal V.sub.g reaches the voltage U/2, the action occurring at the instant t.sub.1 is repeated.

A detailed inspection of the curve of the signal V.sub.g shows that this signal is a periodical signal having the period T and that it is symmetrical with respect to the voltage U/2. This signal V.sub.g makes it possible to generate, at an input of the "exclusive-OR" circuit 2, the delayed signal V.sub.r shown in diagram 4e, which has a time delay .tau.>T/2 with respect to the signal V.sub.a applied to the other input of this circuit 2. This results in pulses having a duration .theta. in the pulse-shaped signal V.sub.j shown in diagram 4f. The above-described circuit produces a delay .tau. which varies versus the frequency 1/T, that is to say, seeing that .theta.=T-.tau., a pulse duration .theta. which varies versus the frequency 1/T.

The law according to which the pulse duration varies versus the frequency F=1/T, is the result of simple calculations, the principle of which is described hereinafter. The diagrams 4d and 4f show that during the period of time .theta., the curve V.sub.g1, for example, changes from 3U/2 to U+U.sub.o. It is easy to deduct from the formula (7) that:

On the other hand, during the interval T/2-.theta. between the pulses of the signal V.sub.j, the curve V.sub.g2 changes, for example, from U+U.sub.o to U/2. It is possible to deduce therefrom that:

and consequently that: ##EQU10##

By combining the formulae (11) and (12) it is finally obtained that: ##EQU11##

It is easy to see that when the frequency F increases the pulse width .theta. decreases and vice versa.

The phase difference .phi. between the signals V.sub.a and V.sub.r applied to the "exclusive-OR" circuit 2 has for its expression .phi.=2.pi..theta.F and may therefore be written, using the formula (13): ##EQU12##

It is possible to verify that this expression, in accordance with formula (14), satisfies a characteristic of the invention, namely that .phi. decreases when the frequency increases and vice versa. In addition, it is possible to verify that the derivative of .phi. increases when the frequency increases.

In accordance with formula (14), the output voltage U.sub.S of the demodulator may be written: ##EQU13## This output voltage varies versus the frequency F in the same way as the phase difference .phi.. It decreases when the frequency F increases and the slope of the curve of U.sub.S as a function of F increases when the frequency increases. The formula (15) shows clearly that it is possible to adjust the law which governs the variation of the output voltage U.sub.S versus the frequency F by adjusting the time constant RC, that is to say, in practice, the ohmic value R of the resistor 15.

For the case of a demodulator for data transmitted by two frequencies F.sub.A and F.sub.B, it may be of interest that for the highest frequency, for example for F.sub.A, the output signal U.sub.S be zero. This condition is realized when for said frequency F.sub.A, the width .theta..sub.A of the pulses of the signal V.sub.j is zero. It can therefore be easily deduced from the formulae (11) and (12) that then: ##EQU14##

This formula (16) also shows the value to be given to the time constant RC in order to obtain a zero voltage U.sub.SA for the highest frequency F.sub.A. The variation .DELTA.U.sub.S of the output signal of the demodulator has therefore, in accordance with the formula (5), the value .DELTA.U.sub.S =2U .theta..sub.B F.sub.B, where .theta..sub.B is given by formula (13) by replacing RC therein by the value given by formula (16). For this case, the variation .DELTA.U.sub.S has its maximum possible value and the average value V.sub.m between the two values of the output signal U.sub.S for the frequencies F.sub.A and F.sub.B is of necessity equal to .DELTA.U.sub.S /2, as for one of these frequencies, F.sub.A, the output signal is zero.

The circuit diagram of FIG. 5 shows a second embodiment of the demodulator in accordance with the invention. This FIG. 5 comprises a number of elements which are the same as shown in FIGS. 1 and 3 and are given the same reference numerals.

The square-wave signal V.sub.d, having amplitude U and having the frequency F=1/T of the frequency-modulated signal e(t), appears at the output of the amplitude-limiting circuit formed by the operational amplifier 10. This signal V.sub.d, which is represented in diagram 6a of FIG. 6, constitutes the non-delayed signal V.sub.a which is applied to an input of the "exclusive-OR" circuit 2.

The signal V.sub.r applied to the other input of the circuit 2 is obtained by delaying the signal V.sub.d by a time .tau. which varies versus the frequency F, by means of the following circuits. The signals V.sub.d is applied to an integrating circuit formed by a resistor 20 having the value R.sub.3 and being arranged in series with a capacitor 21 having the capacitance C', which is connected to the ground terminal connected to the negative terminal of the voltage supply source. At the junction 22 of resistor 20 and capacitor 21, a signal V.sub.h is obtained, whose shape is shown in diagram 6b of FIG. 6 and will be explained hereinafter. The terminal 22 is connected to the non-inverting input of an operational amplifier 23 which functions as a comparator comparing the signal V.sub.h applied to its non-inverting input with the signal V.sub.n applied to its inverting input. The output signal of comparator circuit 23 is inverted by means of an inverter circuit 24. The output signal V.sub.i of this inverter circuit 24 is applied to the non-inverting input of operational amplifier 23 via a resistor 25 having value R.sub.4 and also to the inverting input of amplifier 23 via a resistor 26 having the value R.sub.2. Said inverting input is also connected to the junction of two series-arranged resistors 27 and 28, which have the same value 2R.sub.1 and are connected between the positive terminal of the voltage supply source having the value U and ground. The signal V.sub.n at the inverting input of operational amplifier 23 may assume two values, depending on whether the signal V.sub.i has the value 0 or U. It is easy to demonstrate that these two values are ##EQU15##

Operational amplifier 23 compares the signal V.sub.h to said two possible values of the signal V.sub.n, the result being the signal V.sub.i at the output of inverter circuit 24. Said signal V.sub.i, represented in diagram 6c, forms the delayed signal V.sub.r applied to an input of "exclusive-OR" circuit 2. It is easy to deduce from the signal V.sub.a and V.sub.r represented by the diagrams 6a and 6c, the signal V.sub.j which appears at the output of "exclusive-OR" circuit 2 and which, as in the foregoing, is formed by pulses having an amplitude U and a duration .theta. as shown by diagram 6d.

It will now be described how the signal V.sub.h present at the non-inverting input of operational amplifier 23 and represented by diagram 6b is formed.

The starting point is the instant t.sub.1 at which the signal V.sub.d increases from 0 to U, the signal V.sub.i then having the value U which, in accordance with the relations (17), means that V.sub.n =U-u.sub.2. At said instant t.sub.1, the signal V.sub.h has a certain value U-u.sub.1 <U-u.sub.2, u.sub.1 being a value which will be defined hereinafter. After the instant t.sub.1, since the voltages V.sub.i and V.sub.d have the same value U, one may say that capacitor 21 is charged by means of the voltage U applied to it via the parallel-arranged resistors 20 and 25. If the equivalent resistance of said two parallel arranged resistors 20 and 25 is denoted as R', in which R'=(R.sub.3 R.sub.4 /R.sub.3 +R.sub.4), it is easy to demonstrate that the law, in accordance with which the voltage V.sub.h varies after the instant t.sub.1, is: ##EQU16## It is possible to verify that for: ##EQU17## Diagram 6b shows the curve V.sub.h1 which is composed of a solid line portion extended by means of a dashed line.

At the instant t.sub.2 at which the increasing voltage V.sub.h reaches the voltage V.sub.n =U-u.sub.2 present at the inverting input of operational amplifier 23, the voltage V.sub.i =V.sub.r drops to zero as shown by diagram 6c. As this results from the relations (17), the voltage V.sub.n drops simultaneously to U.sub.2. After the instant t.sub.2, capacitor 21 discharges via the center tap of a voltage divider formed by the series arrangement of the resistors 25 and 20, one end of said voltage divider being connected to the voltage U (resistor 20), the other end being connected to ground (resistor 25). It can be shown that the law in accordance with which the voltage V.sub.h varies after the instant t.sub.2 is: ##EQU18## It can be verified that then for: ##EQU19## Diagram 6b shows the curve V.sub.h2 which is formed by a solid line portion extended by a dashed line.

At the instant t.sub.3 at which the signal V.sub.d drops from U to 0, the signal V.sub.h has a certain value u.sub.1. After the instant t.sub.3, since the signals V.sub.i and V.sub.d have the same value 0, capacitor 21 is discharged by means of the voltage 0 which is applied to it via the two resistors 20 and 25 arranged in parallel. It can be shown that the law in accordance with which the voltage V.sub.h varies after the instant t.sub.3 is: ##EQU20## It can be verified that then for: ##EQU21## Diagram 6b shows the curve V.sub.h3 which is formed by a solid line portion extended by a dashed line.

At the instant t.sub.4 at which the decreasing signal V.sub.h reaches the voltage V.sub.n =u.sub.2 present at the inverting input of operational amplifier 23, the voltage V.sub.i =V.sub.r increases from 0 to U, as shown by diagram 6c. As this results from the relations (17), the voltage V.sub.n simultaneously increases to U-u.sub.2. After the instant t.sub.4, capacitor 21 is charged by the center tap of a voltage divider formed by the series arrangement of the resistors 25 and 20, one end of said voltage divider being connected to the voltage U (resistor 25) the other end being connected to ground (resistor 20). It can be shown that the law in accordance with which the voltage V.sub.h varies after the instant t.sub.4 is: ##EQU22## It can be verified that then for: ##EQU23## Diagram 6b shows the curve V.sub.h4 which is formed by a solid line portion extended by a dashed line.

At the instant t.sub.5 at which the signal V.sub.d increases from 0 to U, the signal V.sub.h reaches a voltage U-u.sub.1, u.sub.1 being the voltage of the signal V.sub.h at the instant t.sub.3. After the instant t.sub.5 there follows the same procedure as after the instant t.sub.1.

An examination of the curve of the signal V.sub.h shows that this signal is periodical with the period T and symmetrical with respect to the voltage U/2. By means of this signal V.sub.h it is possible to obtain, at an input of "exclusive-OR" circuit 2 the signal V.sub.r shown in diagram 6c, which signal is delayed by .tau.>T/2, with respect to the signal V.sub.a applied to the other input of said circuit 2. This results in pulses having an amplitude U and a duration .theta. in the pulse-shaped signal V.sub.j produced by "exclusive-OR" circuit 2 and shown in diagram 6d. This delay .tau. varies versus the frequency F=1/T, the result being that the duration of the pulses .theta.=T-.tau. of the signal V.sub.j also varies versus the frequency F.

To determine the law in accordance with which .theta. varies versus the frequency F, it can be noted that during the interval T/2-.theta. between the pulses of the signal V.sub.j, the curve V.sub.h1, for example, varies from U-u.sub.1 to U-u.sub.2 and that during the interval .theta., the curve V.sub.h2, for example, varies from U-u.sub.2 to u.sub.1. Applying the formulae (18) and (19), it is possible to show that .theta. has for its expression: ##EQU24##

With this expression of .theta., it is possible to verify that the phase difference .phi.=2.pi..theta.F, between the two signals V.sub.a and V.sub.f applied to the inputs of "exclusive-OR" circuit 2, decreases when the frequency increases and vice versa.

The output voltage U.sub.S of the demodulator, which has for its expression U.sub.S =2UF.theta.=(u/.pi.).phi., varies versus the frequency F in the same way as the phase difference .phi.. It is clear that the law in accordance with which .theta. varies and consequently the law in accordance with which the output voltage U.sub.S varies versus frequency, can be adjusted at one's option, by acting on the different parameters appearing in the formula (22), such as C', R', K and u.sub.2 ; the parameters R' and K depend on the values R.sub.3 and R.sub.4 of the resistors 20 and 25; the voltage u.sub.2 depends in particular on the value R.sub.2 of the resistor 26 and the value 2R.sub.1 of the resistors 27 and 28. It is therefore possible to obtain the values as desired for the variation .DELTA.U.sub.S of the demodulator output signal for two frequencies F.sub.A and F.sub.B and for the average value V.sub.m of said signal.

A special adjustment which may be advantageous for certain applications such as a discrimination between two frequencies F.sub.A and F.sub.B is effected by assigning such values to the different elements of the demodulator that for the highest frequency F.sub.A the output voltage U.sub.S is substantially zero and that for the lowest frequency F.sub.B the output voltage is substantially equal to the supply voltage U. This means that the pulse duration .theta..sub.A for the frequency F.sub.A must be zero and that the pulse duration .theta..sub.B for the frequency F.sub.B must be equal to 1/2F.sub.B. The most advantageous conditions for discrimination between the two frequencies F.sub.A and F.sub.B are then obtained, as the variation .DELTA.U.sub.S of the output signal for these two frequencies F.sub.A and F.sub.B is substantially equal to the supply voltage U, while the average value M.sub.m between the two values of the output signal is, in accordance with formula (6), equal to U/2.

For this special adjustment there now follow the ratios required between the values of the different elements of the demodulator. By applying the formula (22) the respective conditions .theta..sub.A =0 and .theta..sub.B =1/2F.sub.B may be written: ##EQU25## The relation (24) may then also be written as: ##EQU26## For u.sub.2 =KU, the relation (25) is virtually satisfied if F.sub.B is sufficiently small with regard to 1/2R'C'. It is then virtually obtained that .theta..sub.B =1/2F.sub.B and U.sub.S =0 if u.sub.2 =KU or, taking account of the values for u.sub.2 and K given in the foregoing, if: ##EQU27##

When it is assumed that u.sub.2 =KU, that is to say if the relation (26) is satisfied, it can be shown that the formula (23), which is conditioned to obtain that .theta.=0 and U.sub.S =U, may be written: ##EQU28##

Finally, the quantity 1/2R'C' being chosen large with respect to the lowest frequency F.sub.B, the two formulae (26) and (27) provide the means to determine the values of the different elements of the demodulator to obtain that virtually .DELTA.U.sub.S =U and V.sub.m =U/2.

In the analog embodiments of the frequency demodulator as they have been described in the foregoing, it is advantageous that all the circuits employed are on the one hand supplied from a sole voltage source and on the other hand realized in CMOS technology, particularly because of the fact that the output resistance of the circuits produced in said CMOS technology is low. These two measures are very advantageous for the stability of the characteristics of the demodulator as a function of the ambient temperature fluctuations and the supply source fluctuations.