Semiconductor Memory Device

1. Field of the Invention

The present invention relates to a semiconductor memory device, more particularly to a static type semiconductor RAM (Random Access Memory) device having a large memory capacity and a high operating speed.

2. Description of the Prior Art

In general, the current consumption of memory cells and bit lines of a static type RAM device becomes large according to an increase in the memory capacity, i.e., according to an increase in the number of the memory cells. Therefore, especially in a RAM device having a large memory capacity, the gm of each of the load transistors connected to the bit lines is caused to be small in order to decrease the current consumption of the bit lines.

As illustrated in FIG. 1, a conventional static type RAM device comprises a plurality of memory cells MC.sub.0,0, MC.sub.1,0, . . . ; word lines W.sub.0, W.sub.1, . . . ; pairs of bit lines B.sub.0 and B.sub.0, . . . ; word decoders WD.sub.0, WD.sub.1, . . . ; and load MIS transistors Q.sub.1, Q.sub.2, . . . for each of the bit lines B.sub.0 and B.sub.0. Each of the memory cells MC.sub.0,0, MC.sub.1,0, . . . has the same circuit structure and comprises load resistors R.sub.1 and R.sub.2 and MIS transistors Q.sub.3 through Q.sub.6. The drain electrodes and the gate electrodes of the transistors Q.sub.5 and Q.sub.6 are cross-coupled so as to form a flip-flop type memory cell circuit.

In the memory device of FIG. 1, when, for example, the word line W.sub.0 is selected by address signals ADD and the output potential of the word decoder WD.sub.0, i.e., the word line W.sub.0 becomes the potential level for a selected condition, for example high, the transistors Q.sub.3 and Q.sub.4 are both turned on. In this condition, if the transistors Q.sub.6 of the memory cell MC.sub.0,0 is in an on state, a current flows from a voltage source V.sub.DD through the transistors Q.sub.2, Q.sub.4 and Q.sub.6 to another voltage source V.sub.SS, so that the potential of the bit line B.sub.0 becomes low. Since the transistor Q.sub.5 of the same memory cell MC.sub.0,0 is in a turned off condition, the potential level of the bit line B.sub.0 is high. The potential difference between the bit lines B.sub.0 and B.sub.0 is detected by a sense amplifier (not shown in the drawing) and information from the selected memory cell MC.sub.0,0 is provided as an output.

In the above-mentioned RAM device, if the memory cell MC.sub.1,0 is selected next after the memory cell MC.sub.0,0 and if the memory cell MC.sub.1,0 stores a different data from that of the memory cell MC.sub.0,0, i.e., a transistor Q'.sub.5 is in a turned on condition and a transistor Q'.sub.6 is in a turned off condition, it is necessary to electrically charge the bit line B.sub.0 to a high potential level quickly. However, since, as aforementioned, the gm of the load transistors Q.sub.1 and Q.sub.2 is caused to be small in order to decrease the current consumption of the bit lines of a memory device having a large memory capacity, it is impossible to quickly charge the bit line B.sub.0 from low to high. Therefore, the access time of such a conventional memory device cannot be short. If the read-out of information from the memory cell MC.sub.1,0 is effected just after the write-in of information to the memory cell MC.sub.0,0 and if the memory cell MC.sub.1,0 stores data different from that written into the memory cell MC.sub.0,0, it is necessary to electrically charge the bit line, for example, B.sub.0, from a very low potential (e.g. 0 V) to a high potential (e.g. 3 V), so that the access time of the RAM device becomes still longer than that in the above-mentioned case.

It is, therefore, the principal object of the present invention to decrease the access time of a static type RAM device having a large memory capacity without increasing the current consumption in a steady state operation.

According to the present invention, there is provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells disposed at the cross points between the word lines and the bit lines and load circuits each connected between one of the bit lines and a voltage source, a memory cell disposed at the cross point of a word line and a bit line being selected by selecting said word line and the bit line, characterized in that the memory device comprises, besides the load circuits, a charging circuit which electrically charges all the bit lines during the switching period of word address signals.

FIG. 1 is a partial circuit diagram illustrating a known conventional static type RAM device;

FIG. 2 is a partial circuit diagram illustrating a static type RAM device according to the present invention; and

FIG. 3A through FIG. 3E are waveform diagrams illustrating the operation of the RAM device of FIG. 2.

FIG. 2 illustrates a static type RAM device as an embodiment of the present invention. In FIG. 2, the same parts as appear in FIG. 1 are designated by the same reference symbols. The RAM device of FIG. 2 includes a plurality of memory cells MC.sub.0,0, . . . , MC.sub.0,M-1, MC.sub.1,0, . . . , MC.sub.1,M-1, . . . disposed at cross points between a plurality of word lines W.sub.0, W.sub.1, . . . and a plurality of pairs of bit lines B.sub.0 and B.sub.0 through B.sub.M-1 and B.sub.M-1 ; a plurality of word decoders WD.sub.0, WD.sub.1, . . . connected to the word lines W.sub.0, W.sub.1, . . . respectively; and pairs of gate transistors Q.sub.200 and Q.sub.210 through Q.sub.20(M-1) and Q.sub.21(M-1) connected to the pairs of bit lines B.sub.0 and B.sub.0 through B.sub.M-1 and B.sub.M-1 respectively, and controlled by column decode signals Y.sub.0 through Y.sub.M-1 respectively. The RAM device of FIG. 2 further comprises load transistors Q.sub.10 and Q.sub.20 through Q.sub.1(M-1) and Q.sub.2(M-1) connected between the pairs of the bit lines B.sub.0 and B.sub.0 through B.sub.M-1 and B.sub.M-1 and a power source V.sub.DD respectively; a write-in circuit WRC constituted by an amplifier WA and three NAND gates NG1 through NG3, whose output terminals are connected to a pair of data bit lines DB and DB; a sense amplifier SA connected to the pair of data bit lines DB and DB; and an output buffer amplifier BA connected to the sense amplifier SA.

The RAM device of FIG. 2 still further comprises, according to the present invention, a high speed charging circuit constituted by MIS charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) and by MIS transistors Q.sub.13, Q.sub.14, Q.sub.15, Q.sub.16, Q.sub.17, . . . . The MIS charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are connected parallel to the load transistors Q.sub.10 and Q.sub.20 through Q.sub.1(M-1) and Q.sub.2(M-1), respectively. The MIS transistors Q.sub.13, Q.sub.14, Q.sub.15, Q.sub.16, Q.sub.17, . . . constitute a NOR gate to generate a control signal S.sub.C supplied to the gate electrodes of the MIS charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1). The MIS transistor Q.sub.13 is a load transistor of the NOR gate. The gate electrodes of the MIS transistors Q.sub.14 and Q.sub.15 are connected to the word line W.sub.0 at both ends thereof and the gate electrodes of the MIS transistors Q.sub.16 and Q.sub.17 are connected to the word line W.sub.1 at both ends thereof. The other MIS transistors connected to the other word lines at both ends thereof are not shown in the drawing.

The charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are controlled by the output signal, i.e., the control signal S.sub.C. That is, when all the transistors Q.sub.14, Q.sub.15, Q.sub.16, Q.sub.17, . . . are in a turned off condition, the output signal S.sub.C of the NOR gate becomes high so that all the charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are turned on. On the contrary, when at least one of the transistors Q.sub.14, Q.sub.15, Q.sub.16, Q.sub.17, . . . is in a turned on condition, the output signal S.sub.C of the NOR gate becomes low so that all the charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are turned off. The transistors Q.sub.14 and Q.sub.15 (or Q.sub.16 and Q.sub.17 or other transistors not shown in the drawing) detect the potential levels of one end portion of the word line W.sub. 0 (or W.sub.1, . . . ) and of another end portion of the same word line W'.sub.0 (W'.sub.1, . . . ). Therefore, the charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are not turned on until the potential of all portions of the word lines W.sub.0, W.sub.1, . . . becomes low level, i.e., the level of the non-selected conditions even when the potential of each portion of the word line does not change at the same time due to the propagation delay of the word line along the longitudinal direction thereof. On the contrary, the charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are turned on immediately after the output potential of at least one of the word decoders WD.sub.0, WD.sub.1, . . . becomes high level, i.e., the potential level in the selected condition of the word line.

With reference to FIG. 3A through FIG. 3E, operation of the above-mentioned RAM device will now be explained. Assume that, as illustrated in FIG. 3A, the word address signal ADD has changed from ADD(W.sub.0) which selects the word line W.sub.0 to ADD(W.sub.1) which selects the word line W.sub.1 at a time t.sub.0 and pairs of bit lines B.sub.0 and B.sub.0 are continuously selected before and after the time t.sub.0. That is, the memory cell MC.sub.0,0 is selected before the time t.sub.0 and the memory cell MC.sub.1,0 is selected after the time t.sub.0. Assume also that the read-out operations from both the memory cells MC.sub.0,0 and MC.sub.1,0 are sequentially effected and the memory cells MC.sub.0,0 and MC.sub.1,0 store different information from each other. In this condition, if the transistor Q.sub.5 of the memory cell MC.sub.0,0 is in a turned off condition and the transistor Q.sub.6 of the same memory cell is in a turned on condition, the potentials of the bit lines B.sub.0 and B.sub.0 are high (e.g. 3 V) and low (e.g. 2 V) respectively (FIG. 3D), the potentials of the word lines W.sub.0 and W.sub.1 are high and low respectively and the potentials of the end portions W'.sub.0 and W'.sub.1 of the word lines W.sub.0 and W.sub.1 are also high and low, respectively (FIG. 3B), at the time t.sub.0. After the word address signal ADD has changed from ADD(W.sub.0) to ADD(W.sub.1), the output signal of the word decoder WD.sub.0, i.e., the potential of the word line W.sub.0, changes from high to low and the output signal of the word decoder WD.sub.1, i.e., the potential of the word line W.sub.0, changes from low to high. In this case, the potentials of the end portions W'.sub.0 and W'.sub.1 of the word lines W.sub.0 and W.sub.1 change a short time after the potential of the beginning portions of the word lines W.sub.0 and W.sub.1 have changed. In FIG. 3B, the curves of the potentials of the beginning portion of the word lines W.sub.0 and W.sub.1 are designated by the symbols W.sub.0 and W.sub.1 respectively. As a result, all the input signals of the NOR gate constituted by the translstors Q.sub.13 through Q.sub.17 and others become low at a time t.sub.1 when the potential of the end portion W'.sub.0 of the word line W.sub.0 becomes low, so that the output signal S.sub.C of the NOR gate becomes high as illustrated in FIG. 3C. At a time t.sub.2, the output potential W.sub.1 of the word decoder WD.sub.1 becomes high and the output signal S.sub.C of the NOR gate becomes low. Therefore, during the time period between t.sub.1 and t.sub.2, no word line is selected and the output signal S.sub.C becomes high. In the present invention, the charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are turned on during this non-selected time period and the bit lines B.sub.0 and B.sub.0 are quickly charged through the charging transistors Q.sub.110 and Q.sub.120 and through the load transistors Q.sub.10 and Q.sub.20. Therefore, the potential curve of the bit line B.sub.0 rises quickly and crosses the potential curve of the bit line B.sub.0 at a time t.sub.3 as illustrated in FIG. 3D. A curve B'.sub.0 shown by the dotted line of FIG. 3D illustrates the charging characteristics of the conventional memory device of FIG. 1, in which the bit lines B.sub.0 and B.sub.0 are charged only by the load transistors Q.sub.1 and Q.sub.2, respectively. The dotted line curve B'.sub.0 crosses the curve B.sub.0 at a time t.sub.4 which is later than the time t.sub.3 by .DELTA.t. Since the transfer gate transistors Q.sub.200 and Q.sub.210 of FIG. 2 connected between the bit lines B.sub.0 and B.sub.0 and the data bit lines DB and DB are in a turned on condition, the abovementioned potential changes are transferred to the sense amplifier SA and the buffer amplifier BA. The sense amplifier detects the potential change of the bit lines B.sub.0 and B.sub.0 and changes the potential of the read-out signal D.sub.out after the cross point of the potential curves B.sub.0 and B.sub.0 (or B'.sub.0). Therefore, according to the present invention, the access time of the RAM device can be increased by .DELTA.t. Since the chargng transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are only turned on temporarily, the current consumption of the RAM device does not increase much.

In the above-mentioned memory device, the write-in of information to a memory cell, for example, MC.sub.0,0 is effected by applying a write-in data signal D.sub.in and an inverted write enable signal WE of low potential level to the write-in circuit WRC and by turning on the transfer gate transistors Q.sub.200 and Q.sub.210 by the column decode signal Y.sub.0 and the transistors Q.sub.3 and Q.sub.4 by the output signal of the word decoder WD.sub.0. Assume that the potentials of the data bit lines DB and DB are caused to be high (e.g. 3 V) and low (e.g. 0 V) respectively according to the write-in data signal D.sub.in supplied to the write-in circuit WRC. These high and low potentials are transferred to the memory cell MC.sub.0,0 through the transfer gate transistors Q.sub.200 and Q.sub.210 and through the transistors Q.sub.3 and Q.sub.4 and the write-in of information is effected.

If the read-out operation from the memory cell MC.sub.1,0 is effected after the above-mentioned write-in to the memory cell MC.sub.0,0 is effected and, if the data stored in the memory cell MC.sub.1,0 is different from the data written into the memory cell MC.sub.0,0, the bit line B.sub.0 must be charged from the low potential (0 V) of the write-in mode to the high potential (3 V) of the read-out mode quickly. In the RAM device according to the present invention, the charging transistors Q.sub.110 and Q.sub.120 through Q.sub.11(M-1) and Q.sub.12(M-1) are also turned on temporarily in a similar manner to the aforementioned case, and, therefore, the potential of the bit line B.sub.0 rises quicker than that of the conventional RAM device as illustrated in FIG. 3E. Therefore, in even the worst case, the access time of the RAM device of the present invention can be much shorter than that of the conventional RAM device.

As mentioned above, since the RAM device according to a present invention comprises the high speed charging circuit which charges all the bit lines during a short time when all the word lines are in a non-selected condition, the access time of the RAM device having a large memory capacity can be short without increasing the power consumption much, even when the size, and therefore the gm, of each of the load transistors of the bit lines is small.