Pattern Recognition System Operating by the Multiple Similarity Method

This invention relates to pattern recognition systems operating by the multiple similarity method for character readers.

With recent considerable improvement of the character reader techniques, the character readers have been used in various fields. Generally, the character readers are constructed such as to make use of the pattern similarity method for the recognition of characters. For example, with a character optical reader, numeral figures or alphabet letters in a slip, for instance, are optically read out, and the data thus obtained are converted into character patterns, which are checked for the similarity degree with each of a plurality of reference patterns stored in a dictionary memory. Each character pattern thus checked is recognized as a reference pattern, the similarity degree of which is the highest. In the prior art character reader, however, the calculation of the similarity degree of each of the reference patterns with respect to the sample character patterns is effected in a single similarity degree computation circuit for one sample character after another. Therefore, the processing speed is considerably slow, and a considerable processing time is required where a large number of characters are to be identified.

An object of the invention, accordingly, is to provide a pattern recognition system, which can effect simultaneous computation of the similarity degree with respect to a number of characters and thus permit improvement of the character recognition processing speed.

According to the invention, there is provided a pattern recognition system, which comprises a plurality of similarity degree calculation circuits, and in which sample character patterns are inputted to the respective similarity computation circuits for simultaneous calculation of the similarity degree of each of a plurality of reference patterns with respect to them.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing an embodiment of the pattern recognition system according to the invention; and

FIG. 2 is a view showing the memory format of a dictionary memory shown in FIG. 1.

Referring to FIG. 1, a sample pattern generating circuit 11 for generating input patterns, i.e., sample patterns, is connected to a data bus 12. This circuit 11 generates sample pattern data of 7 by 10 dots (one dot being formed by 4 bits). The data bus 12 is connected to an address counter 13 and a data register 14. The address counter 13 counts a number of bit rows that form a sample pattern, and the data register 14 stores the sample pattern in one bit row after another. The output port of the data register 14 is connected to the dictionary address counter 15. The output port of the address counter 13 and dictionary address counter 15 is connected to the input port of a selector 16. The output port of the selector 16 is connected to the input port of an address register 17. The output port of the address register 17 is connected through a counter 18 to a decoder 19 and is also connected to a dictionary 20 and a selector 21. A sample pattern address counter 22 and a similarity address counter 23 are connected to the selector 21. The selector 21 is connected to a plurality of similarity degree computation circuits 24.sub.1 to 24.sub.n. These similarity degree computation circuits 24.sub.1 to 24.sub.n each have an input port connected to the data register 14 and an output port connected to the output port of the dictionary 20 and to an input port of the data register 14. These circuits also each include a computation section and a memory. The computation section has a circuit construction as disclosed in, for instance, the U.S. Pat. No. 3,688,267.

The operation of the pattern recognition system of the above construction will now be described. When a sample pattern data corresponding to, for instance, the character "A" is generated from the sample pattern generating circuit 11, data of one bit row of the generated sample pattern data is stored in the data register 14, and a first address i.e. an initial address is set in the address counter 13. The initial address in the address counter 13 is transferred through the selector 16 to the address register 17 and stored therein. When the initial address of the address register 17 is provided to the counter 18, the counter 18 is caused to count up. The contents of the counter 18 are decoded by the decoder 19 to enable the computation circuit 24. At this time, the address of the memory 25.sub.1 of the computation circuit 24.sub.1 is specified by the initial address data transferred from the address register 17 through the selector 21 to the computation circuit 24.sub.1, and the data of the first bit row transferred from the data register 14 is stored in this address. Then, when the second bit row data of the sample pattern is transferred to the data register 14, the address counter 13 is caused to count up. The updated address in the address counter 13 is transferred through the selector 16 to the address register 17 and stored therein. This address data specifies the next address in the address memory 25.sub.1, and the second bit row data is stored in this address. In this way, every time one bit row data of the sample pattern is transferred to the data register 14, the address counter 13 is caused to count up, and the successive bit rows are progressively stored in the successive addresses of the memory 25.sub.1. When all the bit rows of the first sample pattern are stored in the memory 25.sub.1, the address counter 13 is reset. Then, when the sample pattern for the second character, for instance, the character "B" is generated from the sample pattern generating circuit 11 and the first bit row of the sample pattern is transferred to the data register 14, the initial address is again set in the address counter 13. When this initial address is transferred through the selector 16 and address register 17 to the counter 18, the counter 18 is caused to count up. The contents of the counter 18 are decoded by the decoder 19 to enable the computation circuit 24.sub.2. Thus, the second sample pattern is stored in the memory 25.sub.2 in the computation circuit 24.sub.2. When a plurality of sample patterns are stored in the respective memories 25.sub.1 to 25.sub.n of the computation circuits 24.sub.1 to 24.sub.n, the initial address of the memories 25.sub.1 to 25.sub.n is set in the sample pattern address counter 22. At this time, a timing signal is supplied from a timing control circuit 26 to the decoder 19, and in response to this signal the decoder 19 gives an enable signal to all computation circuits 24.sub.1 to 24.sub.n. In this state, a pre-processing for the multiple similarity method is carried out. The multiple similarity degree is expressed as: ##EQU1## where h.sub.i (i being 1 to 70) is the bit row data of the sample pattern, and .phi..sub.ij (i being 1 to 70, j being the number of reference patterns representing reference characters stored in the dictionary 20. In the pre-processing calculation, the term ##EQU2## and the term ##EQU3## are calculated. At this time, each bit row data of each sample pattern is read out from each of the memory addresses of the memories 25.sub.1 to 25.sub.n which are successively specified by the content of the sample address counter 22, and the aforementioned terms are calculated in the computation sections of the respective computation circuits. The result of calculation is stored in the memory address of each of the memories 25.sub.1 to 25.sub.n specified by the similarity address counter 23 which is counted up each calculation.

When the calculations of both the terms are ended and the results are stored in the specified memory addresses, the dictionary address counter 15 is set at an initial address. The initial address of the dictionary address counter 15 is transferred through the selector 16 to the address register 17 and stored therein. The memory address of the dictionary 20 is specified by the address stored in the address register 17. In the dictionary 20, data representing reference characters as shown in FIG. 2 are stored. As shown in FIG. 2, the dictionary 20 includes an entry table section and a reference pattern memory section, and each of addresses in the entry table section is specified depending upon the address stored in the address register 17. If the initial address is "0", an address 200 in the reference pattern section is read out from the entry table, and the address where the data of the reference character "A" is stored is specified by the address 200. In the addresses 200 through 299 are stored a plurality of reference patterns representing respective reference characters "A", for instance 3 to 10 reference patterns in the case of hand written letters or 16 to 17 reference patterns in the case of Chinese characters. These reference patterns are each constituted by 7 by 10 dots each constituted by 6 bits. Of these reference patterns, the first bit row data of the first reference pattern is read out from the dictionary 20 and transferred to the computation circuits 24.sub.1 to 24.sub.n. The successive bit row data of the first reference pattern are progressively read out from the dictionary 20, and all the bit row data are subjected by the computation circuits 24.sub.1 to 24.sub.n at one time to the calculation of the term ##EQU4## and then at one time to the calculation of the term ##EQU5## The results of the calculation are stored in the next address to that in which the first reference pattern is stored. Subsequently, the calculation of the aforementioned term is effected with respect to the following reference patterns, and the results are stored in the respective memories. When the calculation with respect to all the reference patterns representing the respective reference characters "A" is ended, the dictionary address counter 15 is caused to count up, and the reference pattern corresponding to the next reference character "B" is read out according to the content of the address counter 15 for making the calculation as described above. In the above way, calculations with respect to desired reference characters, for instance, reference characters "A" through "Z", are effected, and the results are stored in the memories 25.sub.1 to 25.sub.n. Thereafter, the calculation of the multiple similarity degree is made as the final calculation. This calculation is effected in a CPU 28 with the calculation results for the three terms mentioned above, transferred from the memories 25.sub.1 to 25.sub.n, through the data register 14 and a data bus 27 to the CPU 28. Thus, the reference pattern of the highest similarity degree is provided as the result of recognition.

As has been described in the foregoing, according to the invention a plurality of similarity degree computation circuits are provided, and the similarity degree calculation is simultaneously effected in these similarity degree computation circuits with respect to each of a plurality reference patterns. Thus, the processing speed in the similarity degree calculation can be considerably increased.