Digital Timer Fuze

1. Field of the Invention.

This invention pertains to digital timer fuzes (DTF) and systems associated therewith.

2. Description of the Prior Art.

Time fuzes are widely used in Navy weapons principally because they are less costly than proximity fuzes. This advantage, however, is offset by a compromise in weapon performance, since fuze function time is a tradeoff based on the statistical average of typical weapon deployments. Also, when launching air-to-surface weapons, the pilot is constrained to a specific weapon delivery flight envelope to maintain weapon effectiveness. As a result of such repeated trajectories, the launch aircraft is more vulnerable to hostile action.

Because it is settable, the proposed DTF system can be used in place of conventional fixed-timer fuzes to provide improved weapon performance with an enlarged launch envelope. This system would also permit the use of low-cost time fuzing in some applications that previously required higher-cost active or proximity fuzing. For example, the DTF could replace costly autonomous slant-range fuzes, which function at ranges from several hundred feet to over 1,000 feet. In such instances, a cost saving in expended fuze hardware of approximately 30 to 1 could be realized.

The advanced capabilities of high accuracy (approximately 0.1%) and almost instantaneous settability (a few milliseconds) offered by the DTF open many new military applications for a timer of this type. However, only the air-to-surface weapon application will be addressed here. By replacing fixed-delay timers, the DTF can greatly enlarge the launch envelope of such weapons. In addition to providing the pilot with greater flexibility in his weapon delivery tactics, weapon effectiveness can be maximized for each launch. This can be accomplished by accurately determining the optimum warhead function time for each weapon to be launched, and by setting each fuze accordingly the instant before launch. Such a procedure involves (1) acquisition of geometric and kinematic data to define the weapon trajectory after launch,(2) manipulation of this data to obtain the optimum fuze delay time for the weapon to be launched, and (3) setting the fuze delay time before launch.

In the technical approach to an optimum fuze design, the type of timer to be used is a prime consideration.

Electrical timers have four significant advantages over mechanical timers: (1) the electrical timer is capable of an almost infinite variation of delay time settings; (2) the delay time can be remotely set through an electrical circuit; (3) the time interval required to set the timer can be made quite brief, allowing the timer to be set at the instant of weapon release; and (4) the accuracy of an electrical timer can be improved over that of mechanical timers in the same cost range.

There are two basic types of electrical timers: analog and digital. An analog timer typically uses the time required for a capacitor to discharge energy through a resistor as the timing element. Associated threshold/fire and setting circuits complete such a timer. A digital timer typically employs a stable oscillator and a digital counter as the timing element. A firing circuit and setting circuit complete this timer.

At first appearance the analog approach may seem more straightforward; however, several features make digital implementation more attractive. First, because of the nature of integrated-circuit technology, the digital format is more readily integrated into a monolithic large-scale integrated circuit. This is important in that large-scale mass-production costs are drastically reduced. Second, the digital timer can be made at least 10 times more accurate than the best analog version. Third, digital timers can be made more immune to inaccuracies and significant unit-to-unit variations introduced in production. Fourth, the digital timer is more immune to environmental variations and adverse environments than the analog timer.

The invention comprises a digital timer fuze in which the input logic and a set/count gate causes an up/down counter to count first up then down. An umbilical line connects the fuze to a fuze setter, which is a subsystem of a fire-control computer located in an aircraft. A signal from the fuze setter charges a power supply capacitor and causes the counter to count up a given number of counts. When the missile is fired and the umbilical line is severed the counter counts down a number equal to the number of up counts and then gates an SCR firing circuit allowing the power supply capacitor to discharge into the detonator.

FIG. 1 shows a block diagram of the digital timer fuze system including the aircraft-rocket interface;

FIG. 2A is a block diagram of the digital timer fuze circuit;

FIG. 2B shows the electrical waveform which is applied through the umbilical line; and

FIG. 3 is a block diagram of the fuze setter which is a subsystem of the fire-control computer.

The digital timer fuze (DTF) system consists of expendable digital timer fuzes, a timer setter, a control computer, and the associated avionics for sufficiently accurate trajectory prediction. The set/count gate, 128 divider, OR gate, and 4,096-bit up/down counter are comprised of complementary-symmetry MOS digital integrated circuits.

The central element is the aircraft fire-control computer which includes a fuze setter which receives input signals from various sensors as required for rocket trajectory computations and, in addition, pilot commands. When the pilot arms the system and selects a firing mode, power is supplied to each fuze in the load. When the pickle switch is depressed, timing commands are injected into each fuze in proper sequence and the rocket motors are initiated via circuits and initiators incorporated in the launcher pods. As each rocket moves forward under motor thrust, the lead to its fuze is separated. Physical interruption of this circuit initiates the "run" phase of the digital timer fuze.

If the system is switched to "disarm" at any point in this sequence prior to separation of the fuze umbilical lead, each fuze will revert automatically to a "safe" condition within one minute.

When the DTF is energized by application of +15 volts through the umbilical line, the power supply capacitor is charged by the charging diode. The 128 divider and the up/down counter also are cleared at this time. The instant before launch, the umbilical voltage drops to zero for approximately 20 microseconds and then goes to -15 volts for the carefully controlled set pulse time period, after which the voltage returns to zero. While the umbilical voltage is negative, clock pulses are passed directly to the main counter, which is in the "up" counting mode. The length of this set pulse determines the number of clock pulses that are set into the counter. These clock pulses are stored in the main counter until counted out during the timed weapon flight interval or until otherwise removed. The delay time countdown of the stored clock pulses begins when physical separation of the umbilical line from the fuze is sensed by the input logic circuit. During weapon flight, the main counter is in the "down" mode and counts out each clock pulse that was counted in during the setting interval. On the last pulse the counter triggers the silicon-controlled rectifier (SCR), which fires the detonator, electric initiator, or similar load. The DTF functions independently once the weapon has been separated from the parent aircraft.

The pulses stored in the main counter after the set pulse can be removed in a number of ways. If the fire control system is turned off before the weapon is launched, or if a hang-fire occurs, the stored pulses will be lost when the power supply capacitor becomes discharged. The time required for the capacitor to discharge is about three times the maximum delay time. If the pilot aborts a weapon delivery maneuver, the fuze can be cleared of the previous time setting by the application of a new energizing pulse.

The DTF was designed to operate with a single coaxial umbilical cable. The sequence of positive and negative setting voltages provides one way of obtaining single wire operation. However, a variety of other techniques may be used, one of which may prove more compatible for use with large-scale integrated circuitry.

The three-stage clock circuit is used to obtain a stable clock frequency with minimum power consumption, a crucial factor to consider when the power is supplied by a capacitor. The supply voltage regulator maintains a constant supply voltage to the multivibrator as the power supply capacitor discharges. The output driver interfaces the clock to the digital integrated circuits.

It should be understood that the actual clock frequency, within the limits described in the appendix, is of little importance. The following derivations will verify this statement.

Letting

f.sub.c =the clock frequency in hertz

n.sub.c =the number of clock pulses stored in the main counter

N.sub.d =the set-time compression factor, which is determined by the divide ratio of the divider

t.sub.d =the delay time, or the duration of the timed interval, in seconds

t.sub.s =the duration of the set pulse in seconds (refer to FIG. 2B)

The number of clock pulses in the counter due to the set pulse is

The .+-.1 count error is inherent with gated digital signals. The number of clock pulses counted out is

Solving for t.sub.d gives ##EQU1## If f.sub.c is considerably larger than 1/t.sub.s, which is normally the case, the delay time is determined soley by the set time and the set-time compression factor.

The set/count gate steers the clock pulses for setting or counting. The 128 divider provides the required slow clock rate during countdown. For fast setting of the counter, the clock pulses bypass the 128 divider. Equation 3 shows that the ratio of count time to set time is determined by the size of this divider. The OR gate directs either the slow clock frequency or the fast clock frequency into the main counter. The main counter is composed of three four-stage binary up/down counters, which provide the demonstration unit with a maximum of 4,096 discrete time settings. The last count from the main counter provides the trigger pulse for the SCR. The SCR is a low-cost, low-current SCR with a 25-ampere peak current rating. The power supply capacitor is a small electrolytic capacitor, and the charging diode is a low-cost silicon diode.

The presettable counter is the principal component of this setter. A time setting can be preset into the counter at any time before the pickle switch is depressed. The required input is a parallel binary-coded decimal (BCD) format. In the setter the input is set by several BCD switches and the outputs are fed through a diode matrix to obtain the proper code for the presettable counter. The output of the umbilical line driver is at ground potential and the 20-microsecond delay is blocked as long as the energizing switch is off. When the switch is turned on, the output immediately rises to +15 volts to charge the power capacitor in the fuze; simultaneously, the 20-microsecond delay is enabled to allow a pickle pulse to pass. After a minimum of 100 milliseconds, the capacitor in the fuze is fully charged and the fuze is ready to accept a set pulse. When the pickle switch is pressed, the line driver output immediately returns to ground potential. The pickle pulse is then delayed approximately 20 microseconds and is synchronized with the 128 kHz clock to assure that the set-pulse width is an integral number of setter clock pulses. The 20-microsecond delay is incorporated to assure proper timing of the set pulse through the fuze input logic. The delayed pickle pulse turns the control gate on, which passes clock pulses to the presettable counter and simultaneously causes the umbilical line driver output to drop to -15 volts. The counter counts the number of clock pulses and, on the last pulse required to equal the preset number, the counter delivers an output pulse that turns the gate off. This stops the counter and causes the line driver voltage to return to ground potential. The DTF is now charged, set, and ready to start the countdown upon separation.

The parameters of maximum delay time, delay time precision (the number of increments in the delay time interval), and maximum set time-all of which are variables left to the choice of the designer--were selected arbitrarily for the DTF unit. The basic parameter is delay time precision, or the number of counts the main counter can store. In the DTF UNIT, the main counter has a capacity of 4,096 counts, which yields approximately 0.1% delay time precision. The ratio between the set time and the corresponding delay time is determined by the size of the divider (128 in FIG. 2A). The clock frequency is constrained by the desired maximum delay time, the maximum acceptable increment of the delay time, and the sizes of the divider and main counter. In the case of the DTF demonstration unit, the requiured clock frequency was determined to be 60 kilohertz. The relationships between these parameters are described in the follow equations.

The size of the divider is determined by the equation ##EQU2## where N.sub.d =the set-time compression factor

t.sub.d (max)=the maximum design delay time

t.sub.s (max)=the maximum acceptable set time

To keep complexity low, the actual divider size, N.sub.d ', should be equal to 2.sup.n, where n is the number of binary stages in the divider. Since the calculated value of N.sub.d usually implies a noninteger value of n, the next larger integer value would be selected. The actual maximum set time, t.sub.s '(max), can be found from ##EQU3## The size of the main counter, N.sub.C, is found from ##EQU4## where t.sub.i (max)=the maximum acceptable increment of the delay time. N.sub.C usually implies a noninteger value of n. Again, the next larger value of the actual counter size, N.sub.C ', should be selected. In determining the clock frequency, the upper and lower limits, f.sub.c (max) and f.sub.c (min), respectively, must be determined from ##EQU5## The nominal clock frequency, f.sub.c (nom), is then determined from

and the permissible tolerance (in percent) for the frequency of the clock, .delta.f.sub.c, is found by ##EQU6## Since f.sub.c (max) and f.sub.c (min) are determined by different criteria, it is possible that the clock frequency tolerance .delta.f.sub.c, will be smaller than desired or even negative. In this case it is necessary to select the next larger N.sub.C ' and reevaluate. The required short-term clock stability, .delta.f.sub.cst (in percent), is given by ##EQU7## This stability must be maintained from the beginning of the set time interval to the end of the delay time.

An example may clarify the application of these formulas. From a hypothetical system performance goal the following parameters were established:

t.sub.i (max)=25 msec

t.sub.d (max)=45 sec

t.sub.s (max)=100 msec

From Equation 4 the size of the divider is determined ##EQU8## The next higher integral 2.sup.n is 512, with n=9. From Equation 5 the actual maximum set time is ##EQU9## The size of the main counter from Equation 6 is ##EQU10## The next larger integral, 2.sup.n, is 2,058, which represents an 11-stage binary counter. Thus, N.sub.C '=2,048. The upper and lower limits of the clock frequency, from Equation 7 and 8, are ##EQU11## Equations 9 and 10 yield the nominal clock frequency and the required clock frequency tolerance ##EQU12## This required clock frequency tolerance would be unacceptable for any mass-produced clock except a crystal-controlled clock. To permit greater flexibility in clock design, the actual main counter size, N.sub.C ', is increased by one stage. The new N.sub.C 'is

Equations 7, 9, and 10 are reevaluated to yield the following results

The required short term clock stability from Equation 11 is ##EQU13## Referring to Equation 8, if f.sub.c (min) is replaced by f.sub.c (nom) and t.sub.i (max) by t.sub.i (nom), and the equation is solved for t.sub.i (nom), the following results are found ##EQU14## The nominal time increment now has been considerably improved over that of the design specifications. This improvement and the improved clock specifications resulted from the addition of one more counter stage to the existing 20 stages. This addition represents a 5% increase in complexity, with better than a 40% nominal performance increase. This type of performance improvement versus added complexity is characteristic of digital systems and is in direct contrast to analog systems, where added complexity produces light performance improvement.