Optical Residue Arithmetic Computer Having Programmable Computation Module

The present invention generally relates to numerical computing systems, and deals more particularly with a computer having a plurality of optically based computational modules adapted to process data using the residue arithmetic system.

Residue arithmetic is one of the fastest numerical computing methods available due to its parallel arithmetic computational properties. Computation methods using residue arithmetic are particularly suited for implementation using optical processors arranged to operate on data using pipelining techniques. Optical numerical computers possess several advantages over electronic computers, including the inherent parallelism of optical systems, the possibility of wave length multiplexing, and the short propagation time of optical signals.

The residue number system is extremely well matched to optical computing systems due to the fact that no carry mechanism is needed in residue arithmetic. This allows all the computations to be performed in parallel, without the need for interconnection between the results of sub-calculations until the final decoding step, which returns the calculation results to a more conventional number system. Also, the residue number system decomposes a calculation into sub-calculations of smaller computational complexity. Once a calculation requiring a large dynamic range is decomposed into segments that can be handled directly by conventional analog methods, the full advantage of parallel processing using optical computer systems can be utilized to handle these segments.

Optical processors using special maps to perform residue arithmetic implemented by optical processors are known per se in the art. See, for example, "optical computation using residue arithmetic", by HUANG, et al, Applied Optics, Vol. 18, No. 2, Jan. 15, 1979. As mentioned previously, the main characteristic of the residue number system is that there are no carries, thus all of the columns of a calculation can be processed in parallel. The residue number system is based upon N fixed, prime integers m.sub.1, m.sub.2, . . . , m.sub.N, which are called moduli. For example, for a residue number system based on moduli 2, 3, 5 and 7, an integer number X=14 can be represented as 14=(R.sub.1, R.sub.2, R.sub.3, R.sub.4)=(0, 2, 4, 0), that is, a number represented by the series of integers which constitute the remainders, or residues when that number is divided by each of the chosen moduli of the residue number system.

In the performance of basic arithmetic operations, computations with respect to each of the residues may be carried out independently because of the absence of carry as noted above. For example, in the addition of two numbers in the residue number system, the two residues of each modules are added and the residue representation of the sum of the two numbers will simply be the ensemble of the sums of the individual residues. That is, if (A.sub.1, A.sub.2, . . . , A.sub.N) and (B.sub.1, B.sub.2, . . . , B.sub.N) are the residue representations of A and B, respectively, then A+B=(A.sub.1 +B.sub.1), (A.sub.2 +B.sub.2), . . . (A.sub.N +B.sub.N). Subtraction and multiplication operations are equally simple, while division is more difficult in the residue number system and generally involves several steps. Effort is usually made to structure algorithms so as to avoid the necessity for division.

Because the residues which collectively constitute a numerical representation in the residue number system may be processed separately to generate partial functions which collectively constitute the numerical representation of an arithmetic function of two input numerical representations, an arithmetic processor for residue numbers may be constructed from a plurality of modules, each of which operates on a single residue in the numerical representation of a number being arithmetically processed. Since the non-divisional processing of each residue only requires a single step, and no carries are involved, the entire arithmetic operation can be performed in a single step, with the output of each of the processor modules providing one residue representation of the output of the processor.

In residue arithmetic, the functions of varying numbers are cyclical. That is, the residue for a single modulus ranges between zero and that modulus. This feature allows the use of maps to generate the functions of a given arithmetic operation of a variable residue. The input to the map is a signal representative of a variable residue and the output signal is a representation of the function of the input and the given operation. For example, the truth table for A+4=C modulo 5 is:

This can be implemented in the two dimensional map shown in FIG. 2. Electronic computers based on hardware or software maps of this type have required a look-up table or some form of external logic for the selection of the appropriate map. After the map is selected for the desired function, the map is then implemented optically, electro-optically or electronically.

The use of look-up tables or additional decision logic for the selection of the appropriate map substantially adds to total computational time. Optical implementation of the mapping concept mentioned above has the benefit of increasing computational speed, however, those prior art optical systems proposed for implementing the mapping technique lack flexibility and are rather complicated in their approach to selecting and programming the maps.

Accordingly, it is a primary object of the present invention to provide a computing system based on residue arithmetic which employs a plurality of optical computing modules to perform computations.

Another object of the present invention is to provide a computational module as described above which may be easily programmed to perform addition, subtraction, multiplication and division using electronic pulses.

A still further object of the invention is to provide a computing system of the type described above in which the computation modules may be interconnected to perform complex mathematical computation, coding, decoding, and scaling.

Another object of the invention is to provide a computing system as described above in which the computational modules are connected in chains to allow parallel, sequential computation operations to be performed.

These and further objects of the invention will become clear or will be made apparent during the course of the following description of a preferred embodiment of the present invention.

An optical computer comprises a plurality of interconnected computational modules which perform complex mathematical computations using the residue number system. Each computational module comprises an array of optical switches in a form of directional wave guide couplers interconnected by optical transmission paths to form a series of maps corresponding to a given modulus. The optical switches are arranged in groups of rows which may be selectively programmed to adapt the modules to perform addition, subtraction, multiplication, or division. Light pulse inputs to each module are spatially arranged such that a given residue input results in the automatic selection of the proper map, and the light pulse outputs from the last row of switches corresponds to the function of two residues which has been computed. The path of light pulses through the rows of optical switches is determined by a plurality of bi-stable electrical switches respectively associated with each row of optical switches and operable for simultaneously switching all of the optical switches in that row, thereby altering the path of light pulses as it passes through such row.

In the drawings, wherein like components are designated by identical reference numerals in the various views:

FIG. 1 is a diagrammatic view of an optical switch forming part of the computational module of the present invention;

FIG. 2 is a series of map diagrams for modulo 5 employed to perform addition operations;

FIG. 3 is a combined block and schematic diagram of a computation module embodying the maps of FIG. 2;

FIG. 4 is a combined block and schematic diagram of a computation module similar to that shown in FIG. 3 but adapted for performing subtraction operations;

FIG. 5 is a transform table for the modulus 5;

FIG. 6 is a diagrammatic view showing how multiplication may be carried out for modulo 5 in accordance with the present invention;

FIG. 7 is a combined block and schematic diagram of a computational module in accordance with the present invention suitable for carrying out multiplication operations using modulo 5;

FIG. 8 is a schematic diagram of an addition module or modulo 5 suitable for conversion to modulo 4;

FIG. 9 is a combined schematic block diagram depicting multiplication and addition modules interconnected to compute functions of residues for modulo 5;

FIG. 10 is a diagrammatic view of a programmable multi-purpose computational module in accordance with the present invention;

FIG. 11 is a detailed schematic view of the module shown in FIG. 10;

FIG. 12A is a block diagram view showing a pair of the modules of FIG. 11 interconnected to perform addition for modulo 5;

FIG. 12B is a view similar to FIG. 12A but showing one arrangement for interconnecting the module to perform multiplication operations;

FIG. 12C is a view similar to FIG. 12B but showing alternate arrangement for interconnecting the modules to perform multiplication operations;

FIG. 12D is a view similar to FIG. 12C but showing the modules adapted for performing division operations;

FIG. 13 is a block diagram showing a plurality of the modules of FIG. 10 interconnected to evaluate the polynomial X.sup.3 +4X.sup.2 +3X+2;

FIGS. 14A and 14B in conjunction are block diagrams showing the arrangement of a series of the modules of FIG. 10 interconnected to perform multiplication of matrices;

FIG. 15 is a block diagram of one arrangement for encoding data into the residue number system;

FIG. 16 is a block diagram of an arrangement for decoding residue numbers output by the computer system of the present invention; and

FIG. 17 is a schematic diagram of an optical data register.

Before discussing the present invention in detail it will be helpful for purposes of later discussion to review several basic concepts related to the residue number system. The residue number system is based on N relatively prime integers m.sub.1, m.sub.2 . . . m.sub.N called moduli. A number X can be represented in this residue number system as r.sub.m.sbsb.1, r.sub.m.sbsb.2, . . . r.sub.m.sbsb.N. The residue r.sub.m.sbsb.i can also be written as .vertline.X.vertline..sub.m.sbsb.i and it is the remainder of the X/m.sub.i division operation. For example, with X=24 and m.sub.i =5, the residue for modulus 5 would be

The number of integers that can be represented uniquely by the residue number system is ##EQU1## The residue representation is cyclic over the range M. That is, the representations are the same for integers K, K+M, K+2M, etc. Ordinarily, only positive numbers are represented by the residue number system. However, negative numbers can also be represented by letting numbers 0 to M/2-1 represent positive integers and M/2 to M-1 represent negative integers such that M/2.ident.-M/2 and M-1.ident.-1.

Operations involving addition, subtraction, multiplication and division may be carried out in the residue number system as will be discussed in more detail later. In order to implement the electro-optical computer of the present invention, computation modules incorporating a plurality of directional coupler wave guide switches generally indicated by the numeral 20 in FIG. 1 are employed. As shown in FIG. 1, a pair of optical wave guides 22 and 24 are placed in physically proximate relationship to each other such that in the absence of an externally applied electric field, the wave guides 22 and 24 operate in synchronism with each other. In other words, a light wave entering one of the wave guides from the input thereof is coupled to the adjacent wave guide so as to produce a switch in the light path through the directional coupler. For example, light waves entering the input end of wave guide 24 are coupled to the wave guide 22 and exit from the coupler at the output end of wave guide 22 denoted as I.sub.out 1. A primary electrode 26 coupled with a positive supply of voltage V.sub.T is interposed between the wave guides 22 and 24, while a pair of ground electrodes 28 and 30 are respectively disposed on opposite sides of the wave guides 22 and 24 whereby the latter are sandwiched between the primary electrode 26 and one of the ground electrodes 28 and 30. When voltage V.sub.T is applied to electrode 26, an electric field is created between electrode 26 and ground electrodes 28 and 30. Such an electric field interrupts the synchronism of the coupler 20 such that light entering the input in one of the wave guides 22 or 24 remains in that wave guide and is prevented from being coupled to the other wave guide. Thus, as shown in FIG. 1, in the absence of voltage being applied to electrode 26, light delivered to the input end of wave guide 24 exits from the directional coupler via the output end of wave guide 22; however, when voltage is applied to the electrode 26, light input to wave guide 24 remains in such wave guide and exits from the coupler 20 at the output end (I.sub.out 2) of wave guide 24. For purposes of simplicity, the ground electrodes 28 and 30 will be deleted from the remaining discussion and the drawings.

The addition operation in the residue numbering system comprises essentially a shifting operation wherein an input light beam is shifted by K positions for the operation +K as is illustrated in FIG. 2 for the modulus 5. The diagrams of FIG. 2 spatially map the various possible residue inputs for modulus 5 so as to provide an output in spatially oriented form corresponding to a given addition operation. Similar maps may be devised for the operations of subtraction, multiplication and division. Previously, however, implementing such maps to perform arithmetic functions required a logic or look-up table in order to select the appropriate map. Using the directional coupler shown in FIG. 1, however, such map is inherently implemented in an electro-optical computation module, the heart of which comprises an adder whose details of construction are shown in FIG. 3 for the modulo 5. As shown in FIG. 3, the computation module includes a first set of 5 light inputs 32 numbered 0-4 and a second set of 5 electrical inputs 34, numbered +0-+4. Additionally, the module includes a set 36 of 5 light outputs indicated by the numeral 0-4 vertically aligned with the light inputs 32. The adder module shown in FIG. 3 comprises a plurality of aligned rows and columns of the directional couplers 20. One of the wave guides 24 of each of the directional couplers 20 and the upper row thereof define the light inputs 32, while the light outputs 36 comprise one or more combinations of the outputs of the directional couplers 20 in the bottom row thereof.

The directional couplers or light switches 20 in the various rows and columns thereof are interconnected with each other by means of optical transmission paths so as to incorporate each of the maps depicted in FIG. 2. The electrodes 26 of the directional couplers 20 of each row thereof are interconnected by an electrical line 38 which is in turn connected to the Q output of a bi-stable switching device such as the RS type flip-flops 40. The R inputs of flip-flops 40 are each connected to a reset pulse source, while the S inputs thereof define the electrical inputs 34. Normally, voltage is present on each of the lines 38 such that light delivered into each of the inputs 32 is output on the corresponding outputs 36; thus, light signals remain in the wave guide in which it originates during its passage through the module. In order to form the module for a +2 operation of example, a signal is applied to the +2 input 34 thereby actuating the set input of the corresponding flip-flop 40. This set input removes the voltage from the Q output, thereby removing voltage from each of the electrodes 26 of the directional couplers in the next to bottom row thereof. With the next to bottom row of couplers 20 having been thusly switched, light propagating through the module from the inputs 32 will have its source altered by the row of switched couplers in accordance with the mapped optical transmission paths so as to deliver such light signal on one of the light outputs 36 in accordance with the spatial input position wherein the light signal was input to the module along the inputs 32. It may therefore be appreciated that the computation adder module shown in FIG. 3 may be simply programmed by applying various combinations of input pulses to the electrical inputs 34 in order to select various premapped transmission paths which alter the optical path of light signals passing through the module in order to form the desired operation. It should be noted, at this point, that the initial voltage of each of the electrodes 26 could be set at zero and the interconnection of the wave guides 24 altered so that the module might then be programmed by selectively energizing the lines 38 to switch the couplers in a corresponding row. For convenience of explanation, however, those embodiments of the present invention discussed herein will each be assumed to operate with voltages normally being applied to the electrodes 26 with interruption of such voltage causing a switch in optical paths as discussed above.

Subtraction can be performed in connection with the present invention using the additive inverse .vertline.-K.vertline..sub.m.sbsb.i of a residue number K which is defined such that

A fixed one-to-one correspondence exits between a residue number and its additive inverse. The additive inverse transformation can therefore be implemented by a fixed map, and by adding this transformation map to an adder computation module, such module can be such as shown in FIG. 4 for modulus 5.

Multiplication can be implemented directly using the computational module of the present invention using m.sub.i maps for the operations of x0, x1, x2, . . . , x(m.sub.i -1). Alternatively, a homomorphic approach may be employed where a modulo m.sub.i multiplication is converted into a modulo m.sub.i -1 additive operation. Using this latter approach a log.sub.b K-like forward transform is first performed on the operands. A modulo m.sub.i -1 addition is then performed and the sum is inverse transformed by a b.sup.K -like transform to obtain the product of the two original numbers. The transform table for modulus 5 is shown in FIG. 5, and the process is illustrated diagrammatically in FIG. 6. Although the log.sub.b K-like transformation for the value 0 is not defined, it is known that if either the multiplier or the multiplicand is 0, the product is 0. A modulo 5 multiplier is shown in FIG. 7 using this homomorphic approach in which a modulo 4 adder 44 is coupled with an additional row 46 of the coupler 20. In order to carry out modulo 5 multiplication, a modulo 4 addition is performed. Thus, in order to convert a modulo 5 adder into a modulo 5 multiplier, the modulo 5 adder is preferably designated in such a way that it can be easily converted into a modulo 4 adder. This can be achieved with the design shown in FIG. 8 in which additional couplers 48, 50 and 52 have been provided which are coupled with an independently controllable voltage source 54. It is to be noted that while the concept described above can be applied to an adder of any modulus, this homomorphic approach can be used only if the modulus is prime.

One feature of the module design described above is that the input, output and programming controls are all represented spatially in the same way. This allows the interconnection of the computational modules to perform sequential operations. The outputs of one module can be connected directly to the inputs of the next module or it can be used to program the map of the next adder module as illustrated in FIG. 9. An electrical pulse is sent to the first multiplier module 53 on one of the program control inputs 54 to program it to perform the operation x.vertline.X.vertline..sub.m.sbsb.i where m.sub.i is the modulus. A light pulse is then delivered into the light inputs 55 of the multiplier module 53 at the spatial position corresponding to .vertline.Y.vertline..sub.m.sbsb.i. The exit position of the light beam from multiplier module 53 would correspond to .vertline.X.times.Y.vertline..sub.m.sbsb.i. A fast avalanche photo diode 60 is connected to each of the output wave guides 62 of multiplier module 53. The exiting light pulse will be detected by the corresponding photo diode 60 which generates an electrical output pulse. The electrical output pulse, in turn triggers the corresponding flip-flop 40 of the next adder module 58 thereby setting or "programming" it for the +.vertline.X.times.Y.vertline..sub.m.sbsb.i operation. Another light pulse is then injected into the input 64 of the adder module 58 at the position corresponding to .vertline.Z.vertline..sub.m.sbsb.i. The position where the light pulse exits at 56 from adder module 58 represents the sum of .vertline.X.times.Y+Z.vertline..sub.m.sbsb.i.

Attention is now directed to FIG. 10 wherein a multi-purpose, programmable computation module capable of forming addition, subtraction, multiplication and division operations is depicted. The multi-purpose programmable module 66 comprises 4 interconnected sections, namely, a log.sub.b K-like transform 68, an additive inverse transform (-K) 70, a modulo m.sub.i adder 72 and a b.sup.K -like transform 74. The modulo m.sub.i adder 72 is adapted to perform modulo m.sub.i -1 addition and the additive inverse transform (-K) section 70 is adapted to be converted into a .vertline.-K.vertline..sub.m.sbsb.i.sub.-1 transform, when the module 66 is programmed to perform multiplication and division respectively. As in the case of modules previously described above, the multi-purpose programmable module 66 is provided with a plurality of light inputs 76, a plurality of light outputs 78, and a plurality of program control, electrical inputs 80 operably connected with the modulo m.sub.i adder section 72. Additionally, sections 68, 70 and 74 are further provided with corresponding electrical inputs 82, 84 and 86. The module 66 is simply programmed to perform the desired arithmetic operation by providing binary input signals on the inputs 80, 82, 84 and 86. For example, in order to program the module 66 to perform addition, appropriate signals are delivered to inputs 82, 84 and 86 in order to disable sections 68, 70 and 74, while appropriate signals are applied to inputs 80 in order to program the adder section 72. The programming of the modules 66 for performing the arithmetic operation X+Y is shown more particularly in FIG. 12A wherein the program control inputs 80 of a module 66 are operably coupled to the light outputs of another module 66A to receive values of X. The light input 76 of module 66 receive the values of Y. Lines 82, 84 and 86 are held low, and the function X+ Y appears at the light output 78 of module 66. The arrangement shown in FIG. 12A may be readily adapted to perform the operation X-Y simply by delivering a high signal on line 84 thereby enabling section 70.

The computational modules 66 shown in FIG. 10 may be readily adapted to perform multiplication operations in either of two ways as indicated in FIGS. 12B and 12C. As shown in FIG. 12C, the light outputs of module 66A are connected to the corresponding programmable inputs 80 of module 66. Sections 70 and 74 of module 66A are held low and section 68 of module 66A is held high, while section 70 of module 66 is held low and sections 68 and 74 of module 66 are held high. While section 74 of module 66 shown in FIG. 12C is enabled to perform an inverse transform, both sections 74 of module 66 and 66A shown in 12B are enabled to perform inverse transforms on the multiplier (X) and multiplicand (Y). The approach depicted in FIG. 12C is advantageous in that the connection of the program control input leads 80 do not have to be altered, thus allowing the module 66 to be simply reprogrammed to perform addition when desired. Also, the arrangement shown in FIG. 12C provides additional flexibility with respect to performing division operations.

The module 66 shown in FIG. 10 may be adapted to perform division operations as shown in FIG. 12D. Before discussing division operations, it is appropriate here to discuss generally division operations in the residue arithmetic system. Division can be performed using the same homomorphic approach, converting a modulo m.sub.i division into a modulo m.sub.i -1 subtraction. However, this can be done only if the quotient is an integer (i.e., no remainder). There are several methods that can be employed for general division but each requires cumbersome sequential procedures. Moreover, these methods provide only a roundoff results since fractions cannot be represented in the residue number system. For this reason, residue arithmetic is generally applied to problems that do not require division operations such as matrix multiplication. Nevertheless it is often times useful to employ division operations where such operations are limited to the remainder zero case. One division operation involving the remainder zero case relates to scaling. In order to maintain the values within the range of the residue number system, it may be necessary to periodically scale the values down by a factor of K. Scaling can be achieved by division if K is a value of one of the moduli or the product of two or more moduli. As shown in FIG. 12D, module 66A is programmed by sections 68 and 70 which are enabled while section 74 is disabled. Thus, an additive inverse transform of the values of X is required for the division X after the log.sub.2 K-like transform is performed. Sections 68 and 74 of module 66 are enabled while section 70 thereof is disabled. The resulting light output from module 66 corresponds to the operation Y divided by X. In order to perform the operation of X divided by Y, section 70 of module 66A is disabled while section 70 of module 66 is enabled.

One suitable design for the module 66 shown in FIG. 10 is depicted in detail in FIG. 11 for the modulo 5. As shown in FIG. 11, each of the inputs 34, 82, 84 and 86 form the set inputs of respectively associated flip-flops 40. Section 68 includes one row of the couplers 20, the second row thereof being controlled by the 0 control input 34. The third row of directional couplers 20 form the additive inverse transform section 70 and are under control of line 84. The fourth row of directional couplers 20 also form a part of section 68 and are under control of line 82. Essentially, rows five through eight of directional couplers 20 form the adder section 72, and section 74 comprises directional couplers 48, 50, 52 and 20a which are controlled by line 86. A directional coupler 20b in the lower left-hand corner of module 66 also forms a part of section 68 and is under control of line 82. When performing an addition operation, a light pulse injected into any of the inputs 76 propagates undeviated along the same input wave guide through the upper four rows of directional couplers 4 since lines 82 and 84 are held low. Likewise, since line 86 is low, section 74 is off and the light outputs of the adder portion of module 66 propagate undeviated to the light output 78. During subtraction operations, with section 70 turned on, the path of light pulses propagating through the module 66 deviate in accordance with the transform map shown in FIG. 6. It is to be noted that, while operating in the addition and subtraction modes, with section 68 disabled, an input on the 0 input control line 80 has no effect on the path taken by light through the module. Thus, the position of the exit light beam would be the same as that of the input light beam for a +0 operation. The additional coupler 20b is provided only when it is desired to interconnect the modules in a manner depicted in FIG. 12C. Coupler 20 is activated along with section 68, as mentioned previously. When the value of the multiplier X is 0, the 0 input control 80 of module 66 shown in FIG. 12C is turned on and the multiplication sign 0 operation is then performed. If the multiplier is 1, its log.sub.2 K-like transform is 0; the purpose of the extra coupler 20b is to maintain the transformed 0 output of the multiplier from setting the 0 control input 34 of module 66.

As an example of how the computation modules of the present invention can be interconnected to perform various mathematical calculations, reference is now made to FIG. 13 wherein an interconnected arrangement of the modules for modulo 5 are interconnected in a manner to compute X.sup.3 +4X.sup.2 +3X+2. As shown in FIG. 13, three computation modules 88, 90 and 92, similar to that depicted in FIGS. 10 and 11, have their light outputs operably connected with the program control inputs of three additional computational modules 94, 96 and 98. Modules 88-92 are programmed to perform multiplication operations while modules 94-98 are programmed to perform addition. The coefficients of X, i.e., 1, 4 and 3 are entered into the respective program control inputs of modules 88-92 while the values of X are input to the light inputs of modules 88-92. The output from module 88 corresponds to X.sup.3, while the outputs of modules 90 and 92 respectively correspond to the 4X.sup.2 and 3X values. Thus, adder module 94 has the control inputs thereof set by the X.sup.3 output of module 88, adder module 96 has the program control inputs thereof set by the 4X.sup.2 output of module 90, and the program control inputs of adder module 98 are set by the value of 3X output from module 92. Next, the +2 value of the equation to be computed is input on the number 2 light input of adder module 98. Modules 94, 96 and 98 then proceed to add the values of X.sup.3 to 4X.sup.2, 3X and 2 in order to complete the computation.

The computation time required to compute a value of the desired polynomial is equal to the period needed to program the program control inputs of adder modules 94-98 in addition to the propagation time through four of the modules. The propagation time through a single module of approximately one-half inch in length is approximately forty pico-seconds. The time required to program each of the addition modules 94-98 is equal to the sum of the detection delay of the photo diodes 60, the switching delay of the flip-flops 40 and the switching time of the wave guide couplers 20. It is thus possible to achieve a set or programming time of two nano-seconds for the computational modules. Assuming that an additional one nano-second is required for a light pulse to pass through the module and to reset the flip-flops, the throughput rate is about one calculation every 3 nano-seconds or about 333 MHz. Due to the fact that the modules are interconnected in parallel with each other, the computational time is approximately equal for polynomials of any order.

One of the most important applications of the numerical optical computer is the multiplication of matrices. This application can be extended to a number of transform operations such as DFT, Hadamard transforms and the like. For purposes of illustrating the application of the present computational module to matrix multiplication, reference is now made to FIGS. 14A and 14B wherein an interconnected arrangement of modules is depicted suitable for carrying out matrix multiplication for the general case of [A].sub.M.times.N [B].sub.N.times.P =[C].sub.M.times.P. The coefficients of the master matrix [B].sub.N.times.P are stored in the modules 100-107 as multipliers. The values of the matrix [A].sub.M.times.N pass through the multiplier modules as light inputs to 100-106, row by row setting or "programming" the corresponding row of adder modules 108-114. Light pulses are entered into the first row of adder modules 108-114, providing in parallel the values of the first row of [C.sub.1,1 ] at the output of module 108. Simultaneously, A.sub.1,1, A.sub.1,2, . . . A.sub.1,n are multiplied by B.sub.1,2, B.sub.2,2, . . . B.sub.n,2. In the second row of multipliers (not shown) and a second row of adders (not shown) adds the results to produce C.sub.1,2. Thus the output C.sub.1,p from adder 116 occurs at the same time the other elements of matrix C's first row [C.sub.1,j ] are being produced. The flip-flops 40 are then reset, ready for the entries of the next row of [A].sub.M.times.N. The total computation time is equal to M+1 set-reset times of the modules and the number of computation modules required is 2NP. For example, to multiply two 10.times.10 matrices, the computation time would be about 30 nsec if we assume a module set-reset time of 3 nsec and the use of 200 computation modules for each modulus.

Before computation can be performed with the computation modules of the present invention, the input thereto must be encoded into its equivalent residue number in the appropriate spatial representation. One simple approach to encoding is to convert the analog input into an intermediate binary form by using a conventional analog to digital converter or, alternatively, by means of integrated optics scheme. The binary input can then be converted into residue numbers in the spatial form with the arrangement shown in FIG. 15. Note that for modulus 5, ##EQU2## Thus, it is apparent that encoding can be performed in one set time of a computation module.

Decoding a residue number is a more complicated operation than encoding. One suitable method of decoding consists of converting the residue number into the mixed radix system. The conversion method can be performed with the same type of hardware used for the basic residue arithmetic computations discussed above. The algorithm shown schematically in FIG. 16 may be employed for decoding a residue number for moduli 2, 3, 5, 7 and 11. .vertline.1//K.vertline..sub.m.sbsb.i represents the multiplicative inverse of the residue K in the modulus m.sub.i system, where .vertline.K.times..vertline.1//K.vertline..sub.m.sbsb.i .vertline..sub.m.sbsb. =1. For example, the inverse of 3 modulo 5 (1//3.sub.5) is 2 because .vertline.3.times.2.vertline..sub.5 =1. To decode a number which has been encoded in a residue representation, a series of subtractions and divisions are performed on the residues, r.sub.m.sbsb.i, which form the encoded number. The result is a set of coefficients, a.sub.i, which, when multiplied by predetermined weighting factors, produce a decoded number. An example of this method is shown in FIG. 16 for moduli 2, 3, 5, 7 and 11. The number 58, which has been encoded, as described earlier, as 0, 1, 3, 2, 3 corresponding to r.sub.2, r.sub.3, r.sub.5, r.sub.7 and r.sub.11, respectively, is decoded by first subtracting the first coefficient, a.sub.i, from each residue r.sub.3 through r.sub.11 in the appropriate modulus. The resulting residue is then multiplied by the inverse of the first modulus, modulus 2. To illustrate, coefficient a.sub.3 is found in FIG. 16 using the following modulus 5 calculations:

Step 1: .vertline.r.sub.5 -a.sub.1 .vertline..sub.5 =.vertline.3-0.vertline..sub.5 =3

Step 2: .vertline.3.multidot..vertline.1//2.vertline..sub.5 .vertline..sub.5 =.vertline.3.multidot.3.vertline..sub.5 =4

Step 3: .vertline.4-a.sub.2 .vertline..sub.5 =.vertline.4-2.vertline..sub.5 =2

Step 4: .vertline.2.multidot.1//3.vertline..sub.5 .vertline..sub.5 =.vertline.2.multidot.2.vertline..sub.5 =4=a.sub.3

This procedure requires N-1 sequential steps where N is the number of moduli used. Since encoding and 1 computation can be performed per one set-reset time of a module, this sequential decoding procedure would seemingly form a bottleneck for the entire decoding process. However, "bottlenecking" is avoided since the computation modules may be connected in a manner to perform pipeline processing. To pipeline the operation, the coefficients obtained earlier in the procedure are synchronously delayed such that all the coefficients advance through the decoding procedure at the same rate. This necessary delay can be accomplished by setting an adder for +K where K is the number to be stored temporarily. The number is recalled by sending a light pulse into the input port corresponding to 0. Alternatively, it can be achieved with the use of the simple data register module shown in FIG. 17. It is also to be noted that the multiplying factors .vertline.1//m.sub.i .vertline.m.sub.j are fixed and can therefore be implemented by fixed maps.

Residue to mixed radix conversion is a very important procedure in residue arithmetic. Besides decoding the output, the conversion is used for other important operations such as sign detection, magnitude comparison, and overflow detection. Pipelining the procedure is therefore an important concept in an optical numerical computer using residue arithmetic. The original residue number may be stored in a cascade of data registers while it is being converted into the mixed radix form for condition check. The residue number is moved down at the same rate as the conversion process and the computation is continued after the checking is completed. Alternatively, after the residue numbers are converted into their mixed radix equivalent for sign detection or overflow detection, they can be converted back into the residue form for further computation. The inverse conversion (mixed radix to residue) can be achieved very easily, and once again in one set time of the computation module.

Overflow is a much more serious problem in residue arithmetic than in conventional arithmetic which utilizes a weighted number system. Not only is the residue for each individual modulus cyclic, the residue number system is also cyclic over its range M. The same representation is repeated for integers K, K+M, K+2M, etc. Overflow detection is not automatic as with weighted number systems and it is generally wise to avoid situations where overflow may occur. For some computations, this would require a periodic downscaling of the residue numbers. To do this, division operations would be necessary. As pointed out earlier, general division cannot be carried out easily and scaling by an arbitrary factor would not be practical. A residue number can be scaled however by a factor equal to the value of one of the moduli or a product of two or more moduli. For example, for a system with moduli 2, 3, 5, 7, a number X=191=[1, 2, 1, 2] would be scaled down by a factor of 7. Since the divisor 7 is also a modulus, the corresponding residue X.sub.7 =2 would be equal to the remainder when the number X is divided by 7. Therefore, X-X.sub.7 is always exactly divisible by 7 and the homomorphic approach can be applied for the division operation. However, for modulus 7, the divisor is equal to 0 and division by 0 is not defined. The general approach is to proceed with the division while ignoring modulus 7. The residue of the quotient for modulus 7 is then obtained using the extension of base procedure. It is essentially a residue to mixed radix conversion. The entire scaling operation can be pipelined to maintain the throughput rate of 1 per one set-reset time of a computation module.

In view of the foregoing, it is apparent that the electro-optical computer and computational module described above not only provides for the reliable accomplishment of the object of the invention but does so in a particularly effective and economical manner. It may be appreciated that the computation module of the present invention allow the operand and operator to be combined in a single representation, without the need for data values to be recalled from storage, in as much as the stored value is entered into the module as an operator. Thus, the state of the module represents both the operand and the operation. The module therefore functions simultaneously as an adder and data storage device, thereby eliminating the need for a separate memory for values such as the coefficients of a reference function in correlation detection operations. Since the access time delay encountered when reading out stored values is eliminated, the inputs can be processed at a very rapid rate, especially for computations that are repeatedly performed.

It is recognized, of course, that those skilled in the art may make various modifications or additions to the preferred embodiment chosen to illustrate the invention without departing from the spirit and scope of the present contribution to the art. Accordingly, it is to be understood that the protection sought and to be afforded hereby should be deemed to extend to the subject matter claimed and all equivalents thereof fairly within the scope of the invention.