Background of the Invention
1. FIELD OF THE INVENTION
This invention relates generally to an ultrasonic length measuring system and more particularly, to an ultrasonic length measuring system which is extremely accurate and reliable in operation and which is especially adapted to measure the length of stressed bolts in situ.
2. PRIOR ART
It is generally well-known that there are numerous applications in which bolts as long as twelve feet and having cross-sectional diameters as large as six inches or more, are used in extremely high stress conditions to secure one part to another over a period of many years. For example, such large bolts may be used to secure the respective flanges of very large pipes or of valves in nuclear and refinery applications. Similarly, large bolts may be used to secure portions of a large vessel such as a nuclear reactor chamber or chemically reactive vessel where it is important that the bolts remain structurally viable despite the application of extremely high stresses over long periods of time. It is generally well-known that when such bolts are installed and tightened, it is important that the bolt's percentage of yield strength used be known to be sure that the bolt remains structurally viable. One method of determining the percentage of yield strength used is by measuring the bolt elongation resulting from the induced stress. For example, the best available high strength bolt material which has a yield strength of 240 Kpsi., will elongate 3.2 thousandths of an inch per inch of grip length at 40% of yield strength and 4.8 thousandths of an inch per inch of grip length at 60% of yield strength. This 40% to 60% yield strength range is considered generally acceptable in terms of structural viability for a tightened bolt. Thus, by measuring the elongation of a bolt as it is being tightened, the structural integrity of the bolt can be assessed and the optimum elongation can be obtained for a particular bolt material and length.
One prior art technique for measuring the actual length, and thus the elongation of bolts under stress, incorporates ultrasonic thickness measuring devices. Such devices include a transducer that is placed at one end of the bolt and an electronic gauge that responds to the reflections induced by the transducer. The gauge determines the distance between the first and second ends of the bolt on the basis of the time between reflections and the assumed velocity of the acoustic energy transmitted therethrough. Then, by comparing the measured length of the bolt under stress with a record of the actual length of the bolt unstressed, such as prior to its installation, an inspector can determine the change in length resulting from the continuous application of high stress and thereby ascertain whether or not the bolt is still of reliable structural integrity.
It will be recognized by those familiar with the art to which the present invention pertains, that the accuracy and resolution of the stressed bolt length measurement must be sufficiently high so that the change of bolt length computed therefrom provides a reliable indication of the actual elongation of the stressed bolt subject to measurement. Unfortunately, there are a number of factors that affect the nominal acoustical velocity that one might ordinarily rely upon to determine the corresponding bolt length for a given measurement. These factors include the effect on velocity resulting from the birefringent characteristics of a bolt under stress, the temperature under which the measurement is being made, and the coefficient of thermal expansion of the material being tested. Accordingly, these factors will detrimentally affect the accuracy of the length measurement unless means are provided for compensating for such factors. Unfortunately, prior art devices that rely upon the transmission of acoustic energy for time measurement which can then be related to the thickness of a material under test, do not provide means for compensating for such factors and would accordingly, yield an inaccurate result when applied to the particular measurement function described above. In addition to these disadvantages of the prior art, it is also to be noted that such prior art devices are particularly adapted to the measurement of thicknesses in the range of a few hundreths of an inch to sixteen to twenty inches maximum. Accordingly, such devices are not readily adapted to measuring bolt lengths that extend to seven feet or even longer. In addition to these relative disadvantages of the prior art, such prior art devices are not readily adapted to provide the measurement resolution required to display length changes that may be as small as 0.0001 inches that may ordinarily be required to measure relatively small changes in bolt lengths induced by moderate stresses as compared to their unstressed configuration.
Irrespective of bolt size, because of their relatively complex shapes from the standpoint of acoustic echo characteristics, bolts are inherently difficult to accurately measure. For example, a typical threaded bolt has a multitude of surfaces which tend to produce spurious echos that increase the likelihood of measurement error. No known prior art utilizing acoustic measurement techniques has satisfactorily solved this problem.
The following U.S. Patents are deemed to be relevant to the present invention:
Of the above-identified patents some are relevant because they disclose measuring apparatus that utilize ultrasonic pulses for measuring the thickness of a test piece which may or may not be an elongated bolt and some are relevant because they disclose elongation measurement devices that are especially adapated to be used for measuring the elongation of bolts. The most relevant of the above-identified patents shall now be discussed in more detail.
The U.S. Pat. No. to Charbonnier et al (3,427,868) discloses an ultrasonic device for measuring the thickness of objects. The time period between a plurality of echo pulses is measured using a counter and a pulse duration multiplication circuit that permits the use of a low performance counter for measurement of the duration of a pulse that is proportional to the time interval between respective echos. Unfortunately, the Charbonnier patent does not disclose a device that is useable with elongated bolts, that is, a device that can overcome the special problems associated with length and elongation measurements as previously described. By way of example, Charbonnier does not disclose means for making temperature and stress factor corrections to the velocity of acoustic energy propagation, nor does it disclose means for measuring the nominal and elongated lengths of bolts that are as long as seven (7) feet or more. Furthermore, this patent does not disclose means for overcoming the special problems associated with noise and other reflection anomalies that are unique to ultrasonic measurement of elongated structures such as very long bolts.
Another form of ultrasonic thickness measuring system which utilizes a counter for measuring the interval between a transmitted burst and a reflected signal is disclosed by Kumer Jr. et al in U.S. Pat. No. 3,605,504. However, Kumer Jr. et al also fails to disclose a system which can overcome all the special problems associated with measuring the nominal length and elongation of a very long bolt.
The U.S. Pat. No. to McFaul et al (3,759,090) discloses an analog-type ultrasonic extensometer for measuring the elongation of a bolt. A meter is used to indicate when the time interval between the transmitted signal and the echo pulse from the far end of the bolt equals a preselected period of time which corresponds to a predetermined bolt length including bolt elongation due to stress. Although McFaul et al recognize the effects of temperature and stress on the accuracy of such measurements, they fail to disclose a convenient and accurate way of adjusting the measuring device to compensate for temperature and fail to disclose any means for adjusting for the effects of the velocity of acoustical energy in a stress bolt as compared to the velocity in an unstressed bolt by dismissing that change in velocity as being negligible and imperceptible in the meter readings of their device.
The U.S. Pat. No. to Makino et al (3,918,294) discloses a method for measuring the actual forces existing in bolts by applying an ultrasonic wave to the article under test to generate forced oscillations within the article, measuring a first natural frequency before the application of axial force, and measuring a second natural frequency subsequent to the application of axial force. Makino et al then determine the difference between those two frequencies and compare that difference against calibration data to determine the axial force during an actual test.
The U.S. Pat. No. to Dileo et al (3,985,022) discloses an ultrasonic measuring device which employs digital counting means and which provides an output indication of thickness of a work piece when the accumulated counts provided during successive time intervals of transmitted search pulses reaches a value that corresponds to a quantity of such search pulses which is commensurate with the acoustic velocity of the work piece. However, as with other prior art discussed previously, Dileo et al do not disclose means for accurately compensating for variations in acoustic velocity resulting from temperature and/or stress, nor do they disclose means for overcoming the special problems associated with measuring lengths of elongated bolts as previously described and as will be more fully understood hereinafter.
Summary of the Invention
The present invention overcomes or substantially reduces the aforementioned disadvantages of the prior art by providing an apparatus and process for measuring the length of stressed bolts to extreme accuracies, and includes means for inclusion of correction factors dependent upon the stressed condition of the bolt, the temperature in which the measurement is being made and the thermal correction coefficient of the material under test, to provide a length or length difference measurement which is based upon an accurate representation of the actual velocity of acoustical energy in the stressed bolt being tested. The apparatus utilizes a microprocessor-based digital system including a binary counter which is connected to an extremely high frequency oscillator. The counter is adapted to provide a high resolution count dependent upon the time interval between a first pulse entering the outer surface of the bolt under test at the probe input end, and a second pulse which is derived from the reflection return of the ultrasonic energy from the opposite end of the bolt.
The count is applied to a microprocessor-based computer for calculation of bolt length. The calculation also utilizes data input via thumbwheel switches and corresponding to material velocity, stress correction factor, measurement temperature, and thermal correction coefficient. In addition, a switch is provided for selecting digital display of either full bolt length or the difference between full elongation and an initial length which may be entered via an additional thumbwheel switch after it is measured using the invention or after it is copied from tabulated data. A unique digital filtering algorithm is used to ensure an accurate and stable measurement.
A novel receiver circuit is utilized to overcome the unique acoustical characteristics of threaded bolts. More specifically, a dual characteristic echo sensing circuit is used to ensure measurement accuracy despite acoustic pulse distortion that results from bolt stress, and a special gain contour circuit is used to further ensure measurement accuracy despite spurious acoustic echos that arise in threaded bolts.
Thus, the present invention provides a novel bolt elongation measurement apparatus and method which are designed to accommodate threaded bolts of virtually all shapes and sizes including very long bolts, with extreme measurement accuracy despite problems unique to such bolts. Stress and temperature induced inaccuracies of prior art devices are readily compensated for by means of thumbwheel switch entered correction factors and a microprocessor-based computer. Bolt stress and geometry induced inaccuracy of prior art devices is also readily compensated for in the present invention by a receiver designed to compensate for acoustic echo pulse distortion and to ignore anomalous echos as will be more fully understood hereinafter.
Objects
It is therefore a principal object of the present invention to provide an apparatus and method for measuring the extension of bolts under stress and which apparatus and method overcome or substantially reduce the aforementioned disadvantages of prior art devices.
It is another object of the present invention to provide an apparatus for measuring the length of bolts as long as seven feet or more and which provides means for achieving increased accuracy of measurement by including input signals representative of correction factors, the omission of which would otherwise render the result highly inaccurate.
It is still a further object of the present invention to provide a portable electrical device for measuring the elongation of stressed bolts in situ and which includes means for entering data representative of nominal length, nominal acoustic velocity, an acoustic velocity stress correction factor, temperature of the measurement, and thermal expansion coefficient; to provide a highly accurate digital representation of the bolt elongation.
It is still a further object of the present invention to provide a microprocessor-based portable electronic instrument for measuring the elongation of stressed bolts in situ (based upon the time of traversal of an acoustic pulse along the length of the bolt) in which the microprocessor is adapted to automatically incorporate acoustic velocity, stress correction factor, measurement temperature and thermal expansion coefficient in the calculation of the bolt elongation.
It is still another object of the present invention to provide a bolt extensometer which employs a novel receiver circuit to overcome the unique acoustical characteristics of a long threaded bolt. More specifically, the receiver circuit employs a dual characteristic echo sensing circuit to compensate for pulse distortion anomalies and a gain contour circuit to overcome spurious acoustic echo anomalies that are indigenious to threaded bolts and which would otherwise preclude the accurate measurement of bolt elongation.
Brief Description of the Drawings
The above-noted objects and advantages of the present invention as well as additional objects and advantages thereof will be more fully understood hereinafter as a result of the detailed description of a preferred embodiment of the invention taken in conjunction with the accompanying drawings in which:
FIG. 1 is an isometric view of the apparatus of the invention showing the front panel thereof and illustrating the manner in which the invention is used to measure the length of a bolt;
FIG. 2 is a plan view of the rear panel of the apparatus taken along lines 2--2 of FIG. 1;
FIG. 3 is a block diagram of the apparatus of the invention;
FIG. 4 is a block diagram of the receiver portion of the invention;
FIG. 5 is a partially schematic and partially block diagram of the digital portion of the invention;
FIG. 6 is a schematic diagram of those features of the digital portion of the invention shown in block form in FIG. 5;
FIG. 7, comprising FIGS. 7a and 7b, is a schematic diagram of the receiver portion of the invention; and
FIG. 8 is a timing diagram illustrating the respective timing of nine selected signals utilized in the invention.
Detailed Description of a Preferred Embodiment
The physical appearance of the apparatus of the present invention may be best understood by reference to FIGS. 1 and 2 which illustrate the overall assembly as well as the front and rear panels, respectively. As seen in FIG. 1, the portable electronic bolt elongation measurement apparatus 10 comprises a self-contained portable housing 11 which enables onsight field measurements of the elongation of bolts such as bolt 12 in the manner illustrated. A suitable transducer 14, which is well-known in the art of ultrasonic thickness measuring devices, is normally applied at about the center of the head of the bolt 12 typically using some couplant material such as oil to assure firm, continuous contact between the transducer and the bolt. In bolt length measurement applications it may be advantageous to utilize a transducer which comprises a magnetic material so that the operator may secure the transducer to the bolt by means of magnetic attraction and thus free both of his hands for operation of the apparatus. The transducer is connected to apparatus 10 by a suitable coaxial cable 16 whereby transmitted pulses may be transferred between the apparatus and the transducer for application to the bolt and echo pulses transmitted from bolt to apparatus for subsequent reception by the contained receiver as will be described herein in more detail.
Apparatus 10 includes a front panel 18 which, in the preferred embodiment of FIG. 1, includes a liquid crystal display 20, a probe connector 22, a power switch 24, an initial length thumbwheel switch array 26, a temperature thumbwheel switch array 28, and a length/stretch selection switch 30. Apparatus 10 also includes a rear panel 32 which is illustrated in FIG. 2. On rear panel 32 are mounted a temperature factor thumbwheel switch array 34, a correction factor thumbwheel switch array 36, and a material velocity thumbwheel switch array 38. Also shown are AC power connector 40 and line fuse 42. it is to be noted that the instrument of the present invention may be operated on either AC power provided through connector 40 through a suitable line cable, or by means of internal rechargeable batteries which provide various DC voltages that are required and that are noted in the diagrams of FIGS. 5, 6 and 7.
The preferred embodiment of the apparatus of the invention illustrated in FIGS. 1 and 2 utilizes an ultrasonic pulse frequency of 5 MHz. with a 9 MHz. bandwidth. The apparatus may be selected to operate in either English or metric units and provides a bolt length measurement range of between 1 inch and 99 inches or between 2.5 centimeters and 99 centimeters. It also measures bolt elongation (or stretch) anywhere within the range of 0 to 99 inches or 0 to 99 centimeters. The digital resolution is plus or minus 0.0001 inch or plus or minus 0.0003 meters. The instrument error is less than plus or minus twenty parts per million plus or minus one digit and utilizes a six digit liquid crystal display 20 as seen on the front panel 18 in FIG. 1.
All of the multi-digit thumbwheel switches provide a binary coded decimal (bcd) outputt as will be described hereinafter in more detail. The initial length switch array 26 is a six digit entry device with two digits to the left of the decimal point and four to the right. Temperature entry switch array 28 provides four entries including a (sign) bit and a two and one half digit switch entry for temperatures in the range of -199.degree. C. to +199.degree. C., to the nearest degree. The material velocity switch array 38 on the rear panel is a six digit thumbwheel switch array in which velocity may be entered in either inches per microsecond or centimeters per microsecond. By way of example, a typical material correction factor for rolled aluminum is 0.253000 inches per microsecond.
The temperature factor switch array 34 is a three digit entry thumbwheel switch which provides for entry of numbers in the range of 000. to 999. parts per million per degree centigrade, which may be used to enter the temperature factor of the bolt material to automatically compensate for the difference in temperature during the current measurement as represented by switch array 28 on the front panel, and a reference temperature of 25.degree. C. or other selected reference temperature encountered during a prior measurement.
The initial length thumbwheel switch arrary 26 is a six digit entry switch which provides for initial bolt length entry data in the range of 0 to 99.9999 inches or centimeters. The velocity correction factor thumbwheel switch array 36 is a three digit range input device which provides for a correction multiplier in the range of 0.000 to 0.999.
An overall block diagram of the apparatus of the present invention is illustrated in FIG. 3. Included are a transmitter 44 and a receiver 46 both connected to transducer 14 via cable 16 for transmitting ultrasonic pulses into bolt 12 from one end thereof and for receiving the echo pulses generated thereby. The system also comprises a binary counter 48, a high frequency oscillator 50, input-output ports 52, a microprocessor subsystem 54, a synchronization generator 56, and trigger logic 58. In addition, all of the previously identified thumbwheel switch arrays are connected to microprocessor subsystem 54 by means of inut-output ports 60 and display 20 is interconnected to the microprocessor subsystem 54 by means of input-output ports 62 and display driver 64.
The timing of the measurement process performed by the apparatus of FIG. 3 is controlled by a 2 MHz. clock signal generated by the microprocessor subsystem 54. The clock signal is applied to the synchronization generator 56 and trigger logic 58 to develop a trigger signal having a 2 millisecond period that is applied to transmitter 44 for generating an ultrasonic pulse 500 times a second. Shortly after the application of the transmission pulse into bolt 12, a counter gate signal is applied to binary counter 48 in response to which binary counter 48 begins counting the number of pulses produced by 100 MHz. oscillator 50. Binary counter 48 continues to count those pulses until a stop counting signal is generated by receiver 47 in response to reception of the first valid echo signal reflected from the far end of bolt 12 in response to the transmitted pulse. Accordingly, the final count generated by binary counter 48 in response to each transmitted pulse into bolt 12, represents the time it takes for the transmission pulse to travel the length of bolt 12, reflect off the end of the bolt and again travel the length of the bolt back to transducer 14. By converting that count into a time of travel and incorporating the known material velocity of the bolt, the length of the bolt is measured to an accuracy dependent upon the stability of oscillator 50 and resolution of counter 48. This process is repeated every 2 milliseconds. A large number of such counts (i.e. 160) are averaged over a fraction of a second and that average further improves the precision of the measurement. A unique binary filtering process described below assures a reliable averaging process that is free of erroneous counts. Each binary count produced by binary counter 48 in response to a transmitted pulse is transferred to input-output ports 52 and thereafter into appropriate portions of memory circuits of microprocessor subsystem 54 as will be hereinafter more fully understood.
As previously discussed, the precision of a bolt elongation measurement using ultrasonic techniques is highly dependent upon the inclusion of correction factors which account for changes in material velocity as a function of stress and changes in length as a function of temperature. The present invention is capable of incorporating such correction factors in the measurement process to provide increased accuracy and precision for the unique characteristics of bolts under stress. The means by which these factors are entered into the measurement process have been alluded to earlier, namely, the thumbwheel switch arrays located on the front panel 18 and rear panel 32 of apparatus 10 shown in FIGS. 1 and 2. In FIG. 3 the blocks on the right-side of the figure, consisting of initial length array 26, material velocity array 38, material factor array 36, temperature factor array 34, temperature array 28, and length/stretch selection switch 30, are all connected to a common data bus 55. Bus 55 transfers binary coded decimal representations of those switch positions to microprocessor subsystem 54 via input-output ports 60. An additional input-output port 62 provides suitable interface between microprocessor subsystem 54 and digital display 20 which is driven by display drivers 64. The various input-output ports 52, 60 and 62 are interconnected to the microprocessor subsystem 54 by means of a data bus 57 as seen in FIG. 3. It is to be noted that trigger logic 58 in addition to providing a trigger signal to transmitter 44 also provides an AGC gate signal and a control signal to receiver 46 for purposes that will be more fully understood hereinafter.
As previously indicated, the difficult problems associated with accurate and precise measurement of bolt elongation that have been solved by the present invention relate also to anomolous characteristics of the reflections of the ultrasonic pulses that are transmitted by transducer 14 into bolt 12. These problems relate to the distortion of the pulse wave shape which renders it more difficult to utilize a consistent characteristic of the reflected pulse to generate the stop counting signal shown previously in conjunction with FIG. 3. In addition, the peculiar acoustical characteristics of a threaded bolt typically results in the production of a plurality of echo signals from one transmitted pulse. One particular problem solved by the present invention and otherwise especially troublesome in measuring the time period elapsed between the transmitted pulse and the first received echo pulse, is the typically anomolous behavior of the secondary echo pulses in that their amplitudes often exceed the amplitude of the first generated valid echo pulse.
The receiver of the present invention utilizes a unique echo sense circuit to overcome the pulse distortion problems described above. It also utilizes a unique gain control circuit to overcome the effects of high amplitude anomolous secondary echo pulses as described above. FIG. 4 provides a simplified block diagram of the receiver portion of the invention. Receiver 46 comprises an RF amplifier 66, a phase switch 68, an echo sense circuit 70, an AGC circuit 72, an AGC buffer 73, a ramp generator 74, a gain dump circuit 76 and a junction 78 for summing the output signal of the AGC circuit, ramp generator and gain dump circuit. The combined signal is input as a gain control signal into RF amplifier 66.
As seen in FIG. 4, the signal from transducer 14 is applied to RF amplifier 66. Amplifier 66 consists of a dual stage amplifier circuit capable of providing up to 70 db gain. The amplified signal is passed into phase switch 68 which provides means for selecting either polarity of the signal generated at the output of RF amplifier 66 depending upon which signal phase provides the best wave form for accurate echo pulse detection by echo sensor circuit 70. The output signal of echo sensor circuit 70 is the stop counting signal which is transmitted to the binary counter as previously indicated in conjunction with FIG. 3. The output of phase switch 78 is also connected to the AGC circuit 72 for adjusting the gain bias level to an appropriate magnitude for the nominal amplitude of the reflected echo ultrasonic pulse. AGC circuit 72 performs this bias adjustment during the occurrence of an AGC gate signal transferred from the trigger logic 58 discussed previously in conjunction with FIG. 3 and the output signal of the AGC gate circuit 72 is applied to a buffer 73. The output of buffer 73 is connected to junction 78. The outputs of ramp generator 74 and gain dump circuit 76 are also connected to junction 78 to provide a gain control signal into RF amplifier 66, which signal is the sum of the outputs of AGC buffer 73, ramp generator 74, and gain dump circuit 76, respectively.
A more detailed description of the hardward portion of the present invention shall now be described in conjunction with FIGS. 5-7.
Referring to FIG. 5 there is shown the individual circuit elements of the binary counter 48, the microprocessor subsystem 54, the thumbwheel switch arrays in which array 36 is included as an illustrative example, the display 20, display drivers 64 and the interconnecting buses and input-output ports for interfacing with the microprocessor subsystem. A portion of FIG. 5 including oscillator 50, synchronous generator 56 and trigger logic circuit 58 is included in block form but further described in conjunction with the more detailed schematic diagram of FIG. 6.
As seen in FIG. 5, binary counter 48 comprises a pair of high speed flip-flops, 80 and 82, a pair of 4-bit binary counters 84 and 86, and a dual 4-bit binary counter 88. High speed flip-flops 80 and 82 may, be way of example, both be contained on a single 74F74 Schottky TTL chip containing a dual D-flip-flop which is capable of responding to clock frequencies as high as 145 MHz. Such chips are available from the Fairchild Camera and Instrument Corporation of Mountainview, Calif. and are described at pages 3-5 of that company's publication entitled "FAIRCHILD ADVANCED SCHOTTY TTL", copyright 1979. The 4-bit nbinary counters 84 and 86 may, be way of example, be model SN74LS293 4-bit binary counters manufactured by Texas Instruments Incorporated of Dallas, Texas and described at page 4-423 etcetera of that company's publication entitled "TTL DATA BOOK FOR DESIGN ENGINEERS, SECOND EDITION", copyright 1976. Dual 4-bit binary counter 88 may, by way of example, be a model CD 4520B COS/MOS dual binary up-counter manufactured by RCA Corporation and described in that company's publication entitled "RCA SOLID STATE COS/MOS INTEGRATED CIRCUITS", copyright 1978, beginning at page 292. The flip-flops 80 and 82 and counters 84, 86 and 88 are interconnected to provide a binary counter having an 18 bit capacity of which the most significant bit corresponds to a count of 128K.
The 18 output lines of binary counter 48 are supplied as input signals to input-output port 52 consisting of individual ports 52a, 52b, and 52c as shown in FIG. 5. In the preferred embodiment of the apparatus, each such input-output port comprises a model CDP1852 8-bit input/output port manufactured by RCA Corporation and described beginning at page 112 of their publication entitled "RCA SOLID STATE COS/MOS MEMORIES, MICROPROCESSORS, AND SUPPORT SYSTEMS", copyright 1979. All such input/output ports including input/output ports 60a and 60b that are used to interface the thumbwheel switches to the microprocessors sub-system 54 and input/output port 62 that is used to interface the display and display drivers to the microprocessor sub-system, are identical chips selected primarily because of their capability with the microprocessor sub-system as will be described hereinafter in more detail. Binary counter 48 counts at a constant rate in response to 100 MHz. oscillator 50, which is a highly stable and accurate quartz controlled oscillator. However, counter 48 begins and ends the counting process in response to counter control signals generated by trigger logic 58 in response to sync generator 56, the timing of which is controlled by microprocessor 94 as will be described in further detail below and also in response to the stop counting signal received from receiver 46 as will also be described further below. Thus, the period during which binary counter 48 is permitted to count the output derived from 100 MHz. oscillator 50 is dependent upon the time interval between the occurrence of the transmitted ultrasonic pulse which enters the head of bolt 12 and the reception of the first valid echo pulse traveling back along bolt 12 to the receiver 46 (see FIG. 3).
It will be observed that input/output ports 52 provide a count input to the microprocessor based sub-system 54 that corresponds to the nominal traversal time of an ultrasonic pulse transmitted into and received back along bolt 12. The other principal input to microprocessor sub-system 54 for the purpose of calculating an accurate measurement of bolt length or bolt elongation, is provided by the aforementioned plurality of thumbwheel switch arrays. The three thumbwheel switches comprising correction factor thumbwheel switch array 36 are shown in FIG. 5 as an illustration of the manner in which all such thrumbwheel switches are interconnected to microprocessor sub-system 54.
There are a total of 22 such thumbwheel switches comprising the various arrays discussed previously. Each such switch is a digital thumbwheel switch having a binary coded decimal (BCD) output. Each output terminal of the thumbwheel switch is tied into the corresponding output of other thumbwheel switches in either one of two 4-wire buses that are applied to the eight input terminals of input/output port 60b. In addition, each thumbwheel switch includes a common connection C which is connected to an output of a strobe buffer 90 or 92, the input terminals of which are connected to input/output port 60a. Thus, input/output port 60a, in response to signals on the data bus of microprocessor sub-system 54, selects any two of the plurality of thumbwheel switches by grounding the corresponding common lines through pull-up resistors (not shown) whereby the output signals on the corresponding BCD terminals of those selected thumbwheel switches are applied to the input terminals of input/output port 60b for transfer to the microprocessor sub-system 54. In this manner microprocessor sub-system 54 selects and receives at appropriate times during the oeration of the apparatus, any of the correction factors and other information previously inserted into the respective thumbwheel switch arrays described previously. Strobe buffers 90 and 92 may be, by way of example, RCA CD4502B COS/MOS strobed hex inverter/buffers which are discussed beginning at page 268 of the aformentioned RCA publication on COS/MOS integrated circuits.
Thus it will be seen that the input/output ports 52a, 52b, 52c and 60b, in combination, provide all the requisite input signals to microprocessor sub-system 54 for measuring a corrected time interval of ultrasonic pulse travel through bolt 12 including correction factors entered into a plurality of thumbwheel switches to permit compensation for temperature and stressed-induced errors that would otherwise detrimentally affect the accuracy of the measurement process.
The remainder of FIG. 5 includes microprocessor sub-system 54 and the display portion of the apparatus, tthe later of which includes input/output port 62, display drivers 64, and LCD display 20. Input/output port 62 is also an RCA model CDP1852 8-input/output port, the input terminals of which are connected to the data bus to which all other input/output ports are connected. The output terminals of input/output port 62 are connected to the pair of 4-digit decoded display drivers. Drivers 64 may, by way of example, be Intersil model ICM7211 devices which drive display 20 which is a liquid crystal model 60D9R05JH manufactured by General Electric Corporation.
Microprocessor sub-system 54 comprises microprocessor 94, random access memory (RAM) 96, eraseable, programmable read-only memory (EPROM) 98, latch and decoder 100, flip-flop 102, and decoder 104.
Microprocessor 94 may, by way of example, be an RCA model CDP1802 microprocessor which is described in detail beginning at page 17 of the aforementioned RCA publication of COS/MOS MEMORIES, MICROPROCESSORS, AND SUPPORT SYSTEMS. The random access memory (RAM) may, by way of example, be an RCA model CDP1824 32-word by 8-bit static random access memory described beginning at page 69 of said publication. Eprom 98 may, by, way of example, be a Texas Instruments model TMS2516JL 16-K eraseable, programmable, read-only memory having a 20 48 X8 organization as described at page 200 of the Texas Instruments publication entitled "THE MOS MEMORY DATA BOOK FOR DESIGN ENGINEERS", copyright 1977. Latch and decoder 100 may, by way of example, be an RCA model CDP1859 type COS/MOS 4-bit latch with decode as described beginning at page 156 of the aforementioned RCA publication. Extra address bit flip-flop 102 may, by way of example, be an RCA model CD4013A dual D-type flip-flop, and one of eight decoder 104 may, by way of example, be an RCA model CDP1853 N-bit one of eight decoder as described beginning at page 119 of the aforementioned RCA publication.
Microprocessor 94 is an eight-bit bi-directional data bus, eight-bit memory address architecture microprocessor. However, because Eprom 98 utilizes a 2K memory structure requiring eleven address bits on address bus 59, three additional address bits are generated, two by latch and decoder 100 and one by extra address bit flip-flop 102 as seen in the right portion of FIG. 5. Data bus 57, in addition to comprising eight data lines that interconnect the microprocessor with RAM 96 and Eprom 98 and all interconnecting input/output ports, also includes a read level signal which is used to indicate the direction of data transfer during input/output instructions. An additional bus 61 interconnects microprocessor 94 and one of eight decoder 104 and includes three input/output command signals as well as a timing pulse signal, all of which are used to select the appropriate input/output port at the appropriate time during the measurement process as will be more fully hereinafter understood as a result of the description of the software portion of the invention. Cycle timing for microprocessor sub-system 54, as well as for the remainder of the logic circuits of the invention, is derived from 2 MHz. crystal 106 and 10 MegOhm resistor 108 which are connected in parallel to the clock terminal of microprocessor 94 for generating a 2 MHz. clock signal. This 2 MHz. signal is transferred to synchronization generator 56 for controlling the counting cycle as will now be described in conjunction with FIG. 6.
In FIG. 6 it will be seen that 100 MHz. oscillator 50 is applied to an emitter follower output circuit 110 which utilizes a 2N3251 transistor. The emitter output is applied to a NOR gate 128, the output of which is applied to the clock terminal of the first high speed flip-flop 80 of binary counter 48. The second input to NOR gate 128 is derived from the output of NAND gate 126. Those familiar with the art to which the present invention pertains will understand that only when the output signal logic state of NAND gate 126 is in a zero or false state can the variation in logic states of the output of circuit 110 be transferred as a series of 100 MHz. frequency pulses to the clock terminal of high speed flip-flop 80 of the counter. Conversely, when the output signal at the output terminal of NAND gate 126 is in a high or true state, the output of OR gate 128 will remain fixed irrespective of the changes of the signal derived from 100 MHz. oscillator 50. Accordingly, NAND gate 126 and NOR gate 128 provide a gating means to control the application of high frequency pulses to the binary counter. Thus, only when both input terminals to NAND gate 126 have signals in a one or true state can counter 48 be activated. One of those two terminals is connected to the Q output of D-type flip-flop 124 and the other terminal of NAND gate 126 is connected to the Q output of monostable multivibrator or one shot 116. One shot 116 provides an adjustable delay of nominally 200 nanoseconds in initiation of counting in binary counter 48 to compensate for ultrasonic pulse delays in the circuit transducer and transducer cable so that the counter starts counting precisely when the transmitted ultrasonic pulse starts its travel into the head of bolt 12. An additional timing delay is provided by one shot 118 for the purpose of inhibiting receiver 46 so that the receiver remains insensitive to the ringing produced by the generation of the transmitted ultrasonic pulse into bolt 12. This delay is also adjustable and is typically in the range of 4 to 8 microseconds.
Logic timing for the circuits of FIG. 6 is controlled by synchronization generator 56 which comprises a frequency divider chip 112 and a plurality of logic inverters 114 which are used to provide the appropriate signals for the remaining logic circuits of trigger logic 58. Frequency divider 112 may be, by way of example, an RCA model CD4020B COS/MOS 14-stage ripple-carry binary counter/divider which is described beginning at page 107 of the aforementioned RCA publication. Frequency divider 112 receives input pulses at a 2 MHz. frequency from the timing output of microprocessor 94 as discussed previously in conjunction with FIG. 5. Only the 11th and 12th output stages of frequency divider 112 are used in the present invention, the 11th stage providing a 1 kiloHertz frequency output signal derived from the 2 MHz. input signal from microprocessor 94. The 1 kiloHertz and 500 Hertz signals are applied to all of the reset terminals of the counting elements of binary counter 48 via NAND gate 120 to reset the counters every 2 milliseconds. The 500 Hertz output signal of frequency divider 112 is applied to the A input terminals of one shots 116 and 118, both of which reside on a single Texas Instruments model 74LS221 chip entitled DUAL MONOSTABLE MULTI-VIBRATORS WITH SCHMITT-TRIGGER INPUTS described beginning at page 6-68 of the Texas Instruments publication entitled "THE TTL DATA HANDBOOK FOR DESIGN ENGINEERS", copyright 1976. Thus it will be seen that the counting process is repeated every two milliseconds and that the counting process can take place only during the first 1 millisecond of that period at which time the counters remain stable for 500 microseconds to allow data transfer to the microprocessor. The reset pulse is then applied for the last 500 microseconds of the time interval.
Each 2 millisecond cycle is initiated upon the generation of a pulse at the Q-12 terminal of frequency divider 112. At this point in time, the reset signal to the binary counter components is removed, the transmitter is triggered via gate 132, M changes to zero, flip-flop 124 is set and both Q output terminals of one shots 116 and 118, respectively, are changed to a zero logic state. Accordingly, one of the input signals to NAND gate 126 is in a zero logic state which as previously indicated, inhibits the initiation of counting in binary counter 48. After a predetermined period of time, nominally 200 nanoseconds, one shot 116 reaches its preset monostable duration permitting the Q output to change logic states to a true or high level. At this point in time, both of the input terminals to NAND gate 126 are in a true or high state and counter 48 is no longer inhibited because the other terminal receives a one or true state signal from the set Q terminal of flip-flop 124. After an additional period of predetermined delay generally within the range of 4 to 8 microseconds as previously described, one shot 118 also reaches its multivibrator duration at which point Q of one shot 118 changes logic states to a high level also changing the state of the AGC gate signal applied to receiver 46. The effects of the logic states of the AGC gate and M signals on the receiver, are discussed below in conjunction with FIG. 7.
Thus, when the two millisecond pulse starting the measurement cycle is applied to the input of one shot 118, a negative pulse is applied to the set terminal of flip-flop 124 setting that flip-flop. In addition, a trigger signal is applied through NAND gate 132 to the transmitter to initiate pulse transmission into bolt 12. As soon as the one shot 116 delay expires, both input terminals to NAND gate 126 have ones or true signals applied thereto thus enabling NOR gate 128 to pass the 100 MHz. frequency signal to the clock terminal of high speed flip-flop 80 to commence counting by binary counter 48. The Q output of flip-flop 124 is applied to the receiver, which will be discussed hereinafter in more detail in conjunction with FIG. 7, to enable normal receiver operation subsequent to the transmission of a trigger pulse. The output Q of one shot 118 is also applied to the receiver as an AGC gate signal delayed by the preselected time delay of one shot 118 wich as previously indicated, is typically within the range of 4 to 8 microseconds. One shot 118 delays the response of the receiver until after all the ringing caused by the transmitted pulse is likely to have dissipated.
Binary counter 48 is enabled to accept the 100 MHz. frequency output of oscillator 50 via NOR gate 128 until one of the two input signals to NAND gate 126 returns to a zero state. This occurs when a stop counting signal is received from the receiver, inverted through NOR gate 122, and applied to the clock terminal of flip-flop 124. Because the D terminal of flip-flop 124 is grounded, the application of a clock signal to flip-flop 124 forces the Q output of that flip-flop to go to a zero state. The output of NAND gate 126 is forced into a one state, thus preventing the clock input to high speed flip-flop 80 from changing during the remainder of that cycle. Therefore, the output of counter 48 remains fixed and the count represents the total time elapsed between the trigger pulse delayed by the period of one shot 116 and the subsequent stop counting signal which is generated by the receiver in response to a valid echo pulse as will now be described in conjunction with FIGS. 7a and 7b.
The receiver of the present invention as illustrated in schematic form in FIG. 7, comprising FIGS. 7a and 7b, is divided into dotted line blocks which represent the equivalent blocks of FIG. 4 discussed previously. More specifically, in FIG. 7a there is shown RF amplifier 66, phase switch 68, AGC buffer 73, ramp generator 74, gain dump circuit 76, and gain control junction 78. FIG. 7b includes the schematic representation of echo sense circuit 70 and AGC circuit 72.
RF amplifier 66 is in the embodiment illustrated herein a two stage, 5 MHz., 70 dB amplifier. The amplifier has two stages including a first stage wide band amplifier with AGC, such as a Motorola model MC1590RF/IF amplifier; and a second stage comprising a wideband amplifier such as an RCA model CA3040 wideband amplifier chip. The first stage provides up to 60 dB of AGC range which is controlled by the signal input from junction 78. The signal at junction 78 is a combination of the signals applied from AGC circuit 72 and AGC buffer 73, ramp generator 74, and gain dump circuit 76. RF amplifier 66 has a nominal center frequency of 5 MHz. and a 10 MHz. bandwidth with the output thereof provided at the second stage of the amplifier in a selectable phasing arrangement determined in accordance with the position of phase switch 68 as shown in the right-most portion of FIG. 7a. The signal input to the first stage of RF amplifier 66 is derived from transducer 14 which is connected to the input of the first stage of the amplifier by a suitable matching network which also includes diode protection to isolate the receiver from the high voltage pulse transmitter (not shown).
At the beginning of a measurement cycle, trigger logic circuit 58 transmits an M signal to gain dump circuit 76 and after the receiver delay of one shot 118 is complete it transmits an AGC gate signal to AGC circuit 72. While binary counter 48 is counting as a result of the setting of flip-flop 124 in FIG. 6, the M signal applied to gain dump circuit 76 is in a zero state, thus applying a zero voltage to the base of transistor 150 keeping that transistor in an off state. As a result, transistor 154 in a ramp generator circuit 74 has its emitter connected to a -6 volt supply voltage through a 10K resistor in AGC buffer 73 and capacitor 156 is free to discharge toward that negative voltage. The result is a substantially linear negative going ramp that increases the gain of the first stage of the RF amplifier 66 as long as transistors 158 and 160 in the ramp generator circuit 174 remain in an off state. Those two transistors remain in an off state as long as the AGC gate signal derived from trigger logic 58 remains in a zero state and the M signal is zero prior to receiving a return echo from the bolt.
When transistor 150 in square wave generator 76 is off transistor 152 is also biased off and the voltage derived at potentiometer 162 is in the collector circuit of transistor 152 is at a ground level which corresponds to maximum gain for the first stage of RH amplifier 66.
The AGC gate signal turns on transistor 164 in AGC gate circuit 72 of FIG. 7b, thereby enabling the differential amplifier formed by transistors 166 and 168. The output of the differential amplifier is at the collector of transistor 166 and represents the difference in voltage between the video signal applied to the base of transistor 168 and a variable voltage reference signal applied to the base of transistor 166. The output of the differential amplifier is applied to a driver transistor 170, the output of which is connected to the positive input terminal of operational amplifier 172 shown in FIG. 7a. The output of operational amplifier 172 is applied to junction 78 along with the ramp signal derived from ramp generator circuit 74 and the stepped signal derived from square wave circuit 76. A gain limit adjustment potentiometer 175 is provided at the positive input to amplifier 172 to limit the AGC excursion as desired.
When the stop counting signal is generated by echo sense circuit 70 in response to a received valid echo pulse, the M signal from trigger logic circuit 58 is changed to a positive voltage turning on transistor 150 and transistor 152. As a result, the voltage at potentiometer 162 suddenly increases through transistor 152 whereby the gain is stepped down to preclude the reception of subsequent echo pulses. In addition, transistor 154 is turned off thereby isolating ramp generator circuit 74 from the -6 volts supply, terminating the ramp at the voltage reached at the occurence of M. It is to be noted that the output of transistor 170 in the AGC gate circuit 72 of FIG. 7b is also connected to an RC circuit comprising capacitor 174 and 1 MegOhm resistor 176 which is in turn connected to the -6 volts supply voltage. This RC circuit acts as a fast attack, slow decay network for the AGC circuit wherein capacitor 174 is rapidly charged during the application of the video signal to the base of transistor 168 and slowly discharged in the absence of a signal.
Echo sense circuit 70, shown in the upper portion of FIG. 7b, is connected to the output of phase switch 68 discussed previously in conjunction with FIG. 7a and comprises primarily an operational amplifier comparator 180 such as a Fairchild model 760. With no received signal present at the input terminal 2 of comparator 180, the output of the comparator at pin 6 is in a low state at ground level and the feedback output at pin 7 is in a high state of approximately 3 volts. Consequently, variable resistor 181 provides a small adjustable positive voltage reference to pin 3 of the comparator. This reference voltage is adjustable to provide variations in threshold to which comparator 180 responds for optimizing the probability of responding only to the first valid echo signal received. When the amplified signal applied to terminal 2 of comparator 180 exceeds the threshold signal applied to terminal 3, the signal at output terminal 6 suddenly goes to a positive level and the feedback signal from terminal 7 goes to a zero level. As a result, the comparator reference feedback voltage then goes to zero so that the output at terminal 6 will immediately revert back to zero volts upon the occurence of the first zero crossing after the threshold is exceeded.
Thus, during each transmitted pulse cycle, the first received reflected pulse that includes a voltage swing above a pre-established threshold produces a positive pulse at the next zero crossing, which pulse is the stop counting signal. That signal is applied to the trigger logic of FIG. 6 where the signal is inverted by NOR gate 122 before being applied to the clock terminal of flip-flop 124. It is the positive going edge of the inverted pulse at the clock terminal of flip-flop 124 which corresponds in timing to the zero crossing of the received signal after it first exceeds the threshold that clocks the flip-flop. Thereafter, the 100 MHz. oscillator pulses are prevented from reaching the binary counter for the remainder of that cycle as discussed previously.
Reference will now be made to FIG. 8 which comprises nine signal waveforms of various signals previously discussed in conjunction with FIGS. 6 and 7, to enhance the understanding of the present invention. Waveform a is the 2 millisecond period squarewave generated at the Q12 terminal of frequency divider 112 of FIG. 6. This 2 millisecond period is the basic measurement cycle of the apparatus. Waveform b is the one millisecond period squarewave available at terminal Q11 of frequency divider 112 of FIG. 6 and is used primarily to provide resetting functions 75% through the measurement cycle, that is, 1.5 millisecond after the occurence of the transmitted pulse. Waveform c is the C-gate signal generated at the Q terminal of receiver delay one shot 118 of FIG. 6 and that is used primarily to control the initiation of the AGC gate signal to the receiver to prevent the ringing effects of the transmitted pulse from interfering with the measurement process. As previously indicated, C-gate signal pulse diration is typically in the range of 4-8 microseconds but is adjustable to provide an optimum value for the measurement taking place. Waveform d is the AGC gate signal applied to the AGC gate circuit 72 (as shown in FIG. 7b) by the trigger logic 58 (shown in FIG. 6) to enable the gain circuits of receiver 46. The AGC gate signal, which permits normal receiver operation when it is in a low state, does not begin to make the transition to that low state until the termination of the C-gate signal of waveform c. It is then reset upon the termination of the 1 millisecond reset cycle established by the 1 kiloHertz signal of waveform b.
Waveform e of FIG. 8 is the zero delay signal produced at the Q terminal of counter delay one shot 116 of FIG. 6. As previously indicated, the timed output of one shot 116 is also adjustable but is typically 200 nanoseconds in duration and is used to compensate for the time delay between the pulse trigger provided by trigger logic 58 and the entry of the transmitted pulse into the bolt 12. The effect of the zero adjust time delay of waveform e is seen in waveform f which is an inverted representation of the output of NAND gate 126 of FIG. 6. Therefore, waveform f represents the time period over which the binary counter 48 is allowed to count the output of 100 MHz. oscillator 50. In the particular example illustrated in the waveforms of FIG. 8, the counter would begin counting immediately upon the termination of the zero adjust pulse of waveform e and continue counting until the received echo pulse first accomplishes a zero crossing subsequent to exceeding the selected threshold as indicated by the video representation of the transducer pulses in waveform g.
In waveform g of FIG. 8 the first signal indication beginning at the initiation of the measurement cycle is the transmitted pulse t.sub.p and the second signal representation is the received echo pulse r.sub.p. The additional signal representations following r.sub.p represent further received echo signals which are ignored by the receiver of the present invention. Waveform h represents the gain characteristic of receiver 46. Just prior to the transmission of transmitter pulse t.sub.p, the gain of receiver 46 is substantially fixed at a value determined by the previous signal history of the AGC circuit as is well-known in the art. However, immediately upon the transmission of pulse t.sub.p into bolt 12, the gain ramp is activated and the gain increases linearly to either a maximum value, if no signal is received, or until the received signal meets the threshold and zero crossing criteria for the echo sense circuit 70 of receiver 46. When this event occurs, the gain dump circuit is activated and the gain of the receiver makes a substantially instantaneous negative change which prevents the receiver from receiving subsequent invalid echo signals which may also exceed the threshold value. The entire gain circuit is then reset at the 1 millisecond reset time as previously indicated.
The last waveform of FIG. 8, that is waveform i, represents the count termination signal applied to the clock terminal of flip-flop 124 of FIG. 6. This is the stop counting signal from the receiver inverted by NOR gate 122 of FIG. 6. Flip-flop 124 of FIG. 6 responds to the first positive going edge of the count termination signal of waveform i resulting from the output of echo sense circuit 70 of FIG. 7b. In the example of the count termination signal of waveform i as shown in FIG. 8, two sequential pulses are shown to indicate the effects of the second traversal of the waveform of received pulse r.sub.p beyond the threshold level and then to zero. However, only the first positive going transition of the count termination signal of waveform i effects a change in the output state of flip-flop 124 of FIG. 6. Therefore, the second such sequential pulse waveform i is ignored by the present invention.
The program stored in EPROM 98 for carrying out the operation of the present invention is disclosed in total in Table I attached hereto as an appendix. Table I includes three columns, namely, an address column, an opcode column and a remarks column. The address column lists a three digit hexadecimal representation of each of the 8 bit address locations in EPROM 98. The opcode column lists a two digit hexadecimal representation of the 8 bits of binary code stored at each such location and the remarks column briefly indicates the nature of the operation being carried out in the program in response to a particular opcode or sequential plurality of opcodes. Those having skill in the art to which the present invention pertains will find the bolt gauge program listed in Table I to be a complete and precise description of each step carried out by the program of the present invention. Accordingly, for purposes of clarity and brevity, only the major computational operations carried out by the program shall now be described in general terms.
More specifically, the output of counters 84, 86 and 88 available at input/output ports 52a, 52b and 52c, respectively, are input to an accumulator in microprocessor 94. This process is repeated 160 times sequentially as long as any one pulse count does not differ from the prior pulse count by more than a count of 8. The program thus acts with the counters to provide a form of digital filtering which prevents inaccuracies due to anomalies in the count that would be represented by a sudden change in the count by a predetermined number. In the preferred embodiment this number is 8 but of course it will be understood that the program is readily changed to utilize any desired count change criteria.
If the count change limit is exceeded, the process of loading the accumulator is restarted. On the other hand, if the count change limit is not exceeded, the process of loading the accumulator with 160 successive counts is completed and the program next divides the accumulator output by 4 and adds the quotient to the original contents of the accumulator. This is the equivalent of multiplying the accumulator contents by a factor of 1.25. This factor is used to compensate for the selected frequency of oscillator 50 which would ideally be an oscillator having a frequency of 125 MHz. However, in the preferred embodiment of the invention in order to be assured of proper component performance despite frequency limitations thereof, the lower frequency of 100 MHz. is used and compensation therefore is accomplished in the computer portion of the invention as just described. Of course it will be clear that the program is readily changed to multiply the contents of the accumulator in this step by any factor dependent upon the selected frequency of oscillator 50.
The program next divides the contents of the accumulator by a factor of 4 which converts the accumulator contents to the appropriate units level for measurement time that may be used in the remainder of the computation. Next the computer inputs the material velocity factor set in thumbwheel switch 38 shown in FIG. 2. Because the thumbwheel switches provide a binary coded decimal output, the computer then converts material velocity in BCD to a binary format. Next the binary representation of material velocity is multiplied by the contents of the accumulator and that produce represents the uncompensated reading of the length of the bolt under test. The computer next inputs the temperature reading input into thumbwheel switch 28 and converts that representation to binary format. It then subtracts 25 degrees from the input temperature to provide a difference temperature including a sign bit indicating whether the input temperature is above or below the reference temperature of 25 degrees C. Next the temperature factor thumbwheel switch 34 is input to the computer and converted to binary format. Then the temperature factor is multiplied by the temperature difference and the results are either added or subtracted from 1 depending upon the polarity of the temperature sign bit. Next the result of the addition or subtraction from 1 in the previous step is multiplied by the uncompensated reading of the bolt length. The result is a compensated reading of bolt length which is more accurate because it takes the effects of temperature into account.
If stretch/length switch 30 has been set to the length position, indicating that the current measurement is of an unstretched bolt, the compensated reading obtained in the previous step is converted to a binary coded decimal representation and applied to the display 20 to provide the user with an indication of the unstressed bolt length compensated for temperature. On the other hand, if the stretch/length switch 30 is set to the stretch position, indicating that the bolt being measured is under stress, the computer program continues with the following steps:
The material factor set into thumbwheel switch 36 is input and converted to binary. Then the initial length is set into thumbwheel switch 26 and corresponding to a prior unstressed bolt length measurement is also input and converted to binary. The program then subtracts the initial length from the compensated reading and multiplies that difference by the material factor. The results are then converted to binary coded decimal format and applied to display 20 to provide an indication of the change in length of the bolt subjected to stress as compared to its initial length and compensated for both temperature and the effects of the stress on the velocity of the acoustic energy through the bolt. A shorthand representation of the program operation as just described is indicated below in equations 1 and 2, the former corresponding to the compensated reading of an unstressed bolt and the latter corresponding to the stretch reading of a stressed bolt.
It will now be understood that what has been disclosed herein is an apparatus and process for measuring the length of unstressed and stressed bolts to extreme accuracies and including means for inclusion of correction factors depending the stress conditon of the bolt, the temperature in which the measurement is made and the thermal correction coefficient of the material under test. The invention thus provides a length or length difference measurement which is based upon an accurate representation of the actual velocity of acoustical energy in the stressed bolt being tested. The apparatus utilizes a microprocessor-based digital system including a binary counter which is connected to an extremely high frequency oscillator. The counter is adapted to provide a high resolution count depending upon the time interval between a first pulse entering the outer surface of the bolt under test at the probe input end, and a second pulse which is derived from the reflection return of the ultrasonic energy from the opposite end of the bolt. A number of thumbwheel switches are provided which permit input of variables corresponding to material velocity, stress correction factor, measurement temperature and thermal correction coefficient. In addition, a switch is provided for selecting digital display of either full bolt length or the difference between full elongation and initial length. The latter may be entered via an additional thumbwheel switch after it has been measured by means of the invention or after it has been copied from tabulated data. The invention utilizes a unique digital filtering algorithm to ensure accurate and stable measurements. Also utilized is a novel receiver circuit which is designed to overcome the unique acoustical characteristics of threaded bolts by means of a dual characteristic echo sensing circuit used to ensure measurement accuracy despite acoustic pulse distortion. The receiver also includes a special gain contour circuit to further ensure measurement accuracy despite spurious echoes that commonly arise in the acoustic measurement in threaded bolts.
Those having skill in the art to which the present invention pertains will understand that the present invention provides a unique method and apparaus for measuring the elongation of stress bolts in situ including means for entering data representative of nominal length, nominal acoustic velocity, acoustic velocity stress correction factor, temperature of the measurement and thermal expansion coefficient to provide a highly accurate digital representation of bolt elongation. Although a preferred embodiment of the apparatus of the invention has been disclosed herein, it will now be apparent that numerous modifications may be made to the invention without deviating from the scope of protection. For example, although the preferred embodiment provides a microprocessor-based portable electronic instrument for measuring the elongation of stressed bolts, it will be understood that it is possible to carry out such measurements and computations utilizing other digital devices as well as analog circuits. Furthermore, it will be understood that although a preferred receiver circuit has been disclosed, which circuit reduces the difficulty of carrying out the measurement process by decreasing the effects of certain acoustical anomalies commonly encountered in measuring the length of threaded bolts by acoustic measurement means, the process of the present invention may be readily carried out by using more common receivers as well as receivers which employ other types of circuits for decreasing the effects of such anomalies. Thus, it will be understood that all such modifications and additions are currently contemplated as being within the scope of the present invention which is to be limited only by the claims appended hereto.