US 4,409,672 AGrant
Dynamic Semiconductor Memory Device
Issue Date:1983-10-11
•8 Claims
•13 Drawing Sheets
Abstract
A dynamic semiconductor memory device incorporating memory cells of a one-transistor and one-capacitor type is provided with increased charge storage and thus improved read operation. In this device, each of the memory cells is connected to one word line, to one bit line and to one power supply line. The potential of the power supply line is toggled low then high so as to store more charges in the capacitor of a memory cell.
Metadata
Assignee
- Fujitsu Limited
Inventor
- Yoshihiro Takemae
Application Information
Application Number:US 2497026
Filing Date:1981-03-31
Priority Date:1980-03-31
Art Unit:235
Classifications
IPC:
G11C 1140G11C 1124
Field of Search:
365149;189;203
Patent Drawings (13 sheets)
Description
Background of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an MIS (Metal-Insulator-Semiconductor) dynamic memory device of a one-transistor and one-capacitor type.
In general, an MOS (broadly, MIS) dynamic memory device of a one-transistor and one-capacitor type incorporates memory cells, each comprising a transistor and a capacitor. In this case, the transistor serves as a switching gate for charging or discharging the capacitor. In addition, the presence of charges in the capacitor corresponds to the data "0" or "1". For example, the state in which the capacitor is discharged corresponds to the data "0", while the state in which the capacitor is charged corresponds to the data "1".
The above-mentioned transistor has a gate connected to a word line, a drain connected to a bit line and a source. The source is connected to one electrode of a capacitor. This capacitor has another electrode connected to a power supply, which is usually the ground or another power supply V.sub.cc. In the stand-by state, the bit line is precharged by the power supply V.sub.cc.
Therefore, if the data "0" is stored in the memory cell, a charge Q.sub.1 stored in the capacitor thereof is
Contrary to the above, if the data "1" is stored in the memory cell, a charge Q.sub.2 stored in the capacitor thereof is
where C is the capacitance of the capacitor;
V.sub.cc is also a voltage of the power supply V.sub.cc ; and
V.sub.th is a threshold voltage of the transistor. Therefore, the difference .DELTA.Q between the charges Q.sub.1 and Q.sub.2 is
However, in the above-mentioned memory cell in which the other electrode of the capacitor is connected to the power supply V.sub.cc or the ground, in other words, the potential of the other electrode is definite, the difference .DELTA.Q is relatively small. This leads to an unstable read operation, since the operation of a sense amplifier for amplifying the difference in potential between the bit lines is dependent upon the difference .DELTA.Q.
Summary of the Invention
It is a principal object of the present invention to provide a semiconductor memory device with a stable read operation.
According to the present invention, there is provided a semiconductor memory device comprising: first and second power supplies, the potential of the second power supply being lower than that of the first power supply; a plurality of word lines; a plurality of power supply lines; a plurality of pairs of bit lines; a plurality of sense amplifiers, arranged between a respective pair of the pairs of bit lines; and a plurality of memory cells, each comprising a transistor and a capacitor. The transistor has a gate connected to one of the word lines and a drain connected to one of the bit lines; the capacitor has an electrode connected to a source of the transistor and another electrode connected to one of the power supply lines. The semiconductor memory device further comprises a plurality of means, connected to one of the power supply lines, for supplying a clock signal thereto after the rising of the potential of one of the word lines, wherein the potential of the clock signal falls and after that, rises. In the present invention, the difference between the charges Q.sub.1 and Q.sub.2 corresponding to the data "0" and "1" is increased due to the bootstrap effect, without changing the structure of the memory cells.
Brief Description of the Drawings
The present invention will be more clearly understood from the following description contrasting the present invention with the conventional device and with reference to the accompanying drawings, wherein:
FIG. 1A is a cross-sectional view illustrating a memory cell of a one-transistor and one-capacitor type;
FIG. 1B is an equivalent circuit diagram of the memory cell of FIG. 1A;
FIGS. 2A and 2B are a block diagram of a conventional semiconductor memory device;
FIG. 3 is a circuit diagram of a part of the device of FIG. 2;
FIGS. 4A, 4B and 4C are timing diagrams of the signals appearing in the circuit of FIG. 3;
FIGS. 5, 5A and 5B are block diagram of an embodiment of the semiconductor memory device according to the present invention;
FIG. 6 is a circuit diagram of a part of the device of FIG. 5;
FIGS. 7A, 7B and 7C are timing diagrams of the signals appearing in the circuit of FIG. 6;
FIGS. 8, 8A and 8B are a block diagram illustrating another embodiment of the semiconductor memory device according to the present invention;
FIG. 9 is a circuit diagram of a part of the device of FIG. 8; and
FIGS. 10A, 10B and 10C are timing diagrams of the signals appearing in the circuit of FIG. 9.
Description of the Preferred Embodiments
Referring to FIG. 1A, which illustrates a one-transistor and one-capacitor type memory cell, the memory cell is manufactured by using a so-called double-layer polycrystalline silicon technology. In FIG. 1A, 1 is a semiconductor substrate which is, for example, p.sup.- -type monocrystalline silicon; 2 is a field layer which is relatively thick and made of, for example, silicon dioxide; 3 and 5 are insulating layers which are relatively thin and made of, for example, silicon dioxide; 4 and 6 first and second conductive layers, respectively, and made of, for example, polycrystalline silicon; and 7 is an n.sup.+ -type impurity doped region. In this case, an MOS transistor Q.sub.m comprises a source formed by an inversion layer within the substrate 1 under the insulating layer 3, a drain formed by the impurity doped region 7 and a gate formed by the second conductive layer 6, while a capacitor C.sub.m comprises one electrode formed by the substrate and the other electrode formed by the first conductive layer 4 with the insulating layer 3 therebetween. Of course, various kinds of memory cells of a one-transistor and one-capacitor type have been developed; however, the memory cell as illustrated in FIG. 1A is a representative one which has an advantage in that the integrated density thereof is high.
FIG. 1B is an equivalent circuit diagram of the memory cell of FIG. 1A. In FIG. 1B, in the transistor Q.sub.m, a drain D and a gate G are connected to a bit line BL.sub.j and a word line WL.sub.i, respectively, and in addition, a source S is connected to an electrode P.sub.1 of the capacitor C.sub.m which, in turn, has a electrode P.sub.2 connected to a power supply line PL. In general, the power supply line PL is grounded.
The transistor Q.sub.m is used for charging or discharging the capacitor C.sub.m. For example, when the potential of the word line WL.sub.i is high (in this case, the transistor Q.sub.m is of an n-channel type), the bit line BL.sub.j is electrically connected to the electrode P.sub.1 of the capacitor C.sub.m so that a charge is transferred from the bit line BL.sub.j to the electrode P.sub.1 or vice versa in response to the potential of the bit line BL.sub.j. In this case, the absence or presence of a charge in the electrode P.sub.1 of the capacitor C.sub.m corresponds to the data "0" or "1" respectively.
FIG. 2 is a block diagram illustrating a conventional semiconductor memory device incorporating a plurality of the above-mentioned memory cells of a one-transistor and one-capacitor type. In FIG. 2, for example, 16,384 memory cells C.sub.00, C.sub.01, . . . , C.sub.0,127 ; C.sub.10, C.sub.11, . . . , C.sub.1,127 ; . . . , C.sub.127,127 are arranged in 128 rows and 128 columns to form matrixes at intersections of word lines WL.sub.0, . . . , WL.sub.63, WL.sub.64, . . . , WL.sub.127 and bit lines BL.sub.0, BL.sub.0, BL.sub.1, BL.sub.1, . . . , BL.sub.127, BL.sub.127. In this case, each sense amplifier, SA.sub.0, SA.sub.1, . . . , SA.sub.127, is located between each pair of the bit lines, such as BL.sub.0 and BL.sub.0, with each bit line being connected to a respective side of the sense amplifier.
In addition, dummy memory cells DC.sub.00, DC.sub.01, . . . , DC.sub.0,127 are connected to the bit lines BL.sub.0, BL.sub.1, . . . , BL.sub.127, respectively, while dummy memory cells DC.sub.10, DC.sub.11, . . . , DC.sub.1,127 (FIG. 2B) are connected to the bit lines BL.sub.0, BL.sub.1, . . . , BL.sub.127, respectively. Further, transistors Q.sub.a0, Q.sub.a1, . . . , Q.sub.a,127 are connected to the bit lines BL.sub.0, BL.sub.1, . . . , BL.sub.127, respectively, in order to precharge these bit lines, while, transistors Q.sub.b0, Q.sub.b1, . . . , Q.sub.b,127 (FIG. 2B) are connected to the bit lines BL.sub.0, BL.sub.1, . . . , BL.sub.127, respectively, in order to precharge these bit lines.
In order to select one of the word lines WL.sub.0, . . . , WL.sub.63, WL.sub.64, . . . , WL.sub.127, word decoders WD.sub.0, . . . , WD.sub.63, WD.sub.64, . . . , WD.sub.127 each comprising an NOR gate, are connected to the word lines through gates G.sub.0, . . . , G.sub.63, G.sub.64, . . . , G.sub.127 which are controlled by a clock signal .phi..sub.WL. In addition, in order to select one of dummy word lines DWL.sub.0 and DWL.sub.1, dummy word decoders DWD.sub.0 and DWD.sub.1 each comprising an NOR gate are connected to the dummy word lines through gates G.sub.-1 and G.sub.128 which are also controlled by the clock signal .phi..sub.WL. In this case, each of the word decoders WD.sub.0, . . . , WD.sub.63, WD.sub.64, . . . , WD.sub.127 receives a combination of seven signals A.sub.0, A.sub.0, . . . , A.sub.6, A.sub.6, selected from fourteen address signals, while each of the dummy word decoders DWD.sub.0 and DWD.sub.1 receives a signal, for example, the address signal A.sub.6 and A.sub.6, respectively.
The operation of the device of FIG. 2 will be explained by using FIG. 3 and FIGS. 4A, 4B and 4C. FIG. 3 is a circuit diagram of a part of the device of FIG. 2, for explaining the read operation of the memory cell C.sub.00 and FIGS. 4A, 4B and 4C are timing diagrams of the signals appearing in the circuit of FIG. 3. In more detail, FIGS. 4B and 4C are used for explaining the read operation for reading the data "0" and "1", respectively. Note that the capacitance of a capacitor C.sub.d of the dummy memory cell DC.sub.1 is about one-half of that of a capacitor C.sub.m of the memory cell C.sub.00.
In FIG. 3, the sense amplifier SA.sub.0 comprises two cross-coupled transistors Q.sub.c and Q.sub.d which constitute a flip-flop, and two transistors Q.sub.e and Q.sub.f for pulling up the bit lines BL.sub.0 and BL.sub.0. In addition, the bit lines BL.sub.0 and BL.sub.0 are connected to data bus lines DB and DB, respectively, by transistors Q.sub.g and Q.sub.h controlled by a column selection signal CL.sub.0 which are, however, not shown in FIG. 2. In addition, the dummy cell DC.sub.1 comprises a transistor Q.sub.d1 and a capacitor C.sub.d which are similar to the transistor Q.sub.m and the capacitor C.sub.m, respectively, of the memory cell C.sub.00 and in addition, a transistor Q.sub.d2 for discharging the capacitor C.sub.d in the stand-by state.
In the stand-by state, the transistors Q.sub.a0 and Q.sub.b0 are turned on by the potential of the reset signal RST being high, so that the bit lines BL.sub.0 and BL.sub.0 are precharged to the power supply voltage V.sub.cc and simultaneously, a transistor Q.sub.d2 of the dummy memory cell DC.sub.1 is also turned on, so that the capacitor C.sub.d is discharged; that is, the potential at a node N.sub.2 is the power supply voltage V.sub.ss (ground). After that, the potential of the reset signal RST returns to the voltage V.sub.ss so that the bit lines BL.sub.0 and BL.sub.0 are floating.
In order to read the data stored in the cell C.sub.00, the word decoder WD.sub.0 (FIG. 2) is triggered and as illustrated in FIG. 4A, the potential of the clock signal .phi..sub.WL rises, so that the potential V.sub.WL of the word line WL.sub.0 rises at a time t.sub.1, and accordingly the transistor Q.sub.m conducts. As a result, if the data stored in the cell C.sub.00 is "0", a current flows from the bit line BL.sub.0 into a node N.sub.1 of the cell C.sub.00, so that, as illustrated in FIG. 4B, the potential V.sub.BL of the bit line BL falls from V.sub.cc to V.sub.cc -.DELTA.V.sub.BL and in turn, the potential V.sub.N1 at the node N.sub.1 rises from V.sub.ss to V.sub.cc -V.sub.th, where V.sub.th is a threshold voltage of the transistor Q.sub.m. In this case, the voltage-drop .DELTA.V.sub.BL is ##EQU1## where C.sub.B and C are capacitances of the bit line BL and the capacitor C.sub.m, respectively. On the other hand, simultaneously, the dummy word decoder DWD.sub.1 (FIG. 2) is triggered so that the potential V.sub.DW1, as illustrated in FIG. 4A, of the dummy word line DWL.sub.1 rises and accordingly, a transistor Q.sub.d1 conducts. As a result, a current flows from the bit line BL.sub.0 into a node N.sub.2 of the dummy memory cell DC.sub.1, so that, as illustrated in FIG. 4B, the potential V.sub.BL of the bit line BL.sub.0 falls from V.sub.cc to V.sub.cc -.DELTA.V.sub.BL and in turn, the potential V.sub.N2 at the node N.sub.2 rises from V.sub.ss to V.sub.cc -V.sub.th. In this case, the voltage-drop .DELTA.V.sub.BL is selected so as to satisfy .DELTA.V.sub.BL =1/2.DELTA.V.sub.BL.
Contrary to the above, if the data stored in the cell C.sub.00 is "1", no current flows from the bit line BL.sub.0 into the node N.sub.1 of the cell C.sub.00, so that the potential V.sub.BL of the bit line BL remains at the same level V.sub.cc and the potential V.sub.N1 at the node N.sub.1 also remains at the same level V.sub.cc -V.sub.th. On the other hand, in the dummy memory cell DC.sub.1, as in the case where the data "0" is stored, the potential V.sub.BL of the bit line BL.sub.0 falls from V.sub.cc to V.sub.cc -.DELTA.V.sub.BL and in turn, the potential V.sub.N2 at the node N.sub.2 rises from V.sub.ss to V.sub.cc -V.sub.th, as illustrated in FIG. 4C.
In any case, the difference 1/2.DELTA.V.sub.BL in potential between the bit lines BL.sub.0 and BL.sub.0 is generated. Therefore, at a time t.sub.2, the potential V.sub.LE of a latch enable signal LE rises so as to trigger the sense amplifier SA.sub.0. As a result, one of the potentials V.sub.BL and V.sub.BL reaches V.sub.cc and the other reaches V.sub.ss.
Note that, in FIG. 4B, at a time t.sub.3, the potential V.sub.BL of the bit line BL.sub.0 rises from V.sub.cc -.DELTA.V.sub.BL to V.sub.cc due to the active pull-up effect, since the potential of a signal .phi..sub.1 rises so that the transistors Q.sub.e and Q.sub.f become conductive.
Next, by causing the potential of a column selection signal CL.sub.0 to be high, the potentials of the bit lines BL.sub.0 and BL.sub.0 are transmitted into an input/output amplifier (not shown) through the data bus lines DB and DB. After the read operation is completed, the potential V.sub.WL of the word line WL.sub.0 becomes V.sub.ss so that the memory device is in the stand-by state. At this time, the data "0" or "1" is stored in the memory cell C.sub.00.
In the case of the data "0" being stored in the memory cell C.sub.00, the charge Q.sub.1 =0 is stored in the capacitor C.sub.m, while, in the case of the data "1"being stored in the memory cell C.sub.00, the charge Q.sub.2 =C(V.sub.cc -V.sub.th) is stored in the capacitor C.sub.m. Therefore, the difference .DELTA.Q in charges between the data "0" and "1" is .DELTA.Q=C(V.sub.cc -V.sub.th). In the present invention, the difference .DELTA.Q is increased so as to increase the difference in potential between the bit lines BL.sub.0 and BL.sub.0 prior to the operation of the sense amplifier SA.sub.0, this increases the stability of the sense amplifier SA.sub.0 operation.
FIG. 5 is a block diagram illustrating an embodiment of the semiconductor memory device according to the present invention. In FIG. 5, the elements which are the same as those of FIG. 2 are denoted by the same references. In FIG. 5, the memory cells C.sub.00, C.sub.01, . . . , C.sub.0,127 ; C.sub.10, C.sub.11, . . . , C.sub.1,127 ; . . . , C.sub.127,127 are connected to power supply lines WL.sub.0, . . . , WL.sub.63, WL.sub.64, . . . , WL.sub.127, not to the power supply V.sub.ss (ground). In this case, the potentials of the power supply lines WL.sub.0, . . . , WL.sub.63, WL.sub.64, . . . , WL.sub.127 are changeable. However, the dummy memory cells DC.sub.00, DC.sub.01, . . . , DC.sub.0,127 and DC.sub.10, DC.sub.11, . . . , DC.sub.1,127 of FIG. 2 are not provided. Further, the potential for precharging the bit lines BL.sub.0 and BL.sub.0 is V.sub.cc -V.sub.th -.alpha.. Here, .alpha. is a voltage necessary for maintaining the conduction of the transistor Q.sub.m when the potential V.sub.WL of the word line WL.sub.0 is V.sub.cc.
In the present invention, the charges stored in the capacitors C of the memory cells are increased by causing the potentials of the power supply lines WL.sub.0, . . . , WL.sub.63, WL.sub.64, . . . , WL.sub.127 to be low and after that, to be high. The changes of the potentials of the power supply lines WL.sub.0, . . . , WL.sub.63, WL.sub.64, . . . , WL.sub.127 can be effected by a clock signal .phi..sub.WL through gates G.sub.0 ', . . . , G.sub.63 ', G.sub.64 ', . . . , G.sub.127 '.
The operation of the device of FIG. 5 will be explained by using FIG. 6 and FIGS. 7A, 7B and 7C. Here, FIG. 6 is a circuit diagram of a part of the device of FIG. 5 and FIGS. 7A, 7B and 7C are timing diagrams of the signals appearing in the circuit of FIG. 5. In more detail, FIGS. 7B and 7C are used for explaining the read operation for reading the data "0" and "1", respectively.
In the stand-by state, the transistors Q.sub.a0 and Q.sub.b0 (FIG. 5) are turned on by causing the potential of the reset signal RST to be high, during this time the bit lines BL.sub.0 and BL.sub.0 are precharged to V.sub.cc -V.sub.th -.alpha.. After the charging, the potential of the signal RST returns to the voltage V.sub.ss (ground) placing the bit lines BL.sub.0 and BL.sub.0 in a floating state.
In order to read the data stored in the cell C.sub.00, the word decoder WD.sub.0 (FIG. 5) is triggered and, as illustrated in FIG. 7A the potential of the clock signal .phi..sub.WL rises, so that the potential V.sub.WL of the word line WL.sub.0 rises at a time t.sub.1. As a result, the transistor Q.sub.m conducts and accordingly, if the data stored in the cell C.sub.00 is "0," a current flows from the bit line BL.sub.0 into the node N.sub.1 of the cell C.sub.00. Therefore, as illustrated in FIG. 7B, the potential V.sub.BL of the bit line BL falls from the precharged potential V.sub.cc -V.sub.th -.alpha. to V.sub.cc -V.sub.th -.alpha.-.DELTA.V.sub.BL and in turn, the potential V.sub.N1 at the node N.sub.1 rises from V.sub.ss to V.sub.cc -V.sub.th -.alpha..DELTA.V.sub.BL. In this case, the voltage-drop .DELTA.V.sub.BL is ##EQU2## On the other hand, the potential V.sub.BL of the bit line BL.sub.0 remains at the same level, since there is no dummy memory cell connected to the bit line BL.sub.0.
At a time t.sub.2 when the potential V.sub.LE of the latch enable signal LE rises as illustrated in FIG. 7A, the sense amplifier SA.sub.0 is triggered so as to amplify the potential difference .DELTA.V.sub.BL, as illustrated in FIG. 7B. After that, the potential of the signal .phi..sub.1 rises as illustrated in FIG. 7A, and the potential V.sub.BL of the bit line BL is pulled up to V.sub.cc via transistor Q.sub.f. Thus, the read operation for the data "1" is completed.
Next, as illustrated in FIG. 7A, the potential of the signal .phi..sub.WL falls from V.sub.cc to V.sub.ss and after that, again, it rises from V.sub.ss to V.sub.cc. Accordingly, at a time t.sub.3, the potential V.sub.WL of the power supply line WL.sub.0 falls from V.sub.cc to V.sub.ss and, at a time t.sub.4, it rises from V.sub.ss to V.sub.cc. During the falling of the potential V.sub.WL, the potential V.sub.N1 falls due to the capacitive coupling of the line WL.sub.0 and the node N.sub.1 ; however, the potential V.sub.N1 immediately returns to V.sub.ss due to transistor Q.sub.m being ON, as illustrated in FIG. 7B. In this case, a small quantity of charges is stored in the capacitor C.sub.m. After that, during the rising of the potential V.sub.WL, the potential V.sub.N1 rises also due to capacitive coupling; however, also in this case, the potential V.sub.N1 returns to V.sub.ss, so that the charges stored in the capacitor C.sub.m flow out. Thus, the refresh operation for the data "0" is completed.
It should be noted that, in the above-mentioned operation, the transistor Q.sub.m is always conductive, since the difference in potential between the gate and the source (or drain) is larger than the threshold voltage V.sub.th of the transistor Q.sub.m.
Contrary to the above, if the data stored in the cell C.sub.00 is "1," that is, the potential V.sub.N1 at the node N.sub.1 is higher than V.sub.cc -V.sub.th -.alpha., a current flows from the node N.sub.1 to the bit line BL.sub.0 when the potential V.sub.WL of the word line WL.sub.0 is V.sub.cc. As a result, the potential V.sub.BL of the bit line BL.sub.0 rises, while, the potential V.sub.BL of the bit line BL remains at the level V.sub.cc -V.sub.th -.alpha.. In this case, the difference in potential between the bit lines BL.sub.0 and BL.sub.0 is defined as .DELTA.V.sub.BL, as illustrated in FIG. 7C. At the time t.sub.2, the difference .DELTA.BL is amplified so that the potential V.sub.BL of the bit line BL.sub.0 reaches V.sub.cc and the potential V.sub.BL of the bit line BL.sub.0 reaches V.sub.ss. In this case, the potential V.sub.N1 at the node N.sub.1 is V.sub.cc -V.sub.th.
As illustrated in FIG. 7A, at the time t.sub.3 when the potential V.sub.WL of the power supply line WL.sub.0 is changed from V.sub.cc to V.sub.ss, the potential V.sub.N1 at the node N.sub.1 falls due to the capacitive coupling, as illustrated in FIG. 7C, so that a current flows from the bit line BL.sub.0 into the node N.sub.1. As a result, a quantity of charges is stored in the capacitor C.sub.m. Next, at the time t.sub.4 when the potential V.sub.WL is changed from V.sub.ss to V.sub.cc, the potential V.sub.N1 at the node N.sub.1 rises so that the charges stored in the capacitor C.sub.m tend to flow out; however, in this state, the charges never flow out. This is because, at this time, the potential V.sub.WL applied to the gate of the transistor Q.sub.m and the potential V.sub.BL applied to the drain of transistor Q.sub.m are both V.sub.cc, so that the transistor Q.sub.m is non-conductive. Therefore, when the potential V.sub.WL of the power supply line WL.sub.0 is changed from V.sub.ss to V.sub.cc, a value V.sub.cc is added to the potential V.sub.N1 at the node N.sub.1 so that this potential V.sub.N1 becomes 2V.sub.cc -V.sub.th. This is a so-called bootstrap effect. Thus, after the read operation and the refresh operation for the data "1" are completed, the charge (2V.sub.cc -V.sub.th).times.C is stored in the capacitor C.sub.m.
Therefore, prior to the read operation for the data "1", the potential V.sub.N1 at the node N.sub.1 is 2V.sub.cc -V.sub.th, as illustrated in FIG. 7C. In this state, again at the time t.sub.1 when the potential V.sub.WL of the word line WL.sub.0 is changed from V.sub.ss to V.sub.cc, a current flows from the node N.sub.1 into the bit line BL.sub.0, so that the potential V.sub.N1 at the node N.sub.1 is decreased and in turn, the potential V.sub.BL of the bit line BL.sub.0 is increased. In this case, the voltage-increase .DELTA.V.sub.BL of the potential V.sub.BL is ##EQU3## On the other hand, the potential V.sub.BL of the bit line BL.sub.0 remains at the same level V.sub.cc -V.sub.th -.alpha., since there is no dummy cell.
Thus, in the circuit of FIG. 6, the differences in potential between the bit lines BL.sub.0 and BL.sub.0, prior to the operation of the sense amplifier SA.sub.0, are ##EQU4## for the data "0" and "1", respectively. As compared with the conventional circuit of FIG. 3 in which such a difference is ##EQU5## the increase of the charge stored in the capacitor C.sub.m contributes to the increase of the difference in potential between the bit lines BL.sub.0 and BL.sub.0, which means that the stored charges in the capacitor C.sub.m are helpful in the read operation.
In the above-mentioned embodiment, the difference in potential between the bit lines BL.sub.0 and BL.sub.0 for the data "0" is different from the difference for the data "1"; however, the two differences can be equal by providing an appropriate dummy memory cell.
FIG. 8 is a block diagram illustrating another embodiment of the semiconductor memory device according to the present invention. In FIG. 8, the elements which are the same as those of FIG. 5 are denoted by the same references. In FIG. 8, dummy memory cells DC.sub.00, DC.sub.01, . . . , DC.sub.0,127; DC.sub.10, DC.sub.11, . . . , DC.sub.1,127 are provided in addition to the memory cells in FIG. 5. In this case, the capacitance of a capacitor of the dummy memory cells is the same as that of the memory cells.
The operation of the device of FIG. 8 will be explained by using FIG. 9 and FIGS. 10A, 10B and 10C. Here, FIG. 9 is a circuit diagram of a part of the device of FIG. 8 and FIGS. 10A, 10B and 10C are timing diagrams of the signals appearing in the circuit of FIG. 9. In more detail, FIGS. 7B and 7C are used for explaining the read operation for reading the data "0" and "1", respectively.
In the stand-by state, the bit lines BL.sub.0 and BL.sub.0 are precharged to V.sub.cc. In order to read the data "0", at the time t.sub.1 when the potentials V.sub.WL and V.sub.DW1 are changed from V.sub.ss to V.sub.cc, the potentials V.sub.BL and V.sub.BL of the bit lines BL.sub.0 and BL.sub.0 are both decreased from V.sub.cc to V.sub.cc -.DELTA.V.sub.BL (=.DELTA.V.sub.BL), as illustrated in FIG. 10B. The voltage-drop .DELTA.V.sub.BL (=.DELTA.V.sub.BL) is, in this case, ##EQU6## After that, at the time t.sub.2 when the potential V.sub.WL of the power supply line WL.sub.0 is changed from V.sub.cc to V.sub.ss, a current flows from the bit line BL.sub.0 to the node N.sub.1 of the cell C.sub.00, so that the potential V.sub.BL of the bit line BL.sub.0 is further decreased by ##EQU7## As a result, the difference in potential between the bit lines BL.sub.0 and BL.sub.0 is ##EQU8##
On the other hand, if the data stored in the cell C.sub.00 is "1", at the time t.sub.1, a current flows from the bit line BL.sub.0 to the node N.sub.2 so that the potential V.sub.N2 at the node N.sub.2 rises from V.sub.ss to V.sub.cc -V.sub.th and in turn, the potential V.sub.BL of the bit line BL.sub.0 falls, as illustrated in FIG. 10C. In this case, the voltage-drop .DELTA.V.sub.BL is ##EQU9## On the other hand, in the memory cell C.sub.00, the transistor Q.sub.m remains non-conductive so that the potential V.sub.BL of the bit line BL.sub.0 remains at the level V.sub.cc. Next, at the time t.sub.2, the falling of the potential V.sub.WL of the power supply line WL.sub.0 causes the potential V.sub.N1 at the node N.sub.1, to also be decreased; however, even in this case, the transistor Q.sub.m remains non-conductive so that the potential V.sub.BL of the bit line BL remains at the level V.sub.cc. Therefore, the difference in potential between the bit lines BL.sub.0 and BL.sub.0 is ##EQU10##
After such a difference in potential between the bit lines BL.sub.0 and BL.sub.0 is generated, at the time t.sub.3, the sense amplifier SA.sub.0 is activated. As a result, as illustrated in FIGS. 10B and 10C, one of the potentials V.sub.BL and V.sub.BL reaches V.sub.ss and the other reaches V.sub.cc. Further, at the time t.sub.4 when the potential V.sub.WL is changed from V.sub.ss to V.sub.cc, the potential V.sub.N1 at the node N.sub.1 returns to V.sub.ss or 2V.sub.cc -V.sub.th in accordance with the data being "0" or "1", as illustrated in FIG. 10B, 10C respectively.
In the embodiment as illustrated in FIGS. 8, 9, 10A, 10B and 10C, the falling of the potential V.sub.WL of the power supply line WL.sub.0 follows the rising of the potential V.sub.WL of the word line WL.sub.0 ; however, the falling of the potential V.sub.WL can occur simultaneously with the rising of the potential V.sub.WL, without problems. In addition, the two differences in potential between the bit lines BL.sub.0 and BL.sub.0 for the data being "0" and "1" can be the same by selecting the capacitance of the capacitor C.sub.d.
As explained hereinbefore, the present invention has an advantage, over the conventional device, in that the read operation is stable. This is because the charge stored in the memory cell can be about twice the usual charge, which increases the difference in potentials between a pair of bit lines prior to the operation of the sense amplifiers.
Claims
I claim:
1. A semiconductor memory device operatively connected to receive address signals and clock signals, said device comprising: first and second power supplies, the potential of said second power supply being lower than said first power supply potential; a plurality of word lines; a plurality of power supply lines; a plurality of pairs of bit lines; a plurality of sense amplifiers, respective of said sense amplifiers operatively connected between a corresponding pair of said pairs of bit lines; a plurality of memory cells, each comprising a transistor having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source, a capacitor having a predetermined capacitance and an electrode connected to the source of said transistor and another electrode connected to a corresponding one of said power supply lines; and clock means operatively connected to said power supply lines and to said word lines, for selectively supplying a clock signal to corresponding of said power supply lines in response to said address signals and after the potential of said corresponding word line rises and before the potential of said corresponding word line falls, the potential of said clock signal falls and after that, rises.
2. A device as set forth in claim 1, wherein said clock signal falls from the potential of said first power supply to the potential of said second power supply and after that, rises from the potential of said second power supply to the potential of said first power supply.
3. A device as set forth in claim 1 or 2, further comprising: two dummy word lines; and a plurality of dummy memory cells, respective of said dummy cells connected to a corresponding one of said bit lines, to a corresponding one of said two dummy word lines and to said second power supply.
4. A device as set forth in claim 3, wherein each of said dummy memory cells comprises: a first dummy transistor having a drain connected to said corresponding one of said bit lines, a gate connected to said corresponding one of said two dummy word lines; a dummy capacitor having predetermined capacitance and a first electrode connected to a source of said first dummy transistor and a second electrode connected to receive said second power supply; and a second dummy transistor having a drain and a source connected to the first electrode and to the second electrode, respectively, and a gate for receiving a reset signal.
5. A device as set forth in claim 4, wherein the capacitance of the dummy capacitor of said dummy memory cells is the same as that of the capacitor of said memory cells.
6. The device as set forth in claim 3, wherein each of said sense amplifiers comprises means for latching data from said corresponding pair of said pairs of bit lines, and wherein said fall and rise of said clock signal occurs after said latching.
7. A dynamic semiconductor memory device operatively connected to receive address signals and clock signals, a first power supply voltage, and a second power supply voltage lower than said first power supply voltage, comprising: a plurality of word lines, each having a potential; a plurality of power supply lines arranged parallel to said word lines; a plurality of bit line pairs, said bit line pairs and said word lines arranged in a matrix; a plurality of sense amplifiers, respective of said sense amplifiers operatively connected between a corresponding pair of said bit line pairs, and comprising means for latching data from said corresponding pair of said pairs of bit lines; a plurality of memory cells arranged at cross points of said matrix, each of said memory cells comprising a transistor having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source, a capacitor having a predetermined capacitance, having a first electrode connected to the source of said transistor and having a second electrode connected to a corresponding one of said power supply lines; and clock means operatively connected to receive said clock signals and said address signals and operatively connected to said word lines and said power supply lines for providing a negative clock pulse to corresponding ones of said word lines and power supply lines responsive to corresponding ones of said address signals and of said clock signals, wherein said clock means comprises means for providing control signals responsive to said corresponding of said control signals and to said clock signals, for providing said negative clock pulse after the potential of at least one of said corresponding ones of said word lines rises and before said potential falls.
8. A method of accessing a dynamic semiconductor memory device, which is operatively connected to receive address signals, a first power supply voltage, a second power supply voltage lower than the first power supply voltage, the device including power supply lines, word lines, bit line pairs, a memory cell array connected to the word lines, the power supply lines, and the bit line pairs, and sense amplifiers respectively connected to corresponding bit line pairs, each sense amplifier having an enable and disable state, said method comprising the sequential steps of: (a) precharging the bit line pairs to a predetermined voltage; (b) selecting one of the word lines, the sense amplifiers, the bit line pairs and the power supply lines; (c) applying the first power supply voltage to the selected word line; (d) enabling the selected sense amplifier; (e) applying the first power supply voltage to the selected bit line pair through the selected sense amplifier; (f) applying the second power supply voltage to the selected power supply line; (g) applying the first power supply voltage to the selected power supply line; and (h) applying the second power supply voltage to the selected word line.