Method and Device for Determining Acceleration and/or Deceleration of a Moving Object

The present invention relates to a method and device for determining varying acceleration or deceleration of an object, particularly acceleration or deceleration of an automotive vehicle wheel for use as part of an anti-skid control in a brake control system. More specificaly, the invention relates to a method and device for the acceleration and deceleration of an automotive vehicle wheel. The device measures the pulse period of a wheel rotation speed sensor signal by measuring the time interval over which suitable numbers of sensor signal pulses are received.

In accordance with automotive anti-skid brake control systems, it is necessary to effectively and accurately determine acceleration or deceleration of at least one automotive vehicle wheel. In various anti-skid control systems, a typical skid-control procedure is to determine a target wheel rotation speed based on the acceleration and/or deceleration thereof, and to control the actual wheel rotation speed to correspond with the target wheel rotation speed. The acceleration and/or deceleration of a wheel is determined by differentiation of a difference between wheel rotational speeds during a period and an immediately preceding period. Such an anti-skid control technique requires the accurate and rapid determination of the acceleration and/or deceleration .alpha. over a significant range of vehicle speed. The acceleration and/or deceleration of the vehicle is generally obtained from the following equation in which the intervals between successive pulses of a sensor signal fed from the wheel rotation speed sensor are denoted as Tn-1, Tn, Tn+1 . . . : ##EQU1##

In such a conventional system it is only possible to determine the difference in pulse period between each successive pulses. This creates a problem in that when the wheels, that rotate at a high velocity, the difference between successive pulse periods approaches zero which lowers the resolution of the calculated value of the acceleration and/or deceleration rate. This disadvantage is clearly illustrated in the following example.

If the brakes are applied to a vehicle moving at a speed of 100 km/h to decelerate at a rate of 0.1 G and assuming the pulse period of the wheel rotation speed sensor signal is measured with reference to a 1 .mu.s clock pulse, the pulse period of both the first and second sensor signal pulses Tn-1 and Tn will be 522 .mu.s. Thus, it is practically impossible to measure the difference between successive pulse periods. In order to eliminate the foregoing disadvantage of the conventional system, the system can be modified to measure the difference between successive intervals over which a predetermined number of pulses of the wheel rotation speed sensor are received. For example, in the above case of acceleration of 0.1 G from speed of 100 km/h with a 1 .mu.s clock pulse, the deceleration rate .alpha. can be adequately resolved by measuring the periods of successive of pulses. Note that under the same conditions as those specified above, except starting from the relatively low speed of 10 km/h, the period of a group of 8 pulses would be on the order of 40 ms. Therefore, according to this procedure, the difference between the pulse periods of adjacent groups of vehicle speed sensor pulses, which operating at high speeds, can be satisfactorily resolved. However, for determining the difference of the pulse periods are relatively low speeds the pulse grouping technique involves a rather long period of time (e.g. yoms at 10 km/h) which makes it difficult to effectively employ anti-skid brake control techniques.

Therefore, in conventional systems for determining acceleration and/or deceleration of wheel rotation, it is desirable to provide a system or device capable of accurately determining changes in vehicle speed sensor pulse group period and of minimizing the period of time need for determining those changes.

It is an object of the present invention to provide a method and device for effectively determining changes in speed sensor pulse group period in which the number of pulses comprising each group of pulses is increased at a given rate until the difference between the pulse group periods of compared groups of sensor signal pulses exceeds a predetermined value.

According to the present invention, there is provided a device for determining the acceleration of a moving object, for example the acceleration and/or deceleration of a rotation vehicle wheel of an automotive vehicle, comprising a sensor means for sequentially determining the instantaneous speed of the object and producing a pulse signal, the frequency of which is proportional to the determined speed, a clock signal generator generating a clock signal, the pulse period of which represents a unit time for the speed measurement, memory means for storing data indicative of measured pulse group periods of the sensor signal and an arithmetic means for effecting arithmetic operations for determining acceleration or deceleration of the moving object based on the stored data in the memory means. The device further comprises a means for detecting the presence of at least a minimal difference between successively measured sensor group periods and generating a command for increasing the number of pulses to be constituting a sensor signal period measured group, hereinafter referred to as a pulse group or group, when the difference between periods of successive pulse groups does not exceed a predetermined value. The device periodically increments the number of pulses which comprises a group, hereinafter referred to as a pulse number until the difference between successive sensor signal group periods is determined to be more than the predetermined value or until the number of pulses becomes equal to a given maximum.

In the preferred embodiment, the device further comprises a controller means for detecting the presence or absence of a change in of sensor signal frequency and for controlling of pulse number based upon results of arithmetic operations.

According to the present invention, a method for determining acceleration or deceleration of the moving object comprises the steps of determining the instantaneous speed of the object and producing a pulse signal, the frequency of which is proportional to the determined speed, measuring the pulse period of the pulse signal with a clock signal, the period of which serves as a unit time for measurement, comparing the measured period of pulse signal with the previously measured period to determine any difference there between, performing arithmetic operation for determining the acceleration or deceleration based upon the determined difference and outputting the obtained result of the arithmetic operations. The method further comprises the steps of determining whether the difference between successively measured periods of the sensor signal is larger than a predetermined value and increasing the period over which the sensor signal is measured if the difference between pulse group periods does not equal the predetermined value.

In the preferred embodiment, the maximum number of pulses to be is set at a predetermined maximum to limit the increment operation. When the pulse member is set at the maximum and the difference between successive sensor signal group periods does not exceed the predetermined value, the speed of the object is recognized as being constant.

The present invention will become more fully understood from the detailed description of the invention given hereinafter and from the accompanying drawings of a preferred embodiment of the invention which, however, should not be taken as limiting the invention thereto but only for elucidation and explanation only.

In the drawings:

FIG. 1 is a schematic block diagram of a preferred embodiment of a device for determining acceleration and/or deceleration rate of an automotive vehicle according to the present invention, in which is shown a general circuit construction of the device;

FIG. 2 is an illustration showing vehicle speed sensor pulse, in which chart (A) shows an example in which the period of individual pulses are measured and chart (B) shows an example in which the period of groups of three pulses are measured;

FIG. 3 is an illustration showing in exemplary relationship between clock pulses and sensor signal pulses;

FIG. 4 is an illustration showing an example of a set of pulse groups useful for determining acceleration;

FIG. 5 is a timing chart for the operation of a means for determining pulse group period of the sensor signal;

FIGS. 6 (a) to 6(d) are illustrations illustrating various ways of shifting the data stored in a memory unit, each of FIGS. 6(a) to 6(d) illustrates a different pattern of shifting depending upon the group pulse number;

FIG. 7 is a table showing the operation of the main control;

FIG. 8 is a circuit diagram of the main control, which illustrates one manner of determining the pulse number;

FIG. 9 is a block diagram of a pulse controller;

FIG. 10 is a block diagram of a memory means having shift registers which function to shift the determined periods of each group of sensor pulses according to the manner of shifting as shown in FIGS. 6(a) to 6(d);

FIG. 11 is a table showing inputs to each of the input terminals of a logic circuit which corresponds to a pattern of shifting the storage in the shift registors in the memory means;

FIG. 12 is a circuit diagram of the logic circuit in the memory means;

FIG. 13 is a block diagram of arthemetic operations effected in the logic circuit of FIG. 12; and

FIG. 14 is a circuit diagram of an output section outputting a signal indicative of the determined acceleration or deceleration of the vehicle.

Referring now to the drawings, particularly to FIG. 1, there is illustrated a general circuit construction of a preferred embodiment of a device for determining acceleration or deceleration of a moving object. The device 6 according to the present invention may be applied any system wherein the acceleration of a moving object is determined. Illustrated and described hereinafter one example of an application of the device wherein it is applied for determining the acceleration or deceleration of an automotive vehicle or the wheel rotation speed thereof. A clock pulse generator 20 generates a clock signal CLOCK having a given constant. The period of a sensor signal V.sub.RPM, indicative of a determined vehicle speed or wheel rotation speed; is generated by a vehicle speed sensor 28. It is preferable that the clock signal CLOCK has a period corresponding to a unit time of measurement, such as 1 ms or 1 .mu.s or the like. In the preferred embodiment, 1 .mu.s clock signal CLOCK is generated by the clock pulse generator 20. The clock signal CLOCK is fed to a counter 22. The counter 22 counts the inputted clock signals CLOCK and generate a signal CLOCK.sub.x, indicative of the counter value. In practice the counter signal CLOCK.sub.x can be any suitable form of electric signal, such as analog signal, digital signal or the like, however, in the shown preferred embodiment, it is a 8 bit binary signal indicative of the counter value. The counter signal CLOCK.sub.x is fed continuously to a latching circuit 24. The latching circuit 24 is responsive to a latch signal LATCH generated in a latch signal generator 26 which receives the sensor signal V.sub.RPM from the vehicle speed sensor 28. The sensor signal V.sub.RPM is a pulse signal having a frequency proportional to the determined vehicle speed or wheel rotation speed. The latch signal generator 26 counts the pulse of the sensor signal V.sub.RPM and generates the latch signal LATCH when the number of pulses counted equals a pre-set value. The pre-set value at which the latch signal LATCH is to be generated is determined by a main controller 40 which is described in detail hereafter.

Responsive to the latch signal LATCH, the latching circuit 24 latches the value of the counter signal CLOCK.sub.x at the time latch signal LATCH is received. Specifically, the latching circuit 24 latches the counter signal value to correspond to the pulse group period of the pre-set number of sensor signal pulses. A latched counter signal value CLOCK.sub.y is outputted from the latching circuit 24 to a memory unit 30 in the form of an 8 bit binary signal. The memory unit 30 comprises a memory control section 32 and three memory sections 34, 36 and 38. The memory control section 32 receives the latching circuit output CLOCK.sub.y and a shift control signal SHIFT from the main controller 40 in the form of a 2 bit binary signal. Based upon the shift control signal SHIFT, the memory control section 32 selects one of the memory sections 34, 36 and 38 in which to store the inputted latched value CLOCK.sub.y.

The memory sections 34, 36 and 38 comprise shift registers which store successive latched values of CLOCK.sub.y in a predetermined order.

For convenience of explanation, the latched values CLOCK.sub.y outputted sequentially by the latching circuit 24 will be labeled A, B, C . . . , and it will be assumed that the earliest latched value A is initially stored in the section 34 and the most recent latched value C is initially stored in the section 38.

It should be appreciated that each value A, B, C . . . is stored in the memory section 34, 36 and 38 as a binary number and therefore to the shift resisters of the memory sections are adapted to store digital values.

An arithmetic circit 50 reads out the stored values A, B, C . . . from the memory unit 30 and determines the difference between consecutive latched values A, B, C . . . , for example (B-A), (C-B), to determine the pulse group period for each of the periods Tn-1 and Tn shown in FIG. 2. The arithmetic circuit 50 further calculates (C-B)-(B-A) to obtain the difference between the determined pulse group periods. The difference value thus obtained is compared with a predetermined value to determined whether the period of sensor signal has varied between the periods Tn-1 and Tn.

The arithmetic circuit 50 generates a binary code signal D.sub.f based on the result of this operation. If there is a change in sensor signal frequency, the value of the binary code signal D.sub.f is set to 1. If there is no change, it is set to 0. The binary code signal D.sub.f is fed to an output circuit 60 and the main controller 40.

At the same time, the arithmetic circuit 50 calculates the acceleration and/or deceleration rate .alpha. of the vehicle or vehicle wheel speed based on the read out stored value A, B and C. The acceleration and/or deceleration rate .alpha. can be obtained from the following equation: ##EQU2## where N represents the number of pulses required in a group. The calculated value of the acceleration and/or deceleration rate .alpha. is also fed to the output circuit 60.

The main controller 40 is responsive to binary code signal D.sub.f to determine the number of pulses to be grouped. Also, the main controller 40 determines a shifting pattern for shifting the data in the memory section 34, 36 and 38. In other words, based upon the binary signal code D.sub.f, the main controller 40 generates a pulse number signal N and a shift control signal SHIFT. The pulse number signal N is a 4-bit binary code signal and the shift control signal SHIFT is a 2 bit binary code signal. Further, the main controller 40 receives an input indicating whether the frequency of the sensor signal has changed between two consecutive periods, e.g., T.sub.n-1 to T.sub.n, based upon the binary code signal D.sub.f fed from the arithmetic circuit 50. The main controller 40 increases at a given rate the number of pulses to be grouped and therefore increments the value of the pulse number N, if the value of the binary code signal D.sub.f is zero. The shift control signal SHIFT is modified so as to adapt the shifting pattern the incremented value of the pulse group number. At the same time, the main controller 40 generates a decision signal .beta. which normally has value 1. If the pulse number has been incremented to a predetermined maximum value but the binary code signal D.sub.f remains at in zero, the value of the decision signal .beta. goes to zero. The decision signal .beta. is fed to the output circuit 60 to finally determine the output therefrom.

Next, the details of the each of the circuits which make up the device of the present invention will be described with reference to FIGS. 4 to 14.

Referring now to FIGS. 4 and 5, there is illustrated an example of incrementing the pulse number and the relationship between the sensor signal V.sub.RPM, the counter value CLOCK.sub.x, the latch signal LATCH and the latched value CLOCK.sub.y. In the description which follows, the labels and assumptions used in connection with FIGS. 1-3 will be maintained.

In FIG. 4, the pulse number signal N generated by the main controller 40 is initialized to 1 and therefore the period of each adjacent sensor signal pulse is compared. Specifically, the pulse period, Tn-1 latched at time t.sub.1 is compared with the period Tn, latched time t.sub.2. If the pulse periods Tn-1 and Tn are substantially equal to one another or if the difference therebetween is so small that it can not be resolved, the main controller 40 increments the value of the pulse number signal N to 2. Responsive to the incrementation of the pulse number the pulse periods Tn-1 and Tn are added and are regarded as a pulse group period 2Tn-1. That is, the interval duration t.sub.0 to t.sub.2 wherein the first and second sensor signal pulses are inputted is regarded as one period of the new pulse group. The new pulse group period 2Tn-1 is compared to the pulse group period 2Tn measured over a time interval from t.sub.2 to t.sub.4. As before, the of pulses to be grouped is incremented by the main controller 40 if the difference between the periods of the pulse groups cannot be adequately resolved. If the difference between successive pulse group periods is zero or too small to be resolved, the pulse group periods 2Tn-1 and 2Tn are grouped or coupled together to from pulse group having a period of 4Tn-1 indicative of the time interval t.sub.0 to t.sub.4 during which the first to fourth sensor signal pulses are inputted. The pulse period 4Tn-1 is then compared with the pulse period 4Tn measured over the time interval t.sub.4 to t.sub.8.

In the present example, the predetermined maximum number of pulses to be grouped is 8. If the time difference between 8Tn-1 and 8Tn can not be adequately resolved, the main controller 40 determines that the speed of vehicle or wheel rotation has been constant over the interval t.sub.0 to t.sub.16 in which case the main controller 40 returns to its initial position wherein the periods of individual pulses are compared.

In FIG. 5, illustrates the relationships between the signals V.sub.RPM, CLOCK.sub.x, LATCH and CLOCK.sub.y and therefore mainly illustrate the operation of the latching circuit 24. FIG. 5, taken in view of FIG. 4, illustrates an example of counting the pulse group period for a group of 8 pulses. With reference to FIG. 2, the period of a sensor signal pulse V.sub.RPM is counted by the clock signal CLOCK. Therefore, the counter 22 counts up the number of clock signal CLOCK and outputs an output CLOCK.sub.x indicative of the counter value. Responsive to latch signal LATCH fed from the latch signal generator 26, the latching circuit 24 latches the value of counter output CLOCK.sub.x and outputs an output CLOCK.sub.y indicative of the latched value. The difference (Tn-1--Tn) between consecutive latched values represents the period of a pulse group measured over that counting interval.

At the end of each cycle of operation for determining the difference between the periods of successive pulse groups or individual pulses, the main controller 40 determines whether the pulse number should be incremented. According to the result of this determination, the shifting pattern of the latched counter A, B, C, . . . in the memory unit is determined and the main controller 40 generates the shift control signal SHIFT corresponding to the determined shifting pattern.

FIG. 6 is explanatory illustration of the various shifting patterns for shifting the stored data A, B, C, . . . . It should be noted that in FIG. 6, on each horizontal line, the indicia A, B, C, . . . at the left side represents the data stored in the memory section 34 and at right side represents data stored in the memory section 38. The first pattern (I), is to be used when a difference between the periods of individual pulses can be adequately resolved. In this case, the data A, B, C, . . . in the memory sections 34, 36 and 38 respectively are shifted in a given order. Specifically, the data A in the memory section 34 is cleared and the data B stored in section 36 is shifted to the section 34. Likewise, the data C is shifted to the memory section 36. The data D, as newly latched counter value CLOCK.sub.y, is stored in memory section 38.

Turning now to pattern (II), (FIG. 6(b)) the pulse number is reduced by one when the difference between the periods of successive pulse groups equals a predetermined value in the immediately preceeding cycle of operation. FIG. 6(b) illustrates an example where the original pulse group number was 2. A similar pattern shifting is also applicable to pulse groups having 4 or 8 pulses. In those cases, the data A and B respectively stored in the memory sections 34 and 36 are cleared and data C is shifted to the memory section 34. Additional data D and E is respectively stored in the memory sections 36 and 38.

According to (Pattern III, FIG. 6(c)), the pulse number is incremented from that of the immediately preceding cycle. As understood from the foregoing description, this pattern is applied when no difference between the periods of consecutive pulse groups is detected. In this case, the data A in the memory section 34 is maintained therein. The data B in the memory section 36 is cleared and the data C in the section 38 is shifted to the section 36. Fresh data D indicative of the period of the first of the newly incremented pulse groups is newly stored in section 38.

Pattern IV, FIG. 6(d)), is substantially same as the Pattern II (FIG. 6(b)) in the manner of shifting but illustrates the case where no difference between the period of successive pulse groups can be detected until pulse groups with the predetermined maximum number of pulses, i.e., 8 pulses are compared. Having noted the difference between Patterns II and IV, Pattern IV is omitted from further detailed description since it is substantially the same in other respects to each Pattern II.

FIG. 7 illustrates the numerical relationship between the pulse number and the shifting patterns corresponding to the pulse number. As explained above, the determination of the pulse number and selection of the shifting pattern are effected by the main controller 40. Accordingly, the outputs from and the input to the main controller 40 are shown the lowermost column in FIG. 7. As seen from FIG. 7, if there is a difference between the periods of successive pulse groups, the input D.sub.f from the arithmetic circuit 50 is set to 1 and otherwise is set to zero. When the period between successive individual pulses differs detectably, the main controller 40 selects the shifting pattern I and sets the pulse number for next cycle of operation to 1. If the difference of the pulse periods of successive multiple-pulse groups differ detectably, the main controller 40 selects shifting pattern II and sets the pulse number for in the next cycle of operation to 1. As should be clear from the above, any time the periods of successive pulse groups, including single pulse groups, differ detectably, the main controller sets the pulse number for the next cycle of the operation to 1. On the contrary, if no difference is detected while comparing the group periods, the main controller 40 increments the pulse number. In this case, the main controller 40 selects the shifting pattern III according to incrementation of the pulse number. If the incremented pulse numbers reaches the predetermined maximum but no change in the period is detected, the main controller 40 determines that the pulse period is constant in and sets the decision signal .beta. to zero. At the same time, the main controller 40 returns the pulse number to 1 and selects the shifting pattern IV.

Referring now to FIG. 8, there is illustrated a circuit according to a preferred embodiment of the main controller 40 of present invention. The main controller 40 comprises a plurality of AND gates, OR gates, and NAND gates, and a latching circuit 402. As stated above, the pulse number signal N generated by the main controller is a 4-bit binary code, the bits of which are labeled a.sub.1, a.sub.2, a.sub.3 and a.sub.4. Likewise, the shift control signal SHIFT is a 2-bit binary code, the bits of which are labeled b.sub.1 and b.sub.2.

The binary code (a.sub.1, a.sub.2, a.sub.3, a.sub.4) representing the value of current pulse number is latched and stored in the latching circuit 402. The value stored in the latching circuit 402 is reset by a reset signal RESET from a logic circuit 320. A delay circuit 448 is interposed between the logic circuit 320 (FIG. 10) and the latching circuit 402. Thereby, the reset signal RESET is inputted to the laching circuit 402 with a predetermined delay time .tau..sub.1 in order to reset the storage in the latching circuit. On the other hand, the binary code signal D.sub.f from the arithmetic circuit 50 is inputted to the main controller 40. Synchronously with the binary code signal D.sub.f, the binary code (a.sub.1, a.sub.2, a.sub.3, a.sub.4) of the pulse number signal N latched in the latching circuit 402 is fed back to a NAND gate NAND.sub.1, NAND gate NAND.sub.2, OR gate OR.sub.1, OR gate OR.sub.2, AND gate AND.sub.1, AND gate AND.sub.2 and AND gate AND.sub.3 through feedback lines 404, 406, 408, 410, 412, 414 and 416. The inputs of the NAND.sub.1 and OR.sub.2 receive the binary code signal D.sub.f from the arithmetic circuit 50 through lines 418 and 420. The inputs of the AND.sub.1, AND.sub.2 and AND.sub.3 receive inverted binary code signal D.sub.f through an inverter 422 and lines 424, 426 and 428. The NAND.sub.1 and OR.sub.1 determine the shifting pattern and generate the bits (b.sub.1, b.sub.2) of the shift control signal SHIFT in cooperation with a NAND gate NAND.sub.3. Generally, based on bits a.sub.1 and a.sub.4 l of the pulse number signal N and the binary code signal D.sub.f, the NAND.sub.1, OR.sub.1 and NAND.sub.3 gates determine the bits (b.sub.1, b.sub.2) of the shift control signal SHIFT. In this purpose, the input terminals of the gate NAND.sub.3 are connected to the output terminals of the NAND.sub.1 and OR.sub.1 gates through lines 430 and 432. As apparent from FIG. 8 the bit b.sub.1 of the shift control signal SHIFT is determined based on the bit b.sub.2 and the output of the gate OR.sub.1. The gates NAND.sub.1, AND.sub.2, AND.sub.3 and OR.sub.2 respectively determine the bits (a.sub.1, a.sub.2, a.sub.3, a.sub.4) of the pulse number signal N based on a preceding value (a.sub.2, a.sub.3, a.sub.4, a.sub.1) of the cyclically-offset bits of the previously outputted pulse number signal N and the binary code signal D.sub.f fed from the arithmetic circuit 50. Further, the NAND.sub.2 gate sequentially generates a decision signal .beta. based on the bit a.sub.4 of the pulse number signal previously outputted and the binary code signal D.sub.f.

FIG. 9 illustrates a preferred embodiment of the latch signal generator 26 of the present invention. The latch signal generator 26 generally comprises a latching circuit 260, a counter 262, a comparator 264 and mono-stable multivibrator 266. The bits (a.sub.1, a.sub.2, a.sub.3, a.sub.4) of the main controller output, i.e., the pulse number signal N is inputted to the latching circuit 260 via leads 440, 442, 444 and, 446, each connecting an input terminal of the latching circuit 260 to an output terminal of gates AND.sub.1, AND.sub.2, AND.sub.3 and OR.sub.2 respectively. The counter 262 receives sensor signal V.sub.RPM from the speed sensor 28 and counts the pulses from the sensor signal. The counter 262 generates a binary signal (v.sub.1, v.sub.2, v.sub.3, v.sub.4) based on the number of pulses counted and feeds the count to the comparator 264. The comparator also receives the latched pulse number signal N (a.sub.1, a.sub.2, a.sub.3, a.sub.4) from the latching circuit 260. The comparator 264 compares the input V.sub.RPM (v.sub.1, v.sub.2, v.sub.3, v.sub.4) from the counter 262 with the input N (a.sub.1, a.sub.2, a.sub.3, a.sub.4) from the latching circuit 260. If the counter value indicated in the binary signal (v.sub.1, v.sub.2, v.sub.3, v.sub.4) is equal to the value of the pulse number signal N, the comparator 264 renders the mono-stable multivibrator 266 operative to generate a latch signal LATCH to be fed to the latching circuit 24. The latch signal LATCH generated by the monostable multivibrator 266 is a one-shot for activating the latching circuit 24 to latch the counter value CLOCK.sub.x therein. The latch signal LATCH is also fed back to the counter 262 to reset the counter value. Likewise, the latch signal LATCH is fed to the latching circuit 260 through a delay circuit 268 with a predetermined time lag .tau..sub.2 from when the signal LATCH was received by the counter 262. Responsive to the latch signal LATCH, the contents of the latching circuit 260 are reset.

Thus, the latch signal generator 26 generates the latch signal LATCH when the number of sensor signal pulses counted equals a pre-set value for latching the counted clock signal value CLOCK.sub.x in the latching circuit 24. Thus, when the selected shifting pattern is I or III, (FIGS. 6(a) and (c)) the pulse number circuit 26 generates a latch signal during one cycle of operation and when the selected shifting pattern as II, (FIG. 6(b)) two shift control signals are generated per cycle of operation.

FIG. 10 illustrates a preferred embodiment of the memory unit 30 including memory control section 32 and memory sections 34, 36 and 38. Each of the memory section comprises a shift register 340, 360 and 380 and associated latching circuits 342, 362 and 382 respectively. The memory control section 32 generally comprises a logic circuit 320 and a counter 330. The logic circuit 320 is connected to the output terminals of the NAND.sub.1 and NAND.sub.3 gates of the main controller 40 in order to receive therefrom the bits (b.sub.1, b.sub.2) from the shift control signal SHIFT. Each pair of logic circuit output terminal 321 and 322, 323 and 324, 325 and 326 are respectively connected to input terminal pairs 343 and 344, 363 and 364, 383 and 384 of the shift registers 340, 360 and 380 respectively. The logic circuit 320 generates signals to be fed to respective shift registers 340, 360 and 380. The value of each signal is determined by the shift control signal SHIFT. Each of signals fed from the logical circuit 320 to the shift register 340, 360 and 380 is a binary code having value of either 1 or 0. Based on the combination of the inputted signal value, the functional mode of the shift registers 340, 360 and 380 is determined. Each shift register is capable of functioning in any of the following three modes as follows in accordance with the inputted signal value.

MODE I: when both the input signals are binary zeros, the shift register is not responsive the clock pulses;

MODE II: when the input signals to the input terminal 322, 324 or 326 is a binary 1 and the input signals to the input terminal 321, 323 or 325 is a binary zero, the shift register shifts its storage to right; and

MODE III: when the input signal to the input terminal 322, 324 or 326 is zero and the signal to the input terminal 321, 323 or 325 is a binary 1, the shift register receives fresh data in the a form of an 8-bit binary signal as a newly latched counter value CLOCK.sub.y from the latching circuit 24.

Each shift register 340, 360 and 380 sequentially generates an output representative of the stored counter value A, B, C, . . . . The output A, B, C of the shift registers 340, 360 and 380 are inputted to the latching circuits 342, 362 and 382 which also receives reset signals RESET from the logical circuit 320. These reset signal RESET are produced by the logical circuit 320 when all of the shift registers are operating in MODE I and are therefore not responsive to clock pulses. This condition of the shift registers 340, 360 and 380 represents a stable condition at the end of the shifting operation. The latching circuits 342, 362 and 382 are responsive to the reset signal RESET from delay circuit 327 which interposes delay time .tau..sub.3. On receipt of the reset signal RESET, the labeling circuit become operative to latch inputs A, B, C, . . . from the shift registeres 340, 360 and 380. After latching the register outputs A, B, C, . . . , the latching circuits 342, 362 and 382 respectively output the latched value A, B, C, . . . to the arithmetic circuit 50.

Each shift register 340, 360 and 380 also receives a clock signal CLOCK from clock signal generator 20 through clock gate 302 and an input terminal 345, 365 and 385. The clock signal CLOCK is also inputted to a clock counter 304 which counts the number of clock signals. Each time the counter 304 counts pulses 8 clock, it increments the number stored in cell bits c.sub.1, c.sub.2 and c.sub.3 by a binary value 1. The clock counter 304 outputs a 3-bit binary signal (c.sub.1, c.sub.2, c.sub.3) to the logic circuit 320. The counter value of the clock counter 304 is reset in response to a reset signal RESET from the logic circuit 320 through delay circuit 327 which interposes a given time delay .tau..sub.3.

A flip-flop 306 is positioned between the logic circuit 320 and the clock gate 302 reset input terminal R of the flip-flop 306 is connected to the logic circuit 320 through the delay circuit 327. A set input terminal S is connected to the logic circuit 320 through the delay circuit 327 and another delay circuit 328. Therefore, the reset signal R from the logical circuit 320 is receivedly both of the input terminals R and S but with a different time lag corresponding to .tau..sub.4. The delay time .tau..sub.4 set in the delay circuit 328 preferably corresponds to the duration (.tau..sub.4) of one cycle of operation for determining acceleration and/or deceleration. Thus, the flip-flop 306 is set by the reset signal RESET inputted from the set input terminal with a delay (.tau..sub.3 +.tau..sub.4) time given by the delay circuits 327 and 328 and is reset by the reset signal RESET inputted through the delay circuit 327.

The logic circuit 320 also receives a shift control signal SHIFT in the form of binary bits b.sub.1 and b.sub.2. The logical circuit 320 also receives the clock counter output in the form of binary bits c.sub.1, c.sub.2 and c.sub.3. Based on these inputs, the logical circuit 320 determines the shift mode signals SHIFT.sub.1 to SHIFT.sub.6, and the reset signal RESET. The relationships between the combinations of the inputs and the shift mode signals SHIFT.sub.1 to SHIFT.sub.6 are shown in FIG. 11, in the form of a table.

The operation of memory unit 30 will now be described in detail with reference to FIG. 11. In the following description, the functions of the various elements of the memory unit will be explained in connection with a particular shifting pattern.

At first, the flip-flop 306 assumes its set position responsive to reset signal RESET from the logic circuit 320 through delay circuits 327 and 328. In this state, the flip-flop 306 signal an output to the clock gate 302 through the line 303. Responsive to that output, the clock gate 302 operates to pass the clock signal CLOCK from the clock pulse generator 20 therethrough.

Where the shifting pattern from the main controller 40 is PATTERN I and the counter value of the clock counter 304 is zero so that the shift registers 340, 360 and 380 are generating in MODE II, (defined hereinabove) the stored values in the shift registers 340, 360, 380 are shifted to the right by 1 bit. Until 8 clock signal pulses are counted by the clock counter 304, the counter output (c.sub.1, c.sub.2, c.sub.3) is kept in zero in order that the shift registers 340, 360 and 380 will continue shifting their contents to the right by 1 bit. Responsive to the 8th clock signal pulse, the counter value (c.sub.1, c.sub.2, c.sub.3) becomes 1 to switch the modes of shift registers 340, 360 and 380 to I, I and III respectively. In this position, the shift registers 340, 360 are in states inhibiting clock pulse input and the shift register 380 is operable to receive fresh data from the latching circuit 24. The clock counter 304 is responsive to the 8th pulse inputted after the preceding 8th pulses to increment the counter value to 2. In this counter condition, the shift registers 340, 360 and 380 are all in MODE I thereby inhibiting clock input. At the same time, the logical circuit 320 produces the reset signal RESET with the binary value of 1. After the time delay .tau..sub.3 set in the delay circuit 327, the reset signal RESET is received by the flip-flop 306 through the reset input terminal R to turn the flip-flop off. Thus, the output value from the flip-flop goes to zero and closes the clock gate 302. The reset signal RESET is also fed to the clock counter 304 to reset the counter value and to the shift registers 340, 360 and 380 through the delay circuit 327 to cause those registers to output their contents to the respectively corresponding latching circuit 342, 362 and 382 respectively. The latched value in each latching circuit 342, 362 and 382 is then outputted to the arithmetic circuit 50.

As in the foregoing PATTERN I, at first, the flip-flop 306 is in a set position in response to the reset signal RESET produced by the logic circuit 320 and received via the delay circuits 327 and 328. In this condition, the flip-flop 306 operates an output to the clock gate 302 through the line 303 to open the latter. In this state, the clock signal CLOCK from the clock pulse generator 20 is transmitted to the clock counter 304. As stated above, the shifting pattern selected by the main controller 40 is PATTERN II and since the counter value outputted from the clock counter 304 is zero, the shift register 340, 360 and 380 are in shifting MODE I. Therefore, the data in each shift register 340, 360 and 380 is shifted 1 bit to right. When the 8th clock signal is inputted, the contents A, B, C . . . in the shift registers are shifted 8 bits, and have therefore been shifted into the adjacent register. In other words, the value B previously stored in the shift register 360 is now shifted to the shift register 340 and the value C in the shift register 380 is shifted to the register 360. At this time, the value of the contents of the shift register 380 is zero.

Responsive to the 8th clock signal, the counter value in the clock counter increase to 1. As a result the shifting modes of the shift registers 340 and 360 changes to MODE I, i.e., clock inhibit state, and the shifting mode of the shift register 380 becomes MODE III and is operable to receive fresh data D from the latching circuit 24. Receipt of the next 8 clock signal causes the counter value in the clock counter 304 to increase to 2. In this counter position, shifting modes of the shift registers 340, 360 and 380 are all changed to MODE II. Thereby, the contents of the shift registers shifts 1 bit to the right. This shifting operation of the shift registers 340, 360 and 380 is maintained until the next 8 clock pulses are counted. Thereupon, the data C in the shift register 360 is shifted to the shift register 340 and data D in the shift register 380 is shifted to the shift register 360. Then, the shift register 380 is reset to zero. Thereafter the counter value of the clock counter increases to 3 to switch the shift registers 340 and 360 to shifting mode MODE I, i.e., clock inhibit state. The shift register 380 switches to MODE III to receive fresh data E from latching circuit 24. Thus, the data C, initially stored in the shift register 380, is shifted to the shift register 340 and the shift registers 360 and 380 receive fresh data D and E respectively from the latching circuit in synchronism with the clock signal CLOCK.

As in the foregoing PATTERN I, the shift registers 340, 360 and 380 are all in MODE I to inhibit clock input. At the same time, the logic circuit 320 produces a reset signal RESET having a value of 1. After the time delay .tau..sub.3 set in the delay circuit 327, the reset signal RESET to the flip-flop 306 through the reset input terminal R switches the flip-flop output to its low or zero value. Thus, the output from the flip-flop goes to zero thereby closing the clock gate 302. The reset signal RESET is also fed to the clock counter 304 to reset its value and to to the shift registers 340, 360 and 380 through the delay circuit 327 to cause those registers to output the contents therein to the corresponding latching circuits 342, 362 and 382 respectively. The latched value in each latching circuit 342, 362 and 382 is outputtted therefrom to the arithmetic circuit 50.

As in the foregoing PATTERN I, at first the flip-flop 306 switches to its set position in response to the reset signal RESET produced by the logic circuit 320 and inputted via the delay circuits 327 and 328. The output of the flip-flop 306 is fed to the clock gate 302 to open that gate same. Thus, the clock signal CLOCK fed from the clock pulse generator 20 passes through the clock gate 302 and to the clock counter 304. In this case, since the shifting pattern determined by the main controller 50 is PATTERN III, and the counter value of the clock counter 304 is zero, the shift register 340 is in MODE I and the shift registers 360 and 380 are in MODE III. In response to the 8th clock signal, the counter value in the clock counter 304 increases to 1 and the data B and C stored in the shift registers 360 and 380 respectively are shifted to the adjacent shift registers. However, in this case, since the shift register 340 is in a clock inhibiting state, the data B shifted from the shift register 360 cannot be stored in the register 340. Consequently, only the data C in the shift register 380 is shifted to the register 360.

In response to to increasing the counter value by 1, the shift registers 340 and 360 switch to MODE I to inhibit the clock and shift register 380 switches to MODE III to receive fresh data D from the latching circuit 24. In this condition, the clock signal CLOCK from the clock signal generator 20 is inputted to the clock counter 304. The clock counter 304 is responsive to the 8th clock pulse to increase the value thereof to 2. In this condition, the shift registers 340, 360 and 380 are all in MODE I to inhibit clock pulse input. At the same time, the logic circuit 320 produces a reset signal RESET having a value of 1. After the time delay .tau..sub.3 set by the delay circuit 327, the reset signal RESET to the flip-flop 306 through the reset input terminal R switches the flip-flop output to its low or zero value. to thereby close the clock gate 302. The reset signal RESET is fed to the clock counter 304 to reset the counter value and fed to the shift registers 340, 360 and 380 through the delay circuit 327 to cause the registers to output their contents to the corresponding latching circuit 342, 362 and 382 respectively. The latched value in each latching circuit 342, 362 and 382 is then outputted to the arithmetic circuit 50.

Referring now to FIG. 12, there is illustrated a preferred circuit construction of the logic circuit 320 which serves as the memory control section 32 of the memory unit 30. The logic circuit 320 generally comprises NAND gate NAND.sub.4, AND gates AND.sub.4, AND.sub.5 and AND.sub.6 and OR gates OR.sub.3, OR.sub.4, OR.sub.5 and OR.sub.6. The NAND.sub.4 is connected with the NAND.sub.1 and NAND.sub.3 of the main controller 50 to receive the bits b.sub.1 and b.sub.2 from the shift control signal SHIFT. The gate OR.sub.3 has three input terminals each of which is connected to an address location of the clock counter 304. Therefore, through the gates NAND.sub.4 and OR.sub.3, shift control signals b.sub.1 and b.sub.2 and counter value c.sub.1, c.sub.2 and c.sub.3 are inputted to the logic circuit 320. Further, the output of the gate NAND.sub.3 of the main controller 50 is inputted to the gate AND.sub.6, and inverted by inverter 330 and then inputted to gate AND.sub.5. The output of gate NAND.sub.1 is also inputted to gate AND.sub.5 together with the inverted value of bit c.sub.1 from the clock counter which is inputted through an inverter 332. Bit c.sub.2 from the counter is also inputted to gate AND.sub.5. The counter value bit c.sub.2 is further inputted to gate AND.sub.6. The gate AND.sub.4 receives outputs from gates NAND.sub.4 and OR.sub.3 and produces an output to be fed to an input of gate OR.sub.5. The other input of gate OR.sub.5 receives an output of gate AND.sub.5. Therefore, gate OR.sub.5 determines the value of the output from the terminal 343 based upon the outputs from gates AND.sub.4 and OR.sub.5. The output of gate OR.sub.5 is the same as the output of the terminal 343 is also fed to gate OR.sub.6 which also receives the output from gate OR.sub.3. Gate OR.sub.6 determines the value outputted at the terminal 363. The output of gate OR.sub.4 is inverted by an inverter 334 and outputted at terminal 383. The output of gate OR.sub.4 is further outputted as the reset signal RESET.

As will be seen from the drawing, the output values of the output terminals 344 and 364 are constantly zero and do not vary. Further, the output terminal 384 outputs the value c.sub.1 of the clock counter 304 as is.

FIG. 13 illustrates a preferred construction of the arithmetic circuit for determining the acceleration and/or deceleration rate .alpha.. The arithmetic circuit 50 generally comprises a plurality of subtractors, dividers and multipliers. Subtractors 502, 504 and 506 are connected to the latching circuits 342, 362 and 382 respectively of the memory unit 30 in order to receive therefrom the register outputs A, B, C . . . representative of respective counter pulse periods of the sensor signal. Each subtractor 502, 504 and 506 subtracts a register output value from that of the other register. Namely, the subtractor 502 calculates B-A, subtractor 504 calculates C-B and subtractor 506 calculates C-A.

It is advantageous to use the outputs (B-A, C-B) of the subtractor 502 and 504 to represent the periods while the predetermined number of pulses of the sensor signal are being counted. The outputs of the subtractors 502 and 504 are fed to a subtractor 508. The subtractor 508 effects the following calculation:

to obtain the difference .alpha.t of the periods. The difference .alpha.t is then compared in a comparator 510 with a predetermined value t.sub.set to determine whether the sensor signal period has varied during the measurement period. At the same time, the output of the subtractors 502 and 504 are inputted to dividers 512 and 514 which generate the respective reciprocal value (1/C-B, 1/B-A) of the subtractor outputs (C-B, B-A). The divider output (1/C-B, 1/B-A) are fed to a subtractor 516 to calculate the value of

The output of the subtractor 516 is fed to a multiplier 518 which multiplies output of the subtractor 516 by the pulse number N determined by the main controller 40 and indicated in the pulse number control signal N (a.sub.1, a.sub.2, a.sub.3, a.sub.4). Accordingly, the multiplier 518 is connected to the main controller 40. In response to the input from the main controller 40, indicative of the determined pulse number, the multiplier calculates the value of ##EQU3## The result of this multiplication is fed to a divider 520. In the divider 520, the output of the multiplyer 518 is divided by the output of the subtractor 506 to obtain the the acceleration and/or deceleration rate .alpha. as follows: ##EQU4##

Based on the result of this previously described comparation operation, the comparator 510 outputs a binary code signal D.sub.f which is fed to the main controller 40 and the output section 60. The output of the divider 520, which is indicative of the determined acceleration and deceleration rate .alpha., is also fed to the output section 60.

FIG. 14 shows a preferred construction of the output section 60 according to the present invention. The output section 60 comprises a gate circuit 600 and a latching circuit 620. The gate circuit 600 has 8 AND gates each of which corresponds to an output terminal of the arithmetic circuit 50. To each of the AND gates, one bit of the output .alpha., which is in the form of an 8-bit binary number, is inputted. Also, each AND gate of the gate circuit 600 is connected to gate NAND.sub.2 (FIG. 8) to receive therefrom the decision signal .beta.. The gates 600 open in response to the decision signal .beta. having a value of 1. In this position, the output of the arithmetic circuit 50 passes through the gate circuit 600 and is received by the latching circuit 620. The decision signal .beta. is also inputted to an OR gate OR.sub.7 through an inverter 622. The binary code signal D.sub.f is also inputted to the gate OR.sub.7 from the comparator 510. The gate OR.sub.7 outputs a latching signal L whenever the input .beta. is zero or the input D.sub.f is 1. If the latching signal L is outputted from gate OR.sub.7 to latching circuit 620, the input value from the gate circuit 600 is latched and outputted. If the latching signal L is absent, the latching circuit 620 permit the input from the gate circuit to pass therethrough and be outputted. In other words, if a difference between the sensor signal periods is detected and decision signals .beta. and D.sub.f are set to have values of 0 and 1 respectively the latching circuit 620 outputs the gate circuit 600 output indicative of the acceleration and/or deceleration rate .alpha. corresponding to the determined difference between the sensor signal periods. On the other hand, if the difference between the sensor signal period is determined to be constant, i.e., (D.sub.f =0) and the value of the decision signal .beta. is 1, the latching circuit 620 outputs the latched value and therefore maintains a constant output value. When both decision signals D.sub.f and .beta. are zero, the latching circuit output goes to zero indicating that the frequency of the sensor signal is constant and the vehicle or vehicle wheel speed is constant.

Thus, according to the present invention, there is provided a device for determining the acceleration and/or deceleration rate of an automotive vehicle speed or vehicle wheel rotation speed. The device according to the invention can effectively measure a wide range of vehicle speeds or wheel rotation speeds and adjust the number of pulses over which the sensor signal period to be compared is measured for accurately ascertaining any variation of the sensor signal period in order to adapt the pulse number to the vehicle speed or wheel rotation speed. The accuracy of results can be maintained within an acceptable range so that it may be applied to an anti-skid control system for the brake system of an automotive vehicle.

Although the present invention has described in detail in terms of the preferred embodiment of the present invention and with reference to the accompanying drawings, the invention should not be limited to the specific embodiment shown hereabove. For example, the device of the present invention can be applied for determining the vehicle or wheel rotation speed per se. Further, possible modifications expected from the foregoing descriptions are to be considered as to be included in the present invention.