Commutation Circuits for Thyristor Inverters

The present invention is directed to thyristor inverter circuits and, in particular, to commutation circuits for thyristors.

With the present interest in the use of variable frequency induction motors, state of the art inverters, whether they are thyristor or transistor based, are attracting attention. The thyristor inverter described in U.S. Pat. No. 3,207,974 which issued on Sept. 21, 1965 to W. McMurray, remains one of the most preferred, particularly in its modified form wherein a pair of diodes are connected across the commutation thyristors with a damping resistor connected between the juncture of the pair of diodes and the juncture of the commutation thyristors. This inverter is advantageous since it has a high efficiency, its commutation circuit components are small and it is suitable for pulse width modulation (PWM) operation. On the other hand, it has been found that this inverter has a propensity for misfirings and shoot-throughs and that protection against commutation failure or short circuit is difficult.

Power transistor inverters have emerged as a solution to many of these problems due to their control flexibility, however, power transistors cannot provide the power levels required in many applications.

It is therefore an object of this invention to provide reliable and flexible commutation for thyristors.

This and other objects are achieved in a commutation circuit for a thyristor which when conducting applies, a dc voltage to a load, where the commutation circuit includes an inductance, a capacitance and a commutation thyristor connected in series with the main thyristor, a first diode connected in reverse polarity across the commutation thyristor and a second diode connected in reverse polarity across the series connected commutation thyristor and capacitance, whereby the commutation of the thyristor is initiated by triggering the commutation thyristor. A further diode may be connected in reverse polarity across the thyristor to obtain soft or current commutation.

In an inverter which has at least a pair of inverter thyristors connected in series across a dc source with a juncture between the thyristors for connection to a load, the thyristor commutation circuit includes a pair of series connected commutation thyristors which are connected in parallel with the main pair of thyristors and a diode which is connected in reverse polarity across each of the thyristors. A first capacitance is connected between the juncture that is between the commutation thyristors and the juncture between the inverter thyristors. A first inductance is series connected between the dc source and the pairs of thyristors. The first inductance may be a single inductor or a number of inductors located in the various commutation paths in the inverter circuit.

The commutation circuit may further include a second inductance connected between the dc source and the first inductance with, a diode connected in reverse polarity across it, and a second capacitance connected in series with the second inductance across the dc source to provide fuseless protection.

In addition, a series connected ac switch and resistor may be connected across the first capacitance to ensure the complete discharge of the first capacitance.

In an inverter which has at least a pair of inverter thyristors connected in series across a variable dc source with a juncture between the inverter thyristors for connection to a load, the thyristor commutation circuit is essentially similar in operation, but requires added components and a separate fixed dc commutation source. The fixed dc source, with blocking diodes, is connected across the pair of inverter thyristors. A pair of series connected commutation thyristors and a pair of series connected auxiliary thyristors are connected in parallel across the fixed dc source. The juncture between the auxiliary thyristors is connected to the juncture between the inverter thyristors. A diode is connected in reverse polarity across each of the commutation and inverter thyristors. A first capacitance is connected between the juncture between the commutation thyristors and the juncture between the inverter thyristors. A first inductance is series connected between the fixed dc source and the pairs of commutation and auxiliary thyristors. A series connected ac switch and resistor may be connected across the first capacitance to ensure the complete discharge of the first capacitance.

Many other objects and aspects of the invention will be clear from the detailed description of the drawings.

In the drawings:

FIG. 1 illustrates the commutation circuit in a single quadrant chopper;

FIG. 2 illustrates currents and voltages in the circuit in FIG. 1;

FIG. 3 illustrates the commutation circuit in a single phase inverter;

FIGS. 4 and 5 illustrate inverters having split commutation inductances;

FIG. 6 illustrates one half cycle of inverter output current for a pulse width modulation inverter; and

FIG. 7 illustrates the commutation circuit for a variable dc source single phase inverter.

The commutation circuit in accordance with the present invention is illustrated in FIG. 1 where it is used with a single quadrant chopper 1. The chopper 1 consists of a gate controlled rectifier or thyristor 2 connected between a dc power source E and a load L. Load L will normally be predominantly inductive such as a motor which prevents sudden change in the load current. The commutation circuit for the thyristor 2 includes an auxiliary thyristor 3, a capacitor 4 and inductor 5, all connected in series with thyristor 2 and the power source E. The capacitor 4 and the thyristor 3 must be connected in parallel with the load L, however, the inductor 5 can be in any part of the series circuit. An auxiliary diode 6 is connected in reverse polarity across the thyristor 3 and a further diode 7 is connected in reverse polarity across thyristor 3 and capacitor 4. A further commutating diode 8 may be connected in reverse polarity across thyristor 2 if current commutation is used, i.e. the voltage drop across diode 8 is caused by a current flow through it, turns off the thyristor 2.

In operation, the power source E voltage is supplied to the load L via thyristor 2 in a controlled manner. Thyristor 2 is turned on by applying a pulse signal to the gate of thyristor 2 and turned off by the commutation circuit in accordance with the present invention. It is to be noted that capacitor 4 is at zero voltage while thyristor 2 is conducting and remains so until the beginning of each commutation cycle. The commutation of conducting thyristor 2 is initiated by triggering thyristor 3 at the desired time t.sub.o which is shown in FIG. 2. FIG. 2 illustrates the current i.sub.4 through capacitor 4, the current i.sub.L through load L and the voltage E.sub.4 across capacitor 4 during the commutation cycle to t.sub.o -t.sub.5. With thyristor 3 turned on, an oscillating current flows through inductor 5, thyristor 2, capacitor 4, and thyristor 3 back to the source E. At this time, the current i.sub.2 through thyristor 2 is the sum of the currents i.sub.4 through capacitor 4 and the current i.sub.L to load L. After reaching its peak, the the current i.sub.4 decreases and reverses at t=t.sub.1, flowing from E(-) through diode 6 and capacitor 4. Since the load current i.sub.L is constant this causes a decrease in the i.sub.2 current. At t=t.sub.2, the capacitor current i.sub.4 equals the load current i.sub.L and the thyristor current i.sub.2 becomes zero. During the interval t.sub.2 -t.sub.3, the excess of the capacitor current i.sub.4 is passed through diode 8 back to the source E, (i.sub.8 =i.sub.4 -i.sub.L). The voltage drop across diode 8 produces reverse biasing across thyristor 1 which commutates the thyristor 1. At t=t.sub.3, the capacitor current i.sub.4 is again equal to the load current i.sub.L and diode 8 stops conducting. From t= t.sub.3 to t=t.sub.5, the capacitor is supplying load L with a constant current, i.sub.8 =i.sub.L and the capacitor voltage E.sub.4 decreases linearly. At t=t.sub.5, diode 7 starts to conduct and the capacitor current i.sub.4 falls sharply to zero. The length of the t.sub.3 -t.sub.5 interval depends on the magnitude of the load current i.sub.6, the capacitor 4 resistance, the Q-factor of the inductor L and the supply voltage E. With the capacitor 4 discharged, it is again ready for the next commutation cycle. The next commutation cycle does not have to be initiated until another thyristor has to actually be commutated.

If hard or voltage commutation is desired, diode 8 is not included across the thyristor 2 to be commutated. A reverse biasing voltage of E-E.sub.4 occurs across thyristor 2, this voltage is much larger than any voltage provided by the forward voltage drop on diode 8 and turns-off the thyristor 2 in a very short time. However, this type of commutation increases the voltage transients in the circuit. The design of the inverter circuit in accordance with the present invention follows the conventional procedures established for McMurray-type circuits. The expressions for the value of the commutation capacitance C.sub.4 and inductance L.sub.5 are ##EQU1## where i.sub.L is the load current

tq is the thyristor 2 turn-off time,

E is the source voltage,

.nu. is the ratio between the maximum load current, and the peak commutation current which is E/.sqroot.L.sub.5 /C.sub.4

Q is .sqroot.L.sub.5 /C.sub.4 /R, and

R is the total resistance of commutation circuit path.

FIG. 3 illustrates a single phase inverter 10 which utilizes the commutation circuit in accordance with the present invention. This single phase inverter 10 may be used by itself or as one of an n-phase inverter fed from the same dc source E.

The inverter 10 consists of a pair of thyristors 11 and 12 connected to a voltage source E with the load L connected to the juncture 13 between thyristors 11 and 12. Thyristors 11 and 12 apply power of opposite polarity to the load L resulting in an alternating current of desired frequency through the load L.

The commutation circuit includes a commutating diode 14, 15 connected in reverse polarity across each of the thyristors 11 and 12. Auxiliary thyristors 16 and 17, each with a diode 30, 31, connected across it in reverse polarity, are connected to the source E. The commutation circuit further includes a commutation inductor 19 between the source E and the thyristors and a commutation capacitor 20 connecting juncture 13 to the juncture between thyristors 16 and 17.

The inverter 10 in FIG. 3 operates in the same manner as the chopper circuit described in FIG. 1. Conducting thyristor 11 is commutated by triggering thyristor 17 which causes an oscillating current in the path inductor 19, thyristor 11, capacitor 20, and thyristor 17 and which turns thyristor 11 off in the same manner as described in FIG. 1. Conducting thyristor 12 is commutated by triggering thyristor 16 which produces an oscillating current in the path inductor 19, thyristor 16, capacitor 20 and thyristor 12. It is to be noted that since the voltage on capacitor 20 is always zero when commutation is initiated, thyristors 11 and 12 may alternately be triggered and commutated for simple inverter operation, or each thyristor 11 or 12 may be triggered and commutated a number of times in sequence for pulse width modulated inverter operation. The need for resetting or recharging the commutation circuit as in conventional commutation circuits is not required.

The inverter in FIG. 3 further includes a filter capacitor 21 which responds to the instant current demand for the load L when an inverter thyristor 11, 12 is turned on.

Referring to FIG. 2, with no-load current, the commutation capacitor 20 should be ideally discharged at time t.sub.4. However, due to an inherent resistance in the commutation circuit (finite Q-factor) the circuit is not purely oscillatory but has some damping. Consequently, there will be some charge left on the capacitor 20 when the diode 30 stops conducting. With zero load current i.sub.L, this charge will be present when the next commutation cycle is initiated. If 11 and 12 are commutated alternately, this charge will alternate its polarity, without causing problems, providing all components can withstand the increased peak of the capacitor current. However, if either of the two main thyristor 11, 12 has to be commutated several times in succession there will be a pump-up increase of the commutation capacitor 20 voltage. To avoid that and to decrease the circuit's clearing time during light loads, a discharge circuit 22 is connected across the capacitor 20. The circuit consists of an ac switch which may be a triac or a pair of reverse polarity connected thyristors 23, 24 or transistors, in series with a resistor 25. Normally the discharge of capacitor 20 through resistor 25 may be initiated at the time T.sub.4, however, the discharge may be delayed depending on the operating frequency.

The reliability of the inverter circuit, in accordance with the present invention, may be further enhanced by adding a further dc side commutation circuit 26 to the inverter. This commutation circuit 26, as illustrated in FIG. 3, includes a parallel connected capacitor 27, a series connected inductor 28 shunted by a diode 29. This dc side commutation circuit 26 automatically turns off all inverter thyristors in case of a shoot through or a short between the inverter input terminals providing fuseless protection. Consider a shoot-through caused by an accidental triggering of both thyristors 16 and 17, or 11 and 12. The short circuit current would rise in an oscillatory manner with a period determined by capacitor 27 and inductor 19. The role of inductor 19 is to transiently isolate the voltage source E from the rest of the circuit by keeping the supply current constant. When the oscillating current reverses direction all diodes 14, 15, 30, 31 conduct and all thyristors 11, 12, or 16, 17, are commutated by the diode forward voltage drop. Further current reversal is blocked by the diodes 14, 15, 30 and 31. An attempt to re-start the inverter can then be made.

A practically identical process occurs when a short develops across the inverter terminals or when a thyristor fails to commutate. In all of these cases, an oscillatory current starts to discharge the capacitor 27 through a fault and then rings back through diodes 14, 15, 30, 31, thus commutating all thyristors 11, 12, 16, 17. The isolating inductance 28 has to be 50-60 times the commutation inductance 19 in order to effectively limit the current rise during a fault. Capacitor 27 has to be more than 5 times the commutation capacitor 20. The diode 29 provides a free-wheeling path for the current trapped in inductor 28 at the end of the commutation. This prevents a damping of the magnetic energy stored in inductor 28 and on capacitor 27 which would force the capacitor voltage significantly above the source voltage E.

It is to be noted, however, that, for practical reasons, fuses are still needed to protect against component failure. Furthermore, commutation circuit 26 will not protect against a high resistance short, such as arcing, since practically all commutation energy will be dissipated in the arc. It is to be noted that only one dc side commutation circuit 26 is required even in an n-phase inverter.

FIGS. 4 and 5 illustrate inverters in accordance with the present invention in which the commutating inductance in the circuit is divided or split. In FIG. 4, the commutation inductance is split into inductor 19a and 19b, where inductances L.sub.19a and L.sub.19b of inductors 19a and 19b, respectively, are equal to the inductance L.sub.19 of inductor 19 (FIG. 3). The commutation process is the same as in FIG. 3, i.e. the commutation of thyristor 11 being initiated by the triggering of thyristor 17 and the commutation of thyristor 12 being initiated by the triggering of thyristor 16, with capacitor 20 being at zero voltage.

If the ratio between inductors 19a and 19b is

then the voltage V.sub.T across the thyristors which do not conduct during commutation, i.e. thyristors 12 and 16, when thyristor 11 is commutated, is ##EQU2## where E.sub.20 is the voltage across the commutating capacitor 20. The maximum voltage E.sub.20 is 2E, as seen in FIG. 2, and therefore: ##EQU3## Since inductor 19a is normally smaller than inductor 19b, then the maximum voltage V.sub.T will be significantly smaller than 2E. However, fuseless protection using the dc-side commutation circuit described in FIG. 3 will not work well with this split inductance circuit since the peak commutation current which discharges capacitor 27 (FIG. 3), will become too high with inductor 19a being much smaller than inductor 19 (FIG. 3).

In FIG. 5, the inductance is split between each of the thyristor arms such that the inductance of each inductor 19c is half of the inductance of inductor 19 (FIG. 3).

The thyristor 11, 12, 16, 17, rating in this case is reduced to 1.5E and may be used with the protection circuit described in FIG. 3. This split inductance configuration ensures current sharing between all inverter legs when the commutation current through capacitor 20 rings back. Other variations of a split inductance including the use of saturable reactors are possible to obtain different degrees of reduction of the thyristor voltage ratings.

FIG. 7 illustrates a commutation circuit in accordance with the present invention for an inverter where the dc source is variable and may be adjusted to values near zero. The inverter 40 consists of a pair of thyristors 41 and 42 connected in series across a variable voltage source E.sub.v. The load L is connected to the juncture 43 between thyristors 41 and 42. Thyristors 41 and 42 apply power of opposite polarity to the load L resulting in an alternating current of desired frequency through the load L.

The commutation circuit includes commutating diodes 44, 45 connected in reverse polarity across each of the thyristors 41 and 42. Auxiliary thyristors 46 and 47, each with a diode 48, 49, respectively, connected across it in reverse polarity, are connected to a fixed commutation voltage source E.sub.c. The commutation circuit further includes a commutation inductor 50a between the source E.sub.c and the thyristors 46, 47, and a series connected commutation capacitor 51 and inductor 50b connecting juncture 43 to the juncture 52 between thyristors 46 and 47. In order to complete the loop for the commutation of thyristors 41 or 42, diodes 52 and 53 are connected across the positive and negative terminals, respectively, of voltage sources E.sub.v and E.sub.c. Diodes 52 and 53 provide the loop connection and also prevent current flow from source E.sub.c to source E.sub.v which is smaller.

As in FIG. 2, a discharge circuit which consists of a pair of reverse polarity connected thyristors 54 and 55 and a series resistor 56 are connected across inductor 50b and capacitor 51, assures that a build-up of voltage on capacitor 51 will not occur. Since the commutation circuit has its own voltage source, a pair of auxiliary charging thyristors 57 and 58 are required. They are connected from load juncture 43 to the cathode of thyristor 46 and the anode of thyristor 47, respectively.

To commutate thyristor 41 both thyristors 47 and 57 are triggered producing an oscillating current by charging and discharging capacitor 51. Capacitor 51 is charged through path source E.sub.c, inductor 50a, thyristor 57, capacitor 51, inductor 50b and thyristor 47, back to source E.sub.c. The maximum charge on capacitor 51 is 2E.sub.c. Capacitor 51 is discharged by feeding the energy stored back to the source E.sub.c through the path source E.sub.c, diode 49, inductor 50b, capacitor 51, diode 44 and diode 52. The voltage drop across diode 44 reverse biases thyristors 41 and 57 turning them both off. The process for commutating thyristor 42 is similar to that described above with respect to thyristor 41, with thyristors 46 and 58 being triggered to initiate the commutation.

The inverter circuit in accordance with the present invention finds particular advantage for use as a pulse width modulation inverter whether it be a single level or a multi-level inverters. Referring to FIG. 3, when an inverter operates with a PWM control, supplying an inductive load, the output current normally does not reverse every time a thyristor is commutated but free-wheels through a corresponding diode as seen in FIG. 6. With repeated triggering of thyristor 11, during a positive half-cycle, the current free-wheels through diode 15, and thyristor 12 starts conducting only at wt=.pi.. The circuit in accordance with the present invention does not need extra commutations during a PWM operation, since, with zero voltage across the capacitor 20, the circuit is always ready for the commutation of any thyristor at any time.

Further, the present commutation circuit gives the flexibility of programming any commutation sequence desired and, therefore, it is suitable for multi-level pulse width modulation. The application of this circuit to multi-level PWM is described in the publication "Generalized Structure of a Multilevel PWM Inverter"--P. Bhagwat and V. R. Stefanovic, IEEE--IAS Conference, Cincinnati, Ohio, U.S.A.--Sept. 28 to Oct. 3, 1980, which is hereby incorporated by reference.

Many modifications in the above described embodiments of the invention can be carried out without departing from the scope thereof and, therefore the scope of the present invention is intended to be limited only by the appended claims.