Temperature Compensated Circuit

1. Field of the Invention

The present invention relates to temperature compensated circuits and more particularly to temperature compensated, peak detector circuits.

2. Description of the Prior Art

Temperature compensation circuits often involve the use of a negative-temperature coefficient reverse-biased Zener diode in series with positive-temperature coefficient forward biased diodes. This common approach lacks precision of control.

Another prior art approach to temperature compensation is revealed in U.S. Pat. No. 4,101,841, entitled "Gain Control Circuit", issued July 18, 1978. In that prior art device, a circuit having a temperature dependence opposite to that of the gain control section is used to cancel the temperature dependence of the gain control section. This approach requires complex circuit matching to achieve precise stability.

In one type of prior art device for temperature compensation, typified in U.S. Pat. No. 3,392,342, entitled "Transistor Amplifier With Gain Stability", issued July 9, 1968, matched transistors having their base and collector electrodes connected are connected directly across the base-emitter junctions of one or more matched transistor amplifiers to provide gain stability. This approach involves the use of a current translator to impose one base-emitter voltage on another base-emitter for the purpose of maintaining stability of current gain. Although current gain stability is achieved in the face of temperature change, the collector currents of the input and amplifier transistors are only approximately equal, and, therefore, the device does not produce a value of output voltage equal to the peak value of input voltage, as is desirable in peak detector circuits.

Accordingly it is an object of the present invention to provide a new and improved peak detector circuit.

It is a further object to provide a new and improved peak detector circuit wherein the peak voltage of the signal input is translated from the base-collector of a first diode connected transistor through the base of a second matched transistor so that it appears at the emitter of the second transistor regardless of changes in ambient temperature.

These and other objects of this invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims and drawings.

In order to attain the above-mentioned objects, the present invention comprises a temperature compensated, peak detector circuit. The base-collector junction of a diode connected transistor is connected to the base of a second transistor which is matched to the first transistor or fabricated on the same semiconductor chip. The emitters of the two matched transistors are maintained at equal voltages because appropriate resistances are used to set the collector currents of the two transistors at essentially equal levels. An averaging circuit is interposed between the two transistors. When a signal enters the first transistor the peak excursion is clamped, the signal is then averaged, and it finally appears at the emitter of the second transistor at its peak voltage regardless of changes in the ambient temperature.

Among the advantages of the present invention over the prior art are simplicity, improved tracking performance over temperature, and gain isolation of the second transistor.

The drawing is a schematic diagram of a device embodying the present invention.

In a preferred embodiment of the peak detector circuit, as illustrated in the drawing, the signal enters at input 28 and is passed through coaxial cable 30, the center conductor of which is connected to ground through resistor R1. The signal is coupled by capacitor C1 to the base of transistor Q1.sub.A. The base and collector electrodes of transistor Q1.sub.A are connected, and the base-collector junction thus formed is connected to a source of potential 32 through resistor R3 and to the base of transistor Q1.sub.B through resistor R4. Transistors Q1.sub.A and Q1.sub.B may be matched or fabricated on the same semiconductor chip. Capacitor C3 is connected between the base of transistor Q1.sub.B and ground. The collector of transistor Q1.sub.B is connected to source of potential 32 and its emitter is connected to ground through resistor R10. Although a preferred embodiment employing NPN transistors is described in this specification, it will be understood by those skilled in the art that PNP transistors could be employed if obvious design adjustments are made.

The emitter of transistor Q1.sub.A is connected to a source of potential 32 through resistor R2 and to ground through capacitor C2. In parallel with capacitor C2 are Zener diode 34, and potentiometer R5 and resistor R6 in series. The wiper of potentiometer R5 is connected to input 38 of gain control circuit 40 through resistor R9. The emitter of transistor Q1.sub.B is connected to second input 36 of gain control circuit 40 through resistor R7. The feedback from gain control circuit 40 is also fed into second input 36.

Gain control circuit 40 as shown in the drawing comprises a differential amplifier 42. Output 44 of differential amplifier 42, which serves as the output of gain control circuit 40 is fed back to input 36 through resistor R11. In the exemplary device, as shown in the drawing, differential amplifier 42 is an operational amplifier. Other methods of gain control could be devised by those skilled in the art and are intended to come within the scope of this invention, as claimed.

In operation, an input signal is applied to input terminal 28 and passes through capacitor C1. The emitter of transistor Q1.sub.A is set at a level of positive voltage determined by the action of Zener diode 34. Capacitor C2 acts to smooth out fluctuations in the emitter voltage of transistor Q1A. Due to diode clamping action, the peak positive excursion of the input signal is clamped at a value above the emitter voltage of transistor Q1.sub.A. A signal passing through transistor Q1.sub.A is averaged by the circuit comprising resistor R4 and capacitor C3, with the value of capacitor C3 being selected for passing high frequency components of the signal to ground. It will be understood that other types of averaging circuits could be devised by those skilled in the art without affecting the essential features and function of the present invention. Transistors Q1.sub.A and Q1.sub.B are a matched pair; the base-emitter voltage drops in each case are equal if the collector currents are held equal. Therefore, the peak positive excursion of the input signal above the emitter of Q1.sub.A should equal the base-emitter voltage drop of the emitter follower transistor Q1.sub.B if the collector current of transistor Q1.sub.A is equal to the collector current of transistor Q1.sub.B.

The collector current of transistor Q1.sub.A is set by R.sub.3 and V.sub.R3, the voltage across R3. The collector current of transistor Q1.sub.B is set by R.sub.10, V.sub.R10 (the voltage drop across R10), R.sub.7 and V.sub.R7 (the voltage drop across R7). At the balance point of gain control circuit 40 there is essentially no current through R.sub.7 because the wiper voltage of potentiometer R5 and the emitter voltage of Q1.sub.B will be identical. Therefore, the collector current of transistor Q1.sub.B will be set by resistor R10. The values of resistors R3 and R10 can be chosen to set the average collector current of transistor Q1.sub.B essentially equal to the average collector current of transistor Q1.sub.A. This means that the peak voltage of the signal input will appear at the emitter of Q1.sub.B regardless of changes in ambient temperature.

For example, a device has been constructed with values for components as indicated in the drawing. The peak positive excursion of the signal is clamped at approximately +0.65 V above the emitter of transistor Q1.sub.A by the base-emitter voltage drop. The emitter of Q1.sub.A is set by Zener diode 34 at +6.2 V DC. The collector current of transistor Q1.sub.A is set by R3 and V.sub.R3 (V.sub.R3 =10 V-0.65 V-6.2 V=3.15 V, R3=10K; 3.15/10K=I.sub.R3 =315 .mu.A). Because transistor Q1.sub.B is an emitter follower matched to transistor Q1.sub.A, the voltage appearing at its emitter is approximately 0.65 V down from its base voltage. The collector current of transistor Q1.sub.B is set by R10, V.sub.R10, R7 and V.sub.R7 (V.sub.R10 =6.2 V, R10=20K; 6.2/20K=I.sub.R10 =310 .mu.A). At the balance point of the control voltage network, the center wiper voltage of potentiometer R8 will equal the emitter voltage of transistor Q1.sub.B so that no current will flow through R7 (I.sub.R7 =0). Therefore, 310 .mu.A of current flows through the collector of transistor Q1.sub.B, an amount nearly equal to the 315 .mu.a flow in the collector of Q1.sub.A. Under these conditions the peak voltage of the signal will appear at the emitter of transistor Q1.sub.B regardless of ambient temperature changes. For example, a 0.2 V peak to peak signal will generate a DC voltage at the emitter of transistor Q1.sub.B of +6.1 V DC (+6.2 V-0.1 V). For a desired peak signal of 0.1 V, the wiper of potentiometer R5 would be set to +6.1 V DC.

While the present invention has been described in terms of a preferred embodiment, further modifications and improvements will occur to those skilled in the art. I desire it to be understood, therefore, that this invention is not limited to the particular form shown, and I intend in the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.