High Conductivity Metallization for Semiconductor Integrated Circuits

This invention relates to semiconductor integrated circuits, and more particularly to methods for metallizing them.

A semiconductor integrated circuit typically includes metallized interconnection electrodes in a pattern which overlies regions of both relatively thick and thin insulating layers. Typically a thick insulating layer region comprises a relatively thick layer of silicon dioxide, called "field oxide," located on a major planar surface of the silicon body in which the circuit is integrated; whereas a thin insulating layer region typically comprises a relatively thin silicon dioxide layer, called "gate oxide," located on the same major planar surface of the silicon body in regions complementary to the thick insulating layer regions (field oxide regions). Insulated gate field effect transistors are located in these regions of gate oxide. At the boundary between the thick and thin insulating regions a step is formed having an oxide sidewall surface (stemming from the field oxide) over which the metallized interconnection electrode must go.

A typical such situation, somewhat simplified for purposes of clarity only, is illustrated in FIG. 1. (The broken lines 4--4 and 5--5 are useful in defining typical cross sections.) Here a top view in perspective shows a monocrystalline silicon body 10; a thin central gate oxide layer 11; a thick oxide layer having a left-hand field oxide portion 12 and a right-hand field oxide portion 13; a first step 14 located at the boundary of the left-hand field oxide portion 13 with the gate oxide layer 11; a second step 15 located at the boundary of the gate oxide 11 with the right-hand portion 13; a first electrode 17 running along a path extending from the left-hand field oxide portion 12 to a termination at a point overlying the central gate oxide layer 11; and a second electrode 16 running along a path extending from the left-hand field oxide 12 to the right-hand field oxide 15. Thus the first electrode 16 crosses over both steps 14 and 15, whereas the second electrode 17 crosses over only the first step 14, for illustrative purposes only. For illustrative purposes, the first electrode 16 can be a gate electrode metallization which interconnects in two directions, and the second electrode 17 can be a gate electrode which interconnects in but one direction.

When these electrodes 16 and 17 are fabricated by conventional deposition of metal silicide on polycrystalline silicon followed by selective masking and etching, there is an undesirable tendency for the electrodes 16 and 17 to be joined (shorted) together by a residual metal strip running along the bottom of the sidewall of the step, because of the tendency of the etching not te remove completely some portions of the electrodes at the step. It would therefore be desirable to have a method for fabricating interconnection which avoids this problem.

This invention involves a method for simultaneously patterning--over relative thick field insulating regions, relatively thin gate insulating regions, and sidewall insulating regions at step boundaries therebetween--metal silicide metallization electrodes for semiconductor integrated circuits including the steps of: (1) forming an unpatterned polysilicon layer on said field, gate, and sidewall insulating regions, (2) forming a patterned resist layer on the polysilicon layer, (3) depositing the metal silicide over on said photoresist layer and on exposed portions of all the insulating regions, (4) removing the patterned resist layer to lift off the metal silicide thereon, and (5) oxidizing exposed portions of polysilicon to form silicon dioxide. In this manner, the metal silicide metallization is patterned, without substantial danger of short-circuits, simultaneously on both the thick insulating and thin insulating regions as well as on the sidewalls of steps at the boundaries therebetween.

This invention may be better understood from the following detailed description when read in conjunction with the drawing in which:

FIG. 1 is a top view in perspective of a semiconductor integrated circuit portion in order to illustrate the problem of the prior art;

FIGS. 2-5 illustrate in cross sections various stages of fabrication of a semiconductor integrated circuit in accordance with a specific embodiment of the invention;

FIGS. 6-7 illustrate a cross section a later stage of fabrication of a semiconductor integrated circuit in accordance with another specific embodiment of the invention; and

FIG. 8 illustrates in cross section a later stage of fabrication of a semiconductor integrated circuit in accordance with yet another specific embodiment of the invention.

Only for the sake of clarity, none of the Figures is to any scale.

FIGS. 4 and 5 show the cross sections 4--4 and 5--5, respectively, of the structure to be fabricated (FIG. 1); whereas

FIGS. 2 and 3 show the corresponding cross sections thereof, respectively, in an early stage of fabrication of the gate electrodes 16 and 17, according to a specific embodiment of the invention. Many similar such electrodes are to be formed, as gate electrode to different transistors of the insulated gate type. Here, in FIGS. 2 and 3, the top major surface 10.5 of the silicon body 10 is coated with the left-hand field oxide layer 12, gate oxide layer 11, and right-hand field oxide layer 13. The field oxide layers are typically in the approximate range of 2000 to 7000 A thick, illustratively about 3500 A thick; the gate oxide layer, typically in the approximate range of 70 to 500 A thick, illustratively about 250 A thick. A layer 21 of polycrystalline silicon (polysilicon), typically about 500 A thick, is deposited all over these oxide layers, as by conventional chemical vapor deposition or plasma deposition. Because of the conformal (good step-coverage) property of polysilicon, the thickness of this polysilicon layer 21 is substantially uniform. A conventional resist layer 22 is formed, in a pattern corresponding to the desired ultimate metallization pattern, on the exposed surface of the polysilicon layer 21. This layer 22 is typically a photoresist layer, as known in the art. More specifically, this photoresist layer 21 is formed in a pattern over both field and gate oxides corresponding to the complement of the desired metallization pattern.

Then tantalum disilicide is formed as a silicide layer 23, for metallization purposes, over the exposed portions of the polysilicon layer 21; and also a tantalum disilicide layer 24 is simultaneously formed on the exposed top surface of the photoresist layer 22. For example, the silicide layer 23 can be formed by deposition by sputtering tantalum and silicon by conventional techniques, typically to a thickness in the approximate range of 1000 to 4000 A, illustratively about 2500 A. This sputtering can be performed with a single target of tantalum silicide or with separate targets (cosputtering) of tantalum and silicon.

Next the photoresist layer 22 is removed, as by a conventional etching solution, thereby lifting off the tantalum disilicide layer 24 but leaving intact the tantalum disilicide layer 23 on the polysilicon layer 21.

Then a conventional dry thermal oxidation treatment, typically at about 900.degree. C. for about 30 minutes in oxygen ambient, oxidizes the exposed portion of the polysilicon layer to silicon dioxide (but does not appreciably oxidize the metal silicide), thereby bringing the structure being fabricated into the condition illustrated in FIGS. 4 and 5, representing the same cross sections as FIGS. 2 and 3, respectively. Here the polysilicon layer will be characterized by sloping edges, that is, a recessed structure of greater width at the bottom of the polysilicon layer than at the top, owing to the isotropic tendency of the oxidation process in polysilicon. Here also (FIGS. 4 and 5), field oxide layers 32 and 33 are thickened at their respective edges, due to the oxidation of polysilicon into silicon dioxide; and the remaining polysilicon forms a polysilicon layer 31 of consequently smaller lateral extent overlaid everywhere by the tantalum silicide layer 23. The polysilicon layer 31 plus the tantalum silicide layer 23 form the desired electrodes 16 and 17 (FIG. 1).

Because of the thermal oxidation of the exposed polysilicon, there is little danger of shorts between other similar gate electrodes and their interconnections, especially those proximate to electrodes 16 and 17, which are all simultaneously formed by remaining portions of the polysilicon layer (not shown) overlaid by the tantalum silicide layer.

As an added alternative, the polysilicon layer 21 (FIGS. 2 and 3) can be doped, preferably when being deposited (in situ doping) with donor impurities (in silicon) such as phosphorus. Accordingly, those (top) portions of the silicon dioxide layers 32, 33, 34, and 35 which grew out of the polysilicon will be doped oxide. In such a case, the structure being fabricated, in the condition shown in FIGS. 4 and 5, can be subjected to treatment with an etching solution which preferentially attacks the doped oxide more rapidly (typically by a factor of 2) than the undoped oxide. For example, a solution of buffered HF (30 parts by volume NH.sub.4 F, 1 part HF) which preferentially attacks phosphorus doped oxide can be used for this purpose. Accordingly the structure being fabricated is brought into the condition illustrated in FIGS. 6 and 7 in which the phosphorus-doped portions of silicon dioxide have been removed, thereby bringing the remaining silicon dioxide layer 11,12,13 more nearly in the configuration as originally deposited (before the added silicon dioxide stemming from oxidation of the polysilicon layer 21).

The structure shown in FIGS. 6 and 7 can also be achieved without doping the polysilicon. For example, instead of using solution etching with buffered HF, etching of the top portions of the silicon dioxide layers 32, 33, 34, and 35 to the extent necessary to bring the structure into the condition shown in FIGS. 6 and 7 can be achieved by reactive sputter etching with CHF.sub.3.

The electrode structure formed by the combined polysilicon layer 31 and tantalum silicide layer 23 overlying gate oxide regions, as shown in FIG. 7, is characterized by a sloping sidewall of the polysilicon layer 31; that is, the width of the polysilicon layer 31 at its interface with the underlying gate oxide layer 11 is greater than its width at its interface with the overlying tantalum silicide layer 23. Accordingly, the edge of the polysilicon layer 31 can be advantageously used as a protective mask for defining the self-aligned edge of a source zone 41 and a drain zone 42 by subsequent conventional impurity introduction into the underlying silicon body 10 followed by thermal diffusion of the impurity therein.

By previously oxidizing the polysilicon layer 21 for a time longer than required to convert some of its regions not underlying the silicide into silicon dioxide, the resulting polysilicon layer 31 will have a recess (FIG. 8) cut into it by the extra time of oxidation. In this manner, as indicated in FIG. 8, the silicide layer 23 will overhang the resulting polysilicon layer 31, so that the edge of the metal silicide layer 23 serves as a selfalignment protective mask against introduction of impurities. Thus, by controlling a subsequent thermal diffusion time for the impurities, the edges of the source and drain zones 41 and 42 can be made more nearly aligned with the edges of the polysilicon layer 31, as is desired for reducing overlap capacitance.

Another advantageous feature of the resulting gate electrode is that the combined overall height of the electrode can be lower (because of the lower electrical resistivity of metal silicide than of polysilicon) than in other procedures using thicker polysilicon layers for reduced electrical resistance; thereby, further reduction of undesired mutual parasitic capacitance of neighboring electrode edge surfaces can be achieved.

Although the invention has been described in detail with respect to specific embodiments, various modifications can be made without departing from the scope of the invention. For example, instead of tantalum, other silicide-forming metals can be used, such as cobalt, or titanium. The resist layer 21 can also be an electron beam resist or an X-ray resist layer, as known in the art. Finally the electrode metallization technique of this invention can similarly be used for metallizing gate, source, or drain of Schottky barrier gate, source, or drain transistors.