Programmable Counter Circuit

1. Field of the Invention

The present invention relates to a programmable counter circuit which has its operable frequency improved.

2. Description of the Prior Art

A programmable counter which operates as an N-step counter having a variable frequency dividing ratio N, is composed of a counter circuit comprising a multistage connection of flip-flops and a loading circuit for inputting an initial value (N) into the counter circuit. FIG. 1 shows an example of a conventional programmable counter circuit indicated generally by CNT, in which a plurality of stages of flip-flops P.sub.D1, P.sub.D2, . . . are cascade-connected. The flip-flop P.sub.D1 of the first stage is supplied with a clock signal F.sub.IN. The flip-flops P.sub.D2, P.sub.D3, . . . of the following stages are each supplied with the output from the immediately preceding stage and bits DL.sub.1, DL.sub.2, DL.sub.3, . . . forming initial values are respectively loaded into the respective flip-flops of the individual stages. The bits DL.sub.1, DL.sub.2, DL.sub.3, . . . are bits of binary numbers and representing the numeric values of the first, second, fourth, eighth, . . . digits in sequential order. For loading the initial values DL.sub.1, DL.sub.2, . . . in the counter circuit CNT, the numeric values of the bits DL.sub.1, DL.sub.2, . . . are first determined by setting digital switches or latch circuits and then a load signal LOAD is applied to a common line L.sub.1, by which the numeric values DL.sub.1, DL.sub.2, . . . are respectively loaded into the flip-flops P.sub.D1, P.sub.D2, . . . . The clock counting of the flip-flops is down-counting. Assuming, for example, that the initial values DL.sub.1, DL.sub.2, . . . are "000100 . . . ",that is "8" in the decimal notation, an "8" count is counted by loading 8 into the counter and counting down to 7, 6, . . . by the down-counting of the clock signal F.sub.IN and when the count value reaches "0", "8" has been counted by the counter; thus, in this case, the counter serves as an 8-step counter. By setting the initial value to "20" with the bits DL.sub.1, DL.sub.2, . . . set to "0010100 . . . " and performing the counting as mentioned above, the counter functions as a 20-step counter. In this way, a desired counter can be formed.

Basically a load signal generator may be one that generates the load signal LOAD when the count value of the counter circuit CNT becomes zero. When the counter circuit CNT is counted down to "0" and it is detected by a gate circuit that outputs Q.sub.1, Q.sub.2, Q.sub.3, . . . Q.sub.12 of the flip-flops P.sub.D1, P.sub.D2, P.sub.D3, . . . P.sub.D12 are all "0", the detected output is directly used as the load signal LOAD. When the initial value bits DL.sub.1, DL.sub.2, . . . are loaded into some of the flip-flops P.sub.D1, P.sub.D2, . . . by the load signal, the above-mentioned condition required for load signal generation is immediately removed. Note, there is a slight time lag in the loading of the bits to the respective flip-flops. Thus, the load signal LOAD disappears, so that the initial values can no longer be loaded into the remaining flip-flops. To improve this above-mentioned system, it is common practice in the art to employ a signal generator LDG such as shown in FIG. 3 which is commonly referred to as an early decoder or look ahead circuit. This look ahead circuit comprises a specific count value detector circuit DET comprising NOR gates NOR.sub.1 to NOR.sub.4 and NAND gates NAND.sub.1 to NAND.sub.4 and a shift register SHR comprising D flip-flops DFF.sub.1 to DFF.sub.3. The detector circuit DET is one in which a Q or Q output from the counter circuit CNT is selectively applied to each gate to derive from NAND gate NAND.sub.4 of the last stage the following output H :

Accordingly, in the detector DET of this example the output H is "0" when Q.sub.1 =Q.sub.2 =Q.sub.4 = . . . =Q.sub.12 =0 and Q.sub.3 =1, that is, when the counter value is "4". The output H =0 is applied as a detection signal of the specific count value "4" to the shift register SHR. The shift register SHR inputs therein the output from the gate NAND.sub.4, using the same clock signal F.sub.IN as the counter circuit CNT, and then after having shifted for three clock signals and, accordingly when the count value of the counter circuit CNT has reached "1", the shift register SHR generates the load signal LOAD. With this system, each flip-flop is initialized by the load signal and even if the output from the NAND gate NAND.sub.4 is made H =1 by the initialization, since it is the shift register SHR that outputs the load signal and since the shift register SHR does not change its state for at least one clock signal, the load signal will not disappear within one clock period; thus, the load signal is produced until the count value "0" is reached.

In such a programmable counter, as its operating frequency is raised, the load circuit cannot keep up with the increase in the operating fequency even though each flip-flop is still operable, presenting the problem that the highest operating frequency is limited. In other words, as the number of stages of flip-flops increases, the load signal line L.sub.1 becomes longer; especially in a MOS circuit, the capacitance of the signal line L.sub.1 increases and rounds the waveform of the load signal transmitted over the signal line L.sub.1, introducing the possibility of an erroneous operation.

The rounding of the waveform can be avoided by applying the load signal to a waveform shaping circuit. The circuit arrangement therefor is shown in FIG. 2. In the illustrated example, a buffer BUF formed by a series connection of two inverters is shown to be inserted between load terminals of every other flip-flop. With such an arrangement, the load signal is applied only to the first stage flip-flop P.sub.D1 and the buffer BUF connected thereto and each of the other buffers drives the flip-flop of the succeeding stage and the buffer connected thereto, so that the load on the load signal generator LDG is greatly alleviated and the rounding of the waveform is removed by each buffer and hence does not become critical. With this arrangement, however, a delay in signal propagation by each buffer is accumulated producing a large delay in the signal propagation of the signal arriving at the terminating flip-flop and, as a result, it is likely that a plurality of load signals occur, making the loading inaccurate. Accordingly, in the circuit of FIG. 2 the highest operating frequency depends on the delay of the load circuit; therefore, an extensive improvement cannot be expected of this circuit though it slightly improves on the circuit of FIG. 1. This will hereinbelow be further described with reference to FIGS. 4 and 5.

FIG. 4 is a waveform diagram depicting the operation of the programmable counter shown in FIG. 2. In FIG. 4, DL.sub.3 =DL.sub.6 =1 and the other bits are "0"; that is, the initial value is "36". Assuming that the level of the output H =0 from the gate NAND.sub.4 is produced upon occurrence of a second clock signal F.sub.IN in FIG. 2, a low-level load signal is generated after the occurrence of three clock signals and the initial values DL.sub.1, DL.sub.2, . . . are loaded into the flip-flops P.sub.D1, P.sub.D2, . . . in a sequential order while being delayed by a signal propagation delay time .tau..sub.1. By the loading of the initial value DL.sub.1, the flip-flop P.sub.D1 is returned to the low level although it is to be high-level, and the NAND gate NAND.sub.4 provides an output H.sub.2 having a low-level other than its original output H.sub.1. The high-level of H is immediately restored by the lowering of the output G down to the low level, as indicated by G.sub.1, so that the loading does not take place twice. Thus, in the case where the initial value is not a certain special value, normal operation is maintained even if the operating frequency is a little high. When loading an initial value such that DL.sub.3 =1 and a high-order bit becomes "1" as indicated by Q.sub.12 in FIG. 5, however, while the loading signal is transmitted to the flip-flop P.sub.D12, "1" is loaded into the flip-flop P.sub.D3 and there can occur the state in which the outputs from the remaining flip-flops are "0". Since this means a count value "4", the NAND gate NAND.sub.4 yields a low-level output H.sub.2 and after three clock signals the shift register SHR produces a load signal LOAD'.

The present invention is directed to a programmable counter circuit which utilizes the merits of the counter circuit of the type having buffers inserted in the load signal line but is free from its problems.

It is an object of the present invention to ensure accurate loading in a programmable counter.

Another object of the present invention is to speed up the counter operation of a programmable counter.

Yet another object of the present invention is to raise the operating frequency of a programmable counter into the vicinity of the operational limit of flip-flops comprising the counter.

Briefly stated, according to the present invention, in a programmable counter circuit, in the loading of an initial value, a load signal is applied from a load signal generator via a buffer to flip-flops of each stage of a counter, which counter serves as an N-step counter dependent on the initial value to be loaded. The load signal generator includes a detector circuit for detecting a specified value which is generated a short time before the initial value loading of the counter circuit. The load signal generator also includes, a shift register which shifts upon reception of the detected output signal from the detector circuit under the control of the same clock signal as that for driving the counter circuit and generates the load signal at the moment of the initial value loading of the counter circuit. The load signal generator further includes a load control circuit which sends out a signal for preventing the application of the output from the detector circuit to the shift register for the duration of the load signal and a certain period of time subsequent thereto.

FIG. 1 is a block diagram showing a conventional programmable counter;

FIG. 2 is a block diagram showing a programmable counter of the type that buffers are inserted in a load signal line.

FIG. 3 is a block diagram illustrating an example of a prior art load signal generator circuit;

FIG. 4 is a waveform diagram explanatory of the operation of the programmable counter of FIG. 1 combined with the circuit of FIG. 3, showing the case in which the number to be loaded is not a certain specific value;

FIG. 5 is a waveform diagram, similar to FIG. 4, showing the case in which data to be loaded is "1" in DL.sub.3 and "1" in a high-order bit (DL.sub.12 in this example);

FIG. 6 is a block diagram illustrating a load signal generator circuit in accordance with an embodiment of the present invention;

FIG. 7 is a waveform diagram explanatory of a programmable counter circuit of the present invention which is a combination of the circuits of FIGS. 2 and 6;

FIG. 8 is a circuit diagram illustrating a specific example of each of D type flip-flops DFF.sub.1 to DFF.sub.3 ;

FIG. 9 is a circuit diagram illustrating a specific example of each of flip-flops P.sub.D1 to P.sub.D13 ; and

FIG. 10 is a circuit diagram illustrating a specific example of a flip-flop P.sub.D14.

FIG. 6 shows the principal part of an embodiment of the present invention, that is, an improved load signal generator circuit LDG. The present invention comprises a programmable counter having a combination of this load signal generator circuit and the counter circuit CNT of FIG. 2. A specific count value detector circuit DET and a shift register SHR in FIG. 6 are the same as those used in FIG. 3 and, in this embodiment, a load control circuit LCT is added. The load control circuit LCT is a dummy counter which is formed by 2-bit flip-flops P.sub.D13 and P.sub.D14. A Q output Q.sub.5 ' of the flip-flop P.sub.D14 is connected to one input of the NAND gate NAND.sub.4 to set a limit to a period during which the detector circuit DET applies the detected output H to the shift register SHR; that is, for the duration of the load signal LOAD and a certain period of time subsequent thereto, the NAND gate NAND.sub.4 is closed in order to hold the output H at the high-level (not by the output G from the preceding stage).

The flip-flop P.sub.D13 of the first stage of the load control circuit LCT is connected to the outputs Q.sub.3 and Q.sub.3 of the flip-flop P.sub.D3 of the counter circuit CNT of FIG. 2. The flip-flop P.sub.D13 is identical in construction with the flip-flops P.sub.D1, P.sub.D2, . . . of the counter circuit CNT and inverts its output upon each application of the clock signal. The flip-flop P.sub.D14 at the output stage has its input circuit specially arranged and, when loaded with an initial value, produces an output "1" and inverts the output to "0" upon application of one clock signal pulse, thereafter retaining the output "0". Reference character V.sub.DD indicates a power supply for loading an initial value "1" in the flip-flops P.sub.D13 and P.sub.D14. The timing of loading the initial value is the timing of the load signal LOAD for the flip-flop P.sub.D14 and the timing of the LD.sub.1 for the flip-flop P.sub.D13, however this may also be the timing of a further signal as LD.sub.2. With such an arrangement, as shown by the waveform diagrams of FIG. 7 (which shows an example of loading "1" in Q.sub.3 and Q.sub.12 as is the case with FIG. 5), when the load signal LOAD becomes "0", the outputs Q.sub.5 ' and Q.sub.5 ' immediately become "1" and "0", respectively. This closes the NAND gate NAND.sub.4 from the moment of generation of the load signal LOAD, preventing the application of a low-level signal from the NAND gate NAND.sub.4 to the shift register SHR. A period LDI during which the output Q.sub.5 ' is "1" is a load signal inhibit period. Next, at the time of the low level of LD.sub.1 the flip-flop P.sub.D13 is loaded with "1" and this state is retained until the outputs Q.sub.3 and Q.sub.3 from the flip-flop P.sub.D3 of the counter CNT vary. When the outputs Q.sub.3 and Q.sub.3 serving as clock signals vary, the flip-flop P.sub.D13 is inverted to render its output Q.sub.4 ' the low-level and Q.sub.4 ' the high-level. Accordingly, the flip-flop P.sub.D14 is inverted by the next clock signal making its output Q.sub.5 ' the high-level in order to open the NAND gate NAND.sub.4, deriving therefrom an output which is dependent on its inputs G and Q.sub.1. In this way, in the present circuit the output from the NAND gate NAND.sub.4 is made the high-level forcibly for a certain period of time in order to inhibit the generation of a second load signal. The period of inhibition may be a period lasting until the output from the NAND gate NAND.sub.4 is made the high-level by the bit "1" of the initial value to be loaded and this period need not be very long. Accordingly, the clock signal for the flip-flop P.sub.D13 can be derived from the output of a flip-flop of a stage preceding P.sub.D3 of the counter. When this clock signal is obtained from the flip-flop of a stage near the last stage of the counter, the value N of the N-step counter cannot be allowed to be small. For example, when the outputs Q.sub.3 and Q.sub.3 are used as described above, if the counter circuit has a 12-bit configuration, the frequency dividing ratio is within the range of 16 to 4095; similarly, if the outputs Q.sub.4 and Q.sub.4 are used, the frequency dividing ratio ranges from 32 to 4095. The clock signal for the flip-flop P.sub.D13 is selected, taking this into account. This is also related to the number of stages of the load control circuit; that is, the application of the outputs Q.sub.3 and Q.sub.3 to a first one of the two stages of flip-flops of the load control circuit LOT is equivalent to the application of the outputs Q.sub.4 and Q.sub.4 to the second stage of the two stages of flip-flops.

FIG. 8 illustrates a specific circuit arrangement for each of the D flip-flops DFF.sub.1 to DFF.sub.3 ; FIG. 9 illustrates a specific circuit arrangement for each of the flip-flops P.sub.D1 to P.sub.D13 ; and FIG. 10 illustrates a specific circuit arrangement for the flip-flop P.sub.D14. Since they are known circuit arrangements which comprises C-MOS inverters and transfer gates, no detailed description will be given. Each of the flip-flops P.sub.D1 to P.sub.D13 feeds back its output Q.sub.n to an invert input terminal, so that it inverts its state upon each application of a clock signal CK.sub.N. In contrast thereto, since the flip-flop P.sub.D14 does not have such a feedback route and has one of its inputs connected to a high potential power supply V.sub.DD and the other input connected to a low potential power supply V.sub.SS, it yields an output "1" upon loading an initial value and produces an output "0" upon application of a clock signal and thereafter retains the output "0" no matter how many clock signals are applied.

It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.