Digital Subscriber Communication System

This invention relates to a distributed, broadband cable sending and receiving system wherein a single transmission medium is used to carry voice and data information between a central office location and multiple subscriber locations.

It is well known in the art that cable television systes using coaxial cable, and telephone systems using twisted pair cable, as the transmission mediums, are capable of delivering voice and data services by means of analog or digital carrier systems, or by the use of modems. Existing digital systems are primarily used to carry a large number of multiplexed voice circuits from one point to another. The purpose of the present invention is to distribute both voice and data information.

Existing distributed digital systems using multiplexed digital baseband transmission have a cost disadvantage relative to the present invention because the higher bit rates necessary to service each subscriber location require more expensive circuit components and require more complex framing and demultiplexing tasks to be performed at each subscriber location.

Existing analog carrier systems have a greater susceptibility to noise and beat-frequency interference than digital systems and are not designed to provide both voice service and high speed data services without additional subcarriers or modems. Existing analog, distributed carrier systems also generally use a separate set of allocated frequencies for each subscriber, making it necessary to use greater bandwidth on the transmission medium relative to the present invention due to the necessity of having spectrum dedicated to subscribers when they are not sending or receiving information.

Existing data modems can be used to transmit and receive both voice and data services but are not currently cost-effective since their polling, addressing or contention formats are optimized for data transmission. And existing systems do not use a combination voice and data format to provide a uniform voice sampling rate with low bit overhead.

The preferred embodiment of the invention utilizes an optimum bit format and frequency synthesized, FDM, concentrated transmission in order to provide a combination of voice and data services in the most efficient and cost-effective manner. The advantages of the present invention over existing carrier systems and data modems are achieved with use of an optimized sixteen bit digital format; the use of an encoded framing bit in each frame indicating phasing criteria for a master synchronization signal having positive and negative transitions that define the beginning, mid-point and end of each frame; the use of an optimized method of detecting the framing bit and distinguishing it from all other bits in the frame; the use of frequency synthesized receivers and transmitters in order to serve more subscribers than the number of available FDM channels; and, the use of a common control signal, with a binary addressing scheme, to continuously manage the frequency allocations of each individual subscriber terminal and transmit data information to the subscriber terminals.

Frequency synthesized transmitters and receivers are widely used in communications systems where switching from one FDM channel to another is a desirable feature. The present invention, however, combines this feature with the novel and uniquely optimized features in order to provide an optimized system uniquely designed to deliver digitized voice and data services in a distributed digital subscriber communications system at a minimum cost. One preferred embodiment places sixty-four FDM channels within a pair of twelve megahertz frequency bands, one for each direction of transmission. A common control signal is added to one direction of transmission. There are two hundred fifty-six subscribers served by the system giving a ratio of four subscribers per available channel. Each subscriber has access by use of a frequency synthesized receiver and transmitter to any one of the 64 two-way FDM channels. The system is considered cost optimized because all subscriber terminals are identical and can be mass-produced; the common control signal has the capacity for future additional data handling capabilities; and, the amount of spectrum used per subscriber is minimized due to the concentrator function of the system.

Another embodiment of the invention does not use the control signal and each of sixty-four subscribers are, with switches, dedicated to a specific channel for voice and data transmissions.

Another embodiment of the invention uses only the control signal and only one of up to two hundred fifty-six subscribers can transmit data at a time.

To practice the invention all data transmissions use a sixteen bit format per frame, which optimizes the design and operation of the communication system for several technical reasons which will be discussed in more detail below. Each sixteen bit frame of information contains a framing bit which is detected and used to properly phase an eight kilohertz master synchronization (MSI) signal with respect to the received digital signal. The framing bit is unique and distinguishable from other bits in the frame because it carries an alternating logic "1", logic "0" pattern. In the present invention it can be placed at the beginning, mid-point or at the end of each frame.

In the preferred embodiment the framing bit is the bit preceding each digitized voice transmission. The use of a framing bit in each frame allows all frames to be identical in structure and provides superior frame-up characteristics with respect to other known methods. It cannot be over emphasized how important the frame-up characteristic is in a concentrated system where receivers are constantly being switched from one received channel to another. Other known carrier systems, that use framing circuitry, frame-up only occasionally. The alternating pattern is not new but commonly used in the art. The method used to detect this pattern and its frequency of use is, however, new and novel.

The frame bit detection begins with a random selection of a bit within the received frame. A number of tests are made to determine if this bit violates the alternating code. A feature of the present invention is the testing procedure.

The received, selected bit logic levels are used to toggle a flip-flop. The flip-flop output will first go to logic "1" with the first received logic "1" signal; and will remain at logic "1" after the receipt of a logic "0" during the next frame (but would switch to logic "0" if two logic "1"'s are received in succession). Assuming the receipt of a valid alternating framing bit signal, the flip-flop check signal output, termed CK signal, will remain logic "1" for two frames. The third frame's logic "1" will cause the CK signal to change to logic "0". The fourth frame's logic "0" will cause this logic "0" state to continue until a logic "1" is received in the fifth frame. The result is a squarewave signal, CK, having a frequency of one-half the frame rate; i.e., four kilohertz, and having characteristics that are easily tested by a circuit which uses inexpensive and readily available digital circuit elements.

For purposes of discussion, one complete cycle of the above described four kilohertz, CK, squarewave signal can be considered to be divided into eight check-points equally spaced and coincident with the positive and negative transitions of a sixteen kilohertz signal. For example, check-point four falls at the CK signal negative transition, at the mid-point of the cycle, and check-point eight falls at the positive transition of the next cycle and, therefore, check-point eight of one cycle is check-point 0 of the next.

The first test is a check for repetitive zeros. If repetitive zeros are detected, an error signal indicating repetitive zeros is generated. The second test is to check the logic level of the CK signal at check-point three. If a logic "0" is detected an error signal indicating check-point three "0" is generated. The third test is to check the CK signal logic state at check-point five. If a logic "1" is detected an error signal indicating check-point five "1" is generated. The final test of the cycle is to check the CK signal logic level at check-point seven. If a logic "1"is detected an error signal indicating check-point seven "1" is generated.

These four error signals are combined. Any error signal, during any CK signal cycle, causes the framing circuit to reset and select another bit, within the frame, to test for framing bit validity. This process is repeated until the proper framing bit is selected. As in other existing digital systems, the bits carrying information are restricted from indicating an alternating logic "1", logic "0" pattern.

Testing the toggled CK signal logic levels for validity is an all-digital method eliminating the practical, empirical problems associated with so-called direct signal technique or other known techniques. Direct tests for validity are often implemented with fewer components but are subject to "sliver errors" and error spikes at frame transition points in some conditions of operation temperature changes and changes in risetimes due to humidity or aging.

A second method of detecting the framing bit, and distinguishing it from all other bits in the frame, is also disclosed. The second method is not on all-digital method, as is the preferred method discussed above, but is a direct signal method with the novel addition of certain analog time constants to minimize error spikes at signal transition points .

These and other advantages, features and objectives of this invention and the manner of attaining them will become more apparent and the invention itself will best be understood by reference to the following description of the embodiments of the invention in conjunction with the accompanying drawings.

FIG. 1 is a diagrammatic representation of the preferred sixteen-bit format at hypothetical digital signal levels and some of the various signals generated by the circuitry used in practicing the preferred embodiment of this invention.

FIG. 2 is a schematic diagram representation of the preferred method of generating the signals necessary to detect the framing bit; and, distinguish it from all other bits in the frame.

FIG. 3 is a schematic diagram representation of the preferred method of detecting repetitive zeros with the CK signal in order to determine an invalid framing bit selection.

FIG. 4 is a schematic diagram representation of the preferred method of testing the CK signal for determining an invalid framing bit selection.

FIG. 5 is a schematic diagram representation of the preferred method of combining the error signals of FIG. 4 and having any error signal cause the framing circuit to reset and select another bit, within the frame, to test for framing bit validity.

FIG. 6 is a schematic diagram representation of the second method of detecting the framing bit; and, distinguishing it from all other bits in the frame.

FIG. 7 is a diagrammatic representation of the preferred central office terminal configuration.

FIG. 8 is a diagrammatic representation of the referred subscriber terminal configuration.

The preferred embodiment of the invention as disclosed comprises a digital subscriber communications system wherein a plurality of two-directional, time-division multiplexed signals, each having a series of frames and a predetermined number of binary digits per frame, are frequency-division multiplexed (FDM) within a pair of given frequency bands, one for each direction of transmission, onto a single broadband cable for transmission of voice and data services between a central office location and multiple subscriber locations.

While cable transmission is disclosed as a preferred embodiment, those skilled in the art will recognize that the invention can be used on any suitable transmission medium such as twisted pair cable or fiber optics with fibers in each direction of transmission.

Three signal transmissions are employed in the preferred embodiment of the invention, each having the sixteen bit format to be discussed in detail below. However, each transmission can be advantageously used separately until the demand on the communications system is such that the preferred embodiment is put into use.

The preferred embodiment employs two transmissions from the central office terminal to the subscriber, each signal having sixteen bits, 1-16, per frame, 28, at a rate of one hundred twenty-eight kilobits per second. A first control signal is received by all subscribers with each frame, 28, containing eight bits, 1-8, to address a particular subscriber; an FDM channel assignment for the addressed subscriber, a framing bit, 16, and other data bits, 9-15, for the addressed subscriber. The central office also preferably transmits to the addressed subscriber a second transmission on the assigned channel also having sixteen bits, 1-16, per frame, 28, at a rate of one hundred twenty-eight kilobits per second with each frame, 28, containing eight digitized voice bits, 1-8, a framing bit, 16, and other data transmissions, 9-15.

The addressed subscriber terminal transmits back to the central office on the assigned channel on the other frequency band a return signal having sixteen bits 1-16, per frame, 28, at a rate of one hundred twenty-eight kilobits per second, with a voice and data format similar to the above.

The preferred embodiment can be used to service two hundred fifty-six subscribers with sixty-four FDM channels within a pair of twelve megahertz frequency bands, one for each direction of transmission.

In the situation where the per subscriber cost must be minimized or a maximum of sixty-four subscribers are to be served there is a cost advantage in deactivating the common control signal and replacing the common control signal circuitry, at each subscriber location, with a module having miniature switches used to select a different binary number at each subscriber location thus placing each subscriber on a dedicated channel. The control logic at the central office is also removed, in this configuration, for cost savings.

In the situation where a CATV company provides only data services, with no present voice requirements, the system is greatly cost-reduced by eliminating all FDM transmission channels to the subscriber except the common control channel, which addresses up to two hundred fifty-six subscribers, sending seven bits of data per frame, 28. During the interval of time a subscriber is receiving information his transmitter is enabled to transmit on the one return channel, a channel shared by all subscriber terminal transmitters. This provides a very cost effective two-way data service for CATV subscribers, in multiples of two hundred fifty-six subscribers per system, which conserves bandwidth in its initial stages and also is expandable at a later time to full voice and data capability.

The transmission of information between the central office terminal and the subscriber terminal and between the subscriber terminal and the central office terminal by use of AM-DSB or other radio frequency modulation schemes, consists of a series of digital pulses transmitted at a rate of one hundred twenty-eight kilobits per second. The information is transmitted in frames having sixteen bits per frame or, in other words, eight thousand frames per second. Each frame employs a framing bit to phase a master synchronization signal with the frame definition of the received digital signal.

FIG. 1 is a diagrammatic representation of the preferred sixteen bit format at hypothetical digital signal levels. The transmitted signal, 307, is transmitted at a rate of one hundred twenty-eight kilobits per second and is transmitted in frames, 28, having sixteen bits, 1-16, per frame. Consequently, the frames, 28, are transmitted at a rate of eight thousand frames, 28, per second. The bit, 1-16, locations within each frame, 28, are designated in FIG. 1 by the base line notations.

From the transmitted digital signal, 307, a clock signal, 301, is regenerated of one hundred twenty-eight kilohertz which is connected to a divider circuit, 302, for various purposes to be discussed below. One purpose is to phase the Master Synchronization Signal (MSI), 306, shown in FIG. 1. The Master Synchronization Signal, 306, is generated by dividing the received digital signal, 307, regenerated clock signal, 301, by sixteen to create an eight kilohertz signal, 303. The digital signal's, 307, framing bit, 16, is then used to phase the master synchronization signal, 306, with the frame, 28, definition of the received digital signal, 307. This divides the received digital signal, 307, uniquely into two frame halves, 37, 38, of eight bits, 1-8, 9-16, per half, 37, 38, which can conveniently be used for voice transmissions, address transmission, and other data transmission, including the framing bit, 16.

The sixteen bit format per frame, 28, has been selected as the optimum configuration for the digital communications system of the present invention for the following reasons:

In order to efficiently use available digital circuit elements, binary multiple numbers, such as 1, 2, 4, 8, 16, 32 etc., should be used whenever possible. Telephone grade voice codecs require eight bits to be used for the voice service. Therefore, the use of eight bits per frame would require a more complex framing method sinc there would be no dedicated framing bit available, and would require a more expensive supervisory control circuit for European CCITT standard voice transmission since this standard requires supervisory control to be provided separate from the eight voice bits. Additionally, high speed data simultaneous with voice transmission would require a higher frame rate in order to alternate voice and data transmission in some manner which would also be more costly due to the additional overhead bits required to distinguish between voice frames and data frames.

The use of thirty-two bits per frame is an inefficient use of transmission bandwidth and requires added cost in components. A number of bits between eight and sixteen, such as fifteen, would require the same number of digital circuit elements as the use of sixteen bits but would provide less capability and would therefore be less efficient than a sixteen bit format. The use of a number of bits between sixteen and thirty-two such as twenty-four would be just as costly in circuit elements as thirty-two bits but would provide less capability and would therefore be less efficient than the use of either sixteen or thirty-two bits. A sixteen bit format is therefore judged optimum from an efficiency point of view.

The use of a sixteen bit format is also optimum when using the master synchronization signal, 306. As discussed above, the framing bit, 16, is detected and used to properly phase the eight kilohertz master synchronization (MSI) signal, 306, with respect to the received digital signal, 307. The eight kilohertz squarewave MSI signal, 306, is conveniently generated by dividing the recovered one hundred twenty-eight kilohertz clock signal, 301, by sixteen. This uses a single, inexpensive digital circuit element, 302. In one embodiment, the MSI signal, 306, is therefore logic "1" during the time the voice bits, 1-8, are received and logic "0" during the time the data bits, 9-16, are received, or vice versa, depending upon the embodiment. Thus, the demultiplexing of the voice and data information is simple and cost-effective. Other known formats are more complex and wasteful of bit overhead.

The use of a sixteen-bit format is optimum from a transmission circuit element point of view, also. An important parameter of the FDM circuitry is the selectivity of the intermediate frequency (I.F.) filter. The function of this filter is to select the desired FDM signal, rejecting the adjacent signals. It is desirable to space these signals as close as possible in order to conserve bandwidth. L-C and helical type filters, having the necessary adjacent channel rejection, are relatively expensive to implement. The availability and use of ceramic type mechanical filters enables substantial cost savings. Typical ceramic filters having a 4.5 megahertz center frequency have a characteristic bandwidth of approximately one hundred sixty-six kilohertz.

Assuming the use of these ceramic filters, conventional design practice requires that the transmission information bandwidth be less than one hundred sixty-six kilohertz but probably not less than one-half of one hundred sixty-six kilohertz. The sixteen bit format, multiplied by the eight kilohertz sampling rate, gives a one hundred twenty-eight kilobits per second digital information rate. Using a two-bits-per-hertz bandlimiting criteria gives a spectrum bandwidth of sixty-four kilohertz. The use of inexpensive amplitude modulated double sideband transmission (AM-DSB) requires one hundred twenty-eight kilohertz of transmission bandwidth which ideally matches the bandpass characteristics of readily available ceramic filters. An eight-bit format would be extremely wasteful of the bandpass characteristic and a thirty-two bit format would require more complex modulation techniques in order to be adequately bandlimited. The sixteen-bit format is, therefore, judged most efficient and cost-effective to ceramic filter handpass characteristics.

It may be argued that the use of 10.7 megahertz center frequency ceramic filters may allow the transmission of wider bandwidth information than the 4.5 megahertz filters discussed above. However, the use of an I.F. frequency that lies within the transmitting frequency band of the coaxial cable system may require extra conversion stages and therefore extra costs and complexity.

The sixteen-bit format per frame, 28, each frame, 28, having a framing bit, 16, in conjunction with a generated master synchronization signal, 306, for each transmission, 307, is conveniently used to transmit the various types of information between the subscriber and the central office terminal. As discussed, the function of the framing bit, 16, is to phase the MSI signal, 32, with the frame, 28, definition of the received digital signal.

The possible framing bit locations, 1-16, of this invention correspond to the transitions of the MSI signal, 306. The electronically convenient locations place the framing bit, on a time basis, in front of the MSI, 306, transitions. This allows the detection of the framing bit and then the formation of a transition of the MSI signal, 306, at the next clock signal, 301, transition. The framing bit, 1-16, location selected for the preferred embodiment is the last bit, 16, in the frame, 28, allowing the framing bit, 16, to indicate the beginning of the following frame, 28, at the next clock signal, 301, transition.

Preferably the first eight bits, 1-8, of the frame, 28, are dedicated to the address for the control signal and digital voice transmission for the other two signals. A codec requires eight bits and it is, therefore, most convenient to use the frame half, 37, for voice that does not contain the framing bit, 16. Other bits, 9-15, are then available for data transmission and housekeeping purposes.

It has been found advantageous to allocate the bit locations, 1-16, as follows, for the three signals used in the preferred embodiment. The described allocation should be understood to be illustrative, however, and is not meant to limit the invention as claimed.

For the control signal sent by the central office subscriber to address a specific subscriber bits 1 through 8 are the control signal's address location. Using the binary numbers 00000000 through 11111111 (0 through 255) two hundred fifty-six subscribers can be addressed on this one common control channel. Once a subscriber terminal receives its assigned address number, in this frame location, 37, the terminal's data decoder is activated to receive the remaining bits, bits 9 through 16. In this example configuration, bit 9 contains supervisory control information which, in this direction of transmission, instructs the subscriber terminal to ring the subscriber's telephone(s). Bit 10 enables (switches on) the terminal's second receiver, 113, and transmitter, 122. Bit 11 uses a serial code to assign the terminal to one particular channel. Bit 12 contains a second framing bit relating to the serial information in bit 11. Bits 13 through 15 are reserved for future data requirements. Bit 16 is the framing bit.

For the voice and data transmission to the addressed subscriber which are transmitted on the channel assigned by bit 11 of the control signal the first eight bits, 1-8, of the frame, 28, are preferably dedicated to digital voice transmission. The codec requires eight bits and it is therefore most convenient to use the frame-half, 37, for voice that does not contain the framing bit, 16. Bits 9 through 15 are then available for data transmission and housekeeping purposes. In one configuration, bit 9 is reserved for supervisory control even though the signal to ring the subscriber's telephone(s) is normally sent via the common control signal and bits 10 through 15 are used to carry data information to the subscriber with four of these generally carrying asynchronous, lowspeed relay closure type information while the remaining two carry higher speed text or facsimile information.

For the digital signal sent from the subscriber to the central office terminal, the first eight bits, 1-8, of the frame, 28, are preferably dedicated to digital voice transmission, for the reasons expressed above. Bits 9 through 15 are available for data transmission and housekeeping purposes. In one configuration, bit 9 is used for supervisory control which, in this direction of transmission, indicates the off-hook condition of the telephone set(s). Bit 10 carries a serial digital code indicating the subscriber terminal's location number. This number is decoded at the central office location and is used to determine which subscriber terminal is actually transmitting on the frequency being received. This same frequency may be assigned to four or more subscriber terminals, and therefore, the central office requires this location number in order to determine which of the four or more subscriber terminals is operational. Once a terminal transmits on an assigned frequency, the other terminals which were assigned to that same frequency, on a standby basis, are given new instructions.

Bits 11 through 15 are used to carry data service to the central office with three of these generally used to drive four lowspeed, asynchronous relay closure type data channels while the remaining two carry higher speed text or facsimile information. Three bits in this direction can be economically used to carry a larger number of lowspeed data channels because the destination of this information is generally a minicomputer, 208, having ample intelligence to decode the necessary data format. In other embodiments each one bit is used to carry several lowspeed circuits. The only consideration is convenience and minimizing system costs.

FIG. 2 is a schematic diagram representing the preferred method of generating the signals necessary to detect the framing bit, 16; and, distinguish it from all other bits, 1-15, in the frame, 28. The received digital signal, digial signal regenerated clock signal, 301, is fed to the clock input of a CMOS type 4024 divider circuit, 302. The divider circuit, 302, divides the one hundred twenty-eight kilohertz clock signal, 301, into an eight kilohertz signal, 303, a sixteen kilohertz signal, 311, and a four kilohertz signal, 304. The divider circuit 302, is reset by reset signal, 305. The function just described is termed the "framing counter".

The eight kilohertz signal, 303, is fed to the data input of flip-flop, 316. The one hundred twenty-eight kilohertz clock signal, 301, is fed to the clock input of flip-flop, 316. The Q output of flip-flop, 316, provides the received MSI signal, 306. This function is termed the "eight kilohertz signal to MSI conversion".

The received digital signal, 307, is fed to the data input of flip-flop, 317, and the eight kilohertz signal, 303, is connected to this flip-flop's, 317, clock input. Reset signal, 305 is connected to the reset input of this flip-flop. The Q output of flip-flop, 317, is connected to the clock input of flip-flop, 318. This signal is the instantaneous logic level of the randomly selected frame bit. This logic level toggles flip-flop 318, in order to generate the CK and inverted-CK signals. The reset of flip-flop 318, is connected to reset signal 305. The data input and inverted-Q output of flip-flop 318, are connected in order to provide the toggle configuration. This function is termed "toggling the selected data time circuit".

The object of the circuitry shown in FIG. 5 is to provide the necessary signals to operate the framing circuit. In addition to the 8-KHz 303, 16-KHz 311, 4-KHz 304 and the MSI 306 signals, this circuit generates the two necessary check signals, CK and inverted-CK, to allow certain tests to be made in order to determine whether the randomly selected frame bit is, indeed, the valid frame bit.

FIG. 3 is a schematic diagram representing the preferred method of detecting repetitive zeros on the CK signal in order to determine an invalid framing bit selection. The inverted-CK signal is fed to the data input of flip-flop 19 and that signal is shifted through flip-flops 320 and 321 at the 4-KHz 304 clock rate. NOR gate, 323, sends a positive transition to the clock input of flip-flop, 324, and repeats this positive transition at a 16-KHz rate if the first NOR gate input, which is connected to the inverted-Q output of flip-flop 21, goes to logic "0". The 16-KHz repetition rate, cause by the 16-KHz signal 311, on the NOR gate's 323, second input, insures that the flip-flop's 324 inverted-Q output 312, will be set to logic "0" without fail. The logic "0" output is caused by the logic "1" 308, fed to the flip-flop's 324, data input; and, a positive transition at the clock input. This condition signals the existence of repetitive zeros on the CK signal. If the CK signal does not consist of repetitive zeros, then, the logic "0", inverted-CK input o NAND gate 322, will cause the shift register (made-up of flip-flops 319 through 321) to reset before the inverted-Q output of flip-flop 321, switches to the logic "0" state. These flip-flops 319-321, are reset by reset signal 305, by means of the inverted-reset 309, signal fed to the first input of NAND gate 322. This circuitry constitutes a repetitive zero detector.

FIG. 4 is a schematic diagram representing the preferred method of testing the CK signal at various checkpoints for determining an invalid framing bit selection. The 8-KHz signal 303, is inverted by inverter 329, and fed to the clock input of the CMOS 4022 divider circuit 325. This divider circuit 325 is reset by reset signal 305, and provides three output signals, 332, 333 and 334, which, clock flip-flops 327, 328 and 326, at the proper testing times. The CK signal has a frequency of one-half the framing rate, assuming a valid framing bit is selected, which is four kilohertz. This four kilohertz CK signal has certain characteristics that are easily tested. One complete cycle of the above described four kilohertz CK signal squarewave is, for discussion, divided into eight check-points equally spaced and coincident with the positive and negative transitions of the sixteen kilohertz signal, 311. Check-point 4 falls at the CK signal negative transition, at the midpoint of the cycle, for example. Check-point 8 falls at the positive transition of the next cycle and therefore, check-point 8 of one cycle is check-point 0 of the next.

It can be shown mathematically that, with the repetitive zero test, check-points three, five, and seven are the optimum test points for checking the selected bit's validity. Check-point one falls within certain settling time uncertainties and should not be used. Check-points two, four and six fall on certain mathematically possible transition locations and therefore have an uncertainty factor. Check-points three, five and seven, however, always test a steady-state logic "1" or logic "0". Additional check-points are unnecessary and repetitive; and, fewer check-points would allow certain invalid signals to go undetected.

The first test, of this series, is to check for a CK signal logic "1" at check-point 3. The divider 325 output signal 332 has a positive transition corresponding, in time, to check-point 3. This signal is fed to the clock input of flip-flop 327. The data input of this flip-flop is connected to the inverted-CK signal and the reset is connected to reset 305. The inverted-Q output of this flip-flop goes to a logic "0" if the CK signal at check-point 3 is a logic "0" instead of a logic "1". This error signal, 313, is termed the "check-point 3 `0`" signal.

The divider, 325, output, 333, has a positive transition corresponding, in time, to check-point 5. This signal is fed to the clock input of flip-flop, 328. The data input of this flip-flop is connected to the CK signal and the reset is connected to reset, 305. The inverted-Q output of this flip-flop goes to a logic "0" if the CK signal at check-point 5 is a logic "1" instead of a logic "0". This error signal, 314, is termed the "check-point 5 `1`" signal.

The divider, 325, output, 334, has a positive transition corresponding, in time, to check-point 7. This signal is fed to the clock input of flip-flop, 326. The data input of this flip-flop is connected to the CK signal and the reset is connected to reset, 305. The inverted-Q output of this flip-flop goes to a logic "0" state if the CK signal at check-point 7 is a logic "1" instead of a logic "0". This error signal, 315, is termed the "check-point 7 `1`" signal.

FIG. 5 is a schematic diagram representing the preferred method of combining the error signals of FIGS. 6 and 7 and having any error signal, during any CK signal cycle, cause the framing circuit to reset and select another bit, within the frame, to test for framing bit validity. The four error signals, 312, 313, 314 and 315 are connected to the inputs of NAND gate, 330. The NAND gate, 330, output goes to logic "1" if and only if one or more of the error signal inputs goes to a logic "0", indicating an invalid framing bit selection. This enables the astable multivibrator's 331 Q output 305 to go to a logic "1" state, thus resetting all the flip-flops and dividers connected to reset 305, but, also enabling these circuits to make a new, random framing bit selection immediately after reset 305 returns to the logic "0" state. The signal 309 is the inverted-Q output of the astable multivibrator 331. The signal 310 is the input to the astable multivibrator 331 reset, and provides a reset signal to insure that the astable multivibrator 331 is in the reset state when the circuit is initially powered up.

The circuitry discussed above and shown in FIGS. 3-5 constitutes the preferred circuitry for an all digital method for detecting the framing bit, 16, and distinguishing it from all other bits, 1-15, in the frame, 28.

FIG. 6 is a schematic diagram representing an alternative method and embodiment for detecting the framing bit, 16. The received, randomly selected bit logic levels, 401, are fed to the data input of flip-flop, 402, and to the second input, 403, of exclusive-OR gate, 404. The Q output, 405, of flip-flop, 402, is fed to the first input, 406, of exclusive-OR gate, 404. This gate's output, 407, will have a logic "1" level if and only if its two inputs, 403 and 406, are opposite in logic levels. This is the situation if and when the randomly selected bit is the valid framing bit. The reason is as follows:

The logic level input at the flip-flop's, 402, data input is shifted to the flip-flop's Q output at the next clock input positive transition. The flip-flop's clock input is the eight kilohertz signal, 408, the eight kilohertz signal, 303, of FIG. 5. Since the valid framing bit has an alternating logic "1", logic "0" pattern, the signals, 403 and 406, will be opposite in logic levels if and when the randomly selected bit is the valid framing bit. In the situation where the signals, 403 and 406, are like logic levels, an invalid framing bit has been selected, and the exclusive-OR gate's, 404, output, 407, goes to a logic "0" level. This logic "0" level is fed to the first input, 409, of NOR gate, 410, via a time constant circuit comprised of signal diode, 411, resistor, 412, and capacitor, 413. This time constant circuit prevents relatively narrow sliver pulses and error spikes from presenting a spurious signal to input, 409.

The second input, 414, of NOR gate 410 has a logic "1" level during the period of time that new information is being shifted into flip-flop, 402, in order to prevent the NOR gate's output from going to a logic "1" level during this period of time. This is accomplished by means of the time constant circuit comprised of signal diode 415, resistor 416, and capacitor 417. The NOR gate's, 410, output, 418, is fed to the clock input of flip-flop, 419. A logic "1" level, 420, is fed to the data input of flip-flop, 419, and, therefore, a positive transition at the clock input causes the flip-flop's Q output, 421, to go to a logic "1" level. This logic "1" level is fed to the flip-flop's reset input, 422, via a time constant circuit comprised of signal diode, 423, resistor, 424, and capacitor, 425. A signal, 426, resets flip-flop, 419, when the circuit is first powered up. The logic "1" level at flip-flop, 419, output, 421, is fed to the reset input, 427, of flip-flop, 402, and also, by means of signal lead, 428, to the other components of the framing circuit.

The framing circuit is caused to select another bit, within the frame for testing when the reset signal, 428, again returns to a logic "0" level.

The framed signals, the control signal and the data transmission signal from the central office terminal and the return data transmission signal from the subscriber terminal, or variations thereof, can then be advantageously used with the equipment shown in FIGS. 7 and 8 as follows:

FIG. 7 is a diagrammatic representation of the preferred central office terminal configuration. The incoming and outgoing broadband signals are carried through the central office terminal system on coaxial cable, 101. Signals are tapped on and off of the coaxial cable, 101, by use of conventional taps, 102. The common control signal circuit, 203, is the same in each of the two hundred fifty-six subscriber terminals, in that, it manages the channel assignments of one pair of twelve megahertz bands. The common control signal module, 203, consists of the common control logic circuit, 206, which formats the information received by circuit, 203, from the central office terminal logic control circuit, 208. This formatted digital common control signal is fed from the common logic control circuit, 206, to the common control transmitter, 205. The common control transmitter, 205, is crystal controlled and tuned to one assigned frequency within the twelve megahertz band transmitted from the central office terminal to the subscriber terminals.

The telephone line module, 204, contains the voice and data transmitter/receiver that are always paired with one assigned subscriber terminal. There may be two hundred fifty-six of these telephone line equipment modules at the central office location, each having a matching subscriber terminal.

Another embodiment (not shown) uses one transceiver per actual channel; i.e., a total of sixty-four transceivers, with a switching matrix connecting the transceivers to the two hundred fifty-six subscriber line interface circuits.

The receiver, 216, is tuned by means of the local oscillator signal generated in the phase locked loop frequency synthesizer 223. The frequency synthesizer 223 generates a local oscillator signal according to the binary coded signal it receives from the central office logic control circuit, 208. The receiver, 216, frequency corresponds to the frequency its matching subscriber terminal's transmitter is instructed to transmit on, if and when it is given the instruction to transmit. The receiver, 216, constantly monitors its assigned frequency and demodulates any received signal that exceeds its squelch threshold. Since more than one subscriber terminal may be instructed to use that frequency, on a first come, first served basis, the receiver, 216, will be instructed to stay on that frequency if and only if it is receiving a signal from its matching subscriber terminal. It will be immediately instructed to tune to a different frequency if a subscriber terminal other than its matching subscriber terminal is the first to transmit on that available frequency. The receiver's, 216, frequency changes, in that situation, to the same newly assigned frequency as its matching subscriber terminal's transmitter.

The demodulated signal is fed from the receiver 216 to the clock recovery circuit 217. The regenerated clock and digital signal is fed to the master synchronization recovery circuit 218. The recovered clock signal, the MSI signal and the digital signal is then fed to the address decoder 219, where, if the address of the received signal matches the address of this telephone line module 204, a signal is sent to the central office logic control circuit 208 indicating that the assigned channel is in use (and therefore the logic control circuit 208 reassigns all other subscriber terminals originally assigned to that frequency to other available frequencies). Assuming a valid address is received by a specific terminal, the clock signal, MSI signal and the digital signal are fed to the received data logic circuit 220 with the received data signals outputted on the received data terminal 221. The clock signal, MSI signal and digital signal are fed to the codec 213 where the voice information is converted from a digital to analog format. The voice signal is fed from the codec, 213, to the subscriber line interface circuit, 214. The received supervisory control signal is fed from the received data logic circuit, 220, to the subscriber line interface circuit, 214. The subscriber line interface circuit, 214, is connected to the central office line switching equipment at the subscriber line terminal, 215.

The telephone voice and supervisory control information to be sent to the subscriber terminal location from the central office location is fed from the subscriber line interface circuit 214 to the codec 213, where the voice information is digitized. The digitized voice information plus the supervisory control information is then fed to the transmit data logic circuit 211 and combined with the transmit data inputted on the transmit data terminal 210. This combined voice and data information is properly formatted and sent to the transmitter 212. The central office logic control circuit 208 receives, from the transmit data logic circuit 211, the indication that there is information to be sent to the matching subscriber terminal and therefore sends an enable signal to the matching subscriber terminal via the common control signal and also sends an enable signal back to the transmit data logic circuit 211, which is fed to the transmitter 212. The transmitter 212 provides a termination 104 equal to the characteristic impedance of the coaxial line.

FIG. 8 is a diagrammatic representation of the preferred subscriber terminal configuration. The coaxial cable transmission line 101, outside of the house, is tapped 102 using conventional CATV hardware and techniques. Inside the house, television service is tapped, 102, off of the coaxial cable using conventional CATV practice. This service is displayed on the subscriber's conventional television set 103. A third tap 102 connects the subscriber terminal 126 to the transmission system which is terminated in its characteristic impedance 104.

Inside the subscriber terminal 126 the common control signal is received and demodulated by the first receiver 105. The high impedance receiver input 106 receives the signal from the transmission medium in the 12-MHz frequency band that carries the information from the central office location to the subscriber locations.

The demodulated signal is fed to the clock recovery circuit 107 where the received digital signal regenerated clock signal is derived. This clock signal and the digital signal are fed to the master synchronization recovery circuit 108 where the framing pulse is detected and the MSI signal is derived. The clock signal, MSI signal and the digital signal are fed to the address code decoder 109 where the data relating only to that particular terminal location is decoded. The decoded information, relating to that particular terminal location, is fed to the received data logic circuit 110. The transmit enable signal 125 keys the transmitter 122 as instructed by the common control signal. The transmitter 122 is also keyed by the transmitted data logic circuit 121 if and when information originates at the subscriber location.

When the subscriber location has been activated by detection of its address in the control signal, voice and data information, sent from the central office terminal to the subscriber location over the assigned channel, is received at the second receiver's 113 high impedance input terminal 112 and demodulated. The frequency this second receiver is tuned to, within the 12-MHz band sent from the central office location to the subscriber locations, is determined by the local oscillator signal generated by the terminal's phase locked loop frequency synthesizer 116.

The frequency synthesizer 116 is controlled by the binary signal 117 it receives from the received data logic circuit 110. The demodulated second signal is fed from the second receiver 113 to the clock recovery circuit 114. The regenerated clock and the digital signal are fed to the master synchronization recovery circuit 115 where the framing pulse is detected and the MSI signal is generated. The second clock signal, the second MSI signal and the second digital signal are fed to the received data logic circuit 110 and to the codec 118. The received data information is outputted at the received data terminal 111. The received voice information is fed from the codec 118 to the subscriber line interface circuit 119. The received supervisory control information is fed from the received data logic circuit 110 to the subscriber line interface circuit 119. The subscriber's telephone set(s) are connected to the telephone interface terminal 120.

The telephone voice and supervisory control information to be sent from the subscriber to the central office location is fed from the subscriber line interface circuit 119 to the codec 118, where the voice information is digitized. The digitized voice information plus the supervisory control information is then fed to the transmit data logic circuit, 121, and combined with the transmit data inputted on the transmit data terminal, 123. This combined voice and data information is formatted per the above discussion and sent to the transmitter, 122, for transmission to the central office terminal. The transmitter, 122, frequency is determined by the local oscillator signal generated by the phase locked loop frequency synthesizer, 116. The control of the frequency synthesizer, 116, is discussed above. The transmitter, 122, output is terminated with the transmission medium's characteristic impedance, 104.

From a consideration of the foregoing disclosure it should be obvious that the invention is simply constructed, simply operable and economical to manufacture since all subscriber terminals are standardized and manufactured from inexpensive and easily obtainable components. As a consequency, the invention as a whole is not susceptible to the complexities of the prior art. It should be understood that modifications and variations beyond those described and discussed may be resorted to without departing from the spirit of the invention as those skilled in the art will readily understand. Such modifications and variations are considered and intended to be within the purview and scope of the present invention as defined by the following claims.