Method and Arrangement for the Digital Regulation of the Carrier Phase Error in Receivers of Data Transmission Systems

The present invention relates to a method and a circuit arrangement, respectively, for digitally regulating the carrier phase error in receivers of digital data transmission systems of the type wherein a comparator is used to determine, from the sampled value of the demodulated input signal and from the estimated value for each sampling time associated therewith by means of a decider, the deviation dk which is a measure for the phase difference between the sampled value and the estimated value. This deviation value is then filtered in a digital loop filter, including a proportional branch and an integration branch, and the regulating value is obtained in a subsequently connected accumulator.

Such a method and circuit arrangements for practicing the method are disclosed in the paper by Kammeyer and Schenk, "Ein Flexibles Experimentier-system fur die Datenubertragung im Fernsprechbereich" (A Flexible Experimental System for Data Transmission in the Telephone Field), FREQUENZ (Frequency), 1979, Volume 33, No. 5, pages 141-145 and No. 6, pages 165-172 as well as in an article by Gockler, Hofmeister and Till "Datenubertragung mit 4.8 kBit/s im Fernsprechnetz" (Data Transmission with 4.8 kBit/s in a Telephone Network) WISSENSCHAFTLICHE BERICHTE (Scientific Reports) AEG-TELEFUNKEN, 1978, Vol. 51, No. 4/5. pages 231-245. In this described system, the phase information for the carrier regulation is derived from the input and output signals of the decider. The decider input signal can be represented in the signal plane by a vector which for quadrature amplitude modulation (QAM) includes the components xk and yk, these components being sampled values of the analytical signal after demodulation. In the decider, these sampled values are associated with estimated values ak, bk. The average of the phase difference between the actual value vector and the desired value vector corresponds to the carrier phase error. By means of the carrier phase error regulation, the demodulation phase is caused to be regulated until the phase difference on the average becomes zero. For this purpose, a deviation dk is determined in a comparator for each sampling time k.multidot.T as it results from the corresponding linkage of the input and output signals of the decider. After filtering of the deviation value dk in a digital loop filter with subsequent accumulation, there results the angle of additional rotation of the signal vector as required for coherent demodulation. The digital loop filter includes a proportional branch and an integration branch. Both branches of the filter can be weighted by means of respective multipliers or multiplying values ki or kv, respectively. However, even with favorable dimensioning of these two weighting factors it is possible that in the nontransient final state other parameter settings occur which are of similar quality criteria but are otherwise unusable.

It is therefore the object of the present invention to provide a method, and a circuit arrangement for practicing this method, which makes it possible to realize an optimum setting of the parameters with mutually coupled adaptive adjustment of the adaptive equalizer and the digital phase regulation so that correct data transmission is possible in the nontransient final state. In this connection it should be avoided that other parameter settings occur which are similar with respect to the quality criteria but are otherwise unusable.

The above object is achieved according to the invention in that, in a method for digitally regulating carrier phase error in receivers of digital data transmission systems including the steps of feeding the sampled values of the demodulated input signal of the receiver to a decider to provide estimated values for each associated sampling time, comparing the sampled value of the demodulated input signal with the associated estimated value for each sampling time to determine a deviation value which is a measure for the phase difference between the sampled value and the associated estimated value, filtering the deviation value in a digital loop filter including parallelly connected proportional and integral circuit branches, accumulating the output values of the digital loop filter to provide a regulating value, and using this regulating value to correct the carrier error, a non-linear limit on the deviation value being integrated over time is included in the integral branch of the digital loop filter.

Preferably, the deviation value being integrated in the integration branch of the digital loop filter is limited to a value equal to or less than one half of the angular spacing between the desired phase positions of the carrier. Moreover, the non-linear limitation of the deviation value is preferably only utilized after the end of a data transmission preamble.

According to the apparatus of the invention, the above object is achieved by inserting a non-linear limiter in the integration branch of the digital loop filter to limit the deviation value being integrated to a desired maximum value.

FIG. 1 is a block circuit diagram of an embodiment of an apparatus according to the invention for carrying out the method of the invention.

FIG. 2 is a block circuit diagram showing a modification of the embodiment of FIG. 1.

Referring now to FIG. 1, there is shown an example for an embodiment of a carrier regulation circuit for an mPSK (phase shift keying) system where m is the number of phase positions. As shown, the demodulated base band signal, which has been equalized in a transversal equalizer 10, is fed to a unit 12 wherein it is, e.g. with the aid of a Cordic algorithm, shifted into the desired phase position by means of a generated regulating value .delta.k. This algorithm is, for instance, described by J. E. Volder "The CORDIC trigonometric computing technique", IRE Trans. Electron. Comput. Vol EC-8, pp. 330-334, Sept. 1959. The sampled regulated output signal value from the unit 12, which signal value with quadrature amplitude modulation (QAM) includes the components xk and yk, is fed to a decider 14 in which the estimated values, e.g. ak and bk, respectively, are associated with the sampled signal values. The estimated output signal values from the decider 14 are fed to a decoder (not shown) for the receiver.

Various deciders are described by Bennett and Davey "Data Transmission" McGraw-Hill Book Company 1965, pages 201-208.

In order to generate the regulating signal .delta.k, the phase difference .DELTA..PHI. between the estimated value and the sampled value is determined by feeding the input and output signals of the decider 14 to a comparator 16, which produces a deviation signal dk corresponding to the phase difference. This deviation dk is filtered in a digital loop filter 18 and is accumulated in a subsequently connected accumulator 20 to form the regulating value .delta.k. The digital loop filter 18 comprises the parallel connection of a proportional circuit branch 22 and an integrating circuit branch 24, with the outputs of the two branches being summed in a summing unit 26. The integrating circuit branch 24 includes a delay member 28 provided with a feedback connection 30. The accumulator 20 is likewise provided with a delay member 32 with a feedback connection 34. The integrating branch 24 of the digital loop filter 18 is provided with a multiplier circuit 36 so that the value of dk therein can be weighted with the multiplier value ki, and the output of the summing circuit 26 is provided with a further multiplier circuit 38 so that the values resulting from both branches 22 and 24 can be weighted with a multiplier kv to provide the values .DELTA..delta.k which are accumulated in accumulator 20.

According to the invention, the integral or integration branch 24 of the digital loop filter 18 further includes a non-linear limiter 40 with which the change in the regulating value .delta.k is limited to a maximum amount per stepping clock pulse, so that unusable parameter settings are avoided. The limiter 40 produces an output signal B such that all output values B of the integration branch greater than a, i.e. .vertline.B.vertline.>a, are limited so that .vertline.B.vertline..ltoreq.a, where a=360.degree./2m and m is the number of desired phase positions for the PSK system.

The invention can of course also be used in receivers having a decision feedback connected equalizer DFE or operating according to any other equalizing principles. A type of decision feedback equalizer is described, e.g. by George, Bowen and Storey, "An adaptive decision feedback equalizer", IEEE Trans. Communic. vol. COM-19 (1971) 3, pages 281-293. The basic regulating circuit arrangement shown in FIG. 1, is described by Maddens, "Carrier-Phase tracking in Synchronous Data Transmission Systems" IBM Techn. Disclosure Bull. vol. 19 (1976) 5 pages 1729-1732. A limiter which can be used for the limiter 40 is described by Freeny, "Special-purpose hardware for digital filtering", Proc. IEEE, vol. 63, No. 4, (1975) pages 633-648.

The invention will now be explained in detail with the aid of an m-PSK modem where m=8. In such a system, the m=8 desired phase points in the phase plane are arranged at equal distances, so that the angle spacing is 360.degree./8=45.degree.. The decider 14 of FIG. 1 emits values corresponding to one of these phase points per step and these values are used as the basis for the future setting of the phase regulation and of the adaptive equalizer. Due to special circumstances, e.g. starting conditions, interference or malfunctions, it can happen that individual values are summed in the integral branch 24 in such a way that the phase regulation from step to step shifts in phase by i.multidot.360.degree./m=i.multidot.45.degree., where i is an integer, without this phase shift corresponding to an actually existing frequency displacement between the modem transmitter and receiver. This leads to error decisions which generally can be detected in the system only upon checking of the received data sequence.

The above-described undesirable state will not be reached if the output value of the integral branch 24 is limited by the non-linear limiter 40 such that the phase can be shifted per step only by a maximum value of 360.degree./2m=22.5.degree. for the 8-PSK system.

Alternatively, the limitation of the phase regulation value .delta.k can be realized with the aid of an overflow readout 42 as shown in FIG. 2. Such overflow readout becomes less complicated if, as shown, instead of inserting the weighting factor ki by means of single multiplier (e.g. multiplier 36 of FIG. 1), the weighting factor ki is divided into the product of two partial factors k.sub.1 and k.sub.2, which are associated with respective multipliers 36' and 44. The realization becomes particularly simple if the weighting factor ki or at least one of the two partial factors k.sub.1 or k.sub.2 is equal to 2.sup.-i, where i=a whole number. The mode of operation of such an overflow readout is described by Freeny, "Special-purpose Hardware for Digital Filtering", Proc. IEEE, vol. 63, No. 4 (1975) pages 633-648.

It is to be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.