Vehicle-Mounted Message Apparatus

The present invention relates to a vehicle-mounted message apparatus which records a simple message by voice and automatically reproduces it for notification.

In the case where a single motor vehicle for business or a company-owned passenger car is used by a plurality of persons, a driver may want to leave a message including instructions on fuel supply, car cleaning or transfer to another use or place to the next driver or vehicle administrator when leaving the vehicle. If such a message is left in the form of written memo, it may go astray or may be overlooked.

Accordingly, it is an object of the present invention to provide a vehicle-mounted message apparatus which records a message through a microphone and reproduces it by speaker, thus informing the next driver of instructions as required.

FIG. 1 is a diagram showing an electrical circuit of an embodiment according to the present invention.

FIGS. 2, 3 and 4 are timing charts showing the operations of recording and reproduction of the apparatus shown in FIG. 1 and the reproduction and erasure at the time of closing a key switch thereof respectively.

The present invention will be described with reference to the accompanying drawings. In the electrical wiring diagram of FIG. 1 showing a general configuration of the apparatus of the invention, reference numeral 1 shows a recording microphone for converting a voice into an electrical signal. Numeral 2 shows a reproduction speaker for converting an electrical signal into a voice. As an alternative, the microphone 1 and the speaker 2 may be integrated in the form of a single dynamic speaker as used in a compact radio communication equipment.

Numeral 3 shows a DC battery mounted in a vehicle, and numeral 4 a key switch provided at accessory position or ignition position.

Reference characters R and P show operating switches, of which character R shows a control switch for issuing a recording command and character P shows a control switch for reproduction in order to confirm the recording command. Character D shows a display unit which is lit for a period of time during which the recording is available after operation of the switch R. The display unit D includes a light-emitting diode. The recording switch R and the display unit D may be conveniently formed integrally with the microphone 1 to facilitate manual operation.

Numeral 10 shows an amplifier circuit for amplifying a weak voice electrical signal converted through the microphone 1, and numeral 20 shows an analog-digital converter for repetitively converting at high speed the amplified voice electrical signal (voltage signal) into a 4-bit digital signal easy to be memorized. This converter circuit 20 comprises the A/D converter MN5123 of sequential comparison type marketed by Micronetwork as designed by numeral 201 and a clock signal generator circuit 202 for generating a clock signal of 2 MHz for actuating the converter 201. The digitized voice data are applied at the rate of 8 bits at a time to a semiconductor memory unit 60 in predetermined cycles through a control circuit 70. The voice data are also read out from the memory 60 at the rate of 8 bits at a time in predetermined cycles and applied to the digital-analog converter 30. This converter circuit 30 is configured of the D/A Converter MN3014 (designated by 301) of ladder type marketed by Micronetwork, which converts a digital signal representing a voice into a voltage signal. Numeral 40 shows a low-pass filter for cutting off high frequencies, which is adjusted at the cut-off frequency of 1.8 KHz. Numeral 50 shows a reproduction amplifier which by use of an integrated amplifier element (such as LM380 of National Semiconductor) amplifies a voice signal and announces it as a voice through the speaker 2.

The semiconductor memory unit 60 includes a decoder 601 (such as TC4556 of Toshiba) and a plurality of CMOS random access memories (such as HM6147 of Hitachi, Ltd.). Random access memory groups 60A, 60B and 60C each including eight random access memories corresponding to the 8 bits subjected to A/D or D/A conversion respectively are arranged in juxtaposition under the control of a decoder 601, so that a total of 4096 multiplied by 3 addresses are set in the memory unit 60.

The control circuit 70 is for controlling the operations of the A/D converter 20, the D/A converter 30, the data storage in the memory unit 60 and the reading thereof from the memory unit 60 in response to the start of power supply by the closing of the key switch 4 and the control switches R and P, thus causing the apparatus to effect the recording, reproduction or erasure selectively. This control circuit 70 is divided by function into a timing circuit 70A for controlling the timing of recording, reproducing and erasing operations, a condition or mode determining circuit 70B for determining the operating mode of the recording, reproduction or erasure, and a memory control circuit 70C for designating an address of the semiconductor memory unit 60 and issuing a command for change-over between storage and reading. The detailed operation of the circuits 70A, 70B and 70C will be described with reference to the operation of the apparatus as a whole later.

Numeral 80 shows a power supply circuit comprising a voltage regulator 801 (SI-3554M of Sanken) for generating a constant voltage of 80a (V) in response to the closing of the key switch 4, a voltage regulator 802 (MC7805 of Motorola) for generating a constant voltage of 80b (VM) for the backup of the memory unit 60 regardless of whwether or not the key switch 4 is closed, and a DC-DC converter 803 (CX255-5 of Tokyo Radio Equipments) for generating positive and negative voltages of 80c (V.sub.+, V.sub.-) for actuating the A/D converter 201 and the D/A converter 301.

The operation of the apparatus will be described in detail. Timing charts of FIGS. 2 and 3 show the recording and reproduction operations respectively, and the timing chart of FIG. 4 the operation of reproduction and erasure at the time of closing of the key switch 4. The functions of the elements designated by typical symbols including an OR gate, an AND gate and a NAND gate in FIG. 1 will not be partly described.

Assume that the key switch 4 is closed. A pulse signal 70a of about 10 ms depending on the time constant due to the capacitor C.sub.2 and the resistor R.sub.2 is generated by a power-on pulse generator circuit 708 in the mode determining circuit 70B. This pulse signal is applied to flip-flops 702, 703 and 705 (TC4013 of Toshiba), thus resetting these flip-flops. In response to the resetting of the flip-flop 702, a reversed output signal 70g thereof becomes "1", thus resetting a counter 701 (TC4024 of Toshiba) of the timing circuit 70A and address counters 706 and 707 (TC4040 of Toshiba) of the memory control circuit 70C.

If the recording switch R is closed under this condition (the reproducing operation by the closing of the key switch 4 will be described later for convenience' sake), a one-shot multivibrator 710 is triggered, so that a pulse signal 70m of about 20 .mu.s is generated as shown in FIG. 2(2). This pulse signal 70m is applied to the flip-flops 702 and 705 thereby to reset the same, after which the flip-flop 702 is set by a delay signal 70n. In response to the setting of the flip-flop 702, the reversed output signal 70g thereof becomes "0" (FIG. 2(4)), so that the reset state of the counters 701 and 706 is cancelled, thus making possible the counting operation.

The pulse signal 70m, after being delayed by the time constant circuit (FIG. 2(3)), on the other hand, is applied to the flip-flop 703, which is thus set with the result that the light-emitting diode D is actuated and lit. Thus the user or driver is informed that the recording operation is available. When the user gives a message to the microphone 1, a corresponding voice electrical signal generated from the microphone 1 is amplified and applied to the A/D converter circuit 20.

In the timing circuit 70, a reference clock circuit 709 continues to generate a clock signal 70b of 48 KHz, the counter 701 counts the clock signal pulses 70b in response to the cancellation of the resetting of the counter 501, and a frequency-divided signal as shown in FIGS. 2(7) and 2(8) are produced at the output terminals Q.sub.3 and Q.sub.4 respectively. The frequency-divided signal Q.sub.3 has 6 KHz and the frequency divided signal Q.sub.4 has 3 KHz.

The one-shot multivibrator 711 responsive to the fall of the signal from "1" to "0" level generates a pulse signal 70h (FIG. 2(5)) taking the level "0" at about 1 .mu.s with the period of 167 .mu.s, in response to the frequency-divided signal Q.sub.3 of 6 KHz from the counter 701 and the reset signal 70g from the flip-flop 702. This signal 70h is applied to the A/D converter 201 as a start pulse for the A/D conversion. The A/D converter circuit 20, which is impressed with the voice signal from the amplifier circuit 10, effects A/D conversion of the voice signal at the sampling frequency of 6 KHz and generates an operating signal 70.theta. which falls from "1" to "0" each time of completion of A/D conversion (FIG. 2(6)).

In response to this fall of the operating signal 70.theta., the one-shot multivibrator 712 generates a pulse signal 70p of about 1 .mu.s each time of completion of A/D conversion (FIG. 2(9)). This pulse signal 70p is applied to a tri-state latch (TC4076 of Toshiba) 713 which performs the latching operation when the signal at the control terminal G.sub.1, namely, the frequency-divided signal Q.sub.4 of the counter 701 is "0". In other words, in response to odd-numbered pulses 70p1, 70p3 and so on among the latch pulses 70p1, 70p2, 70p3 and so on shown in FIG. 2(9), the A/D converted digital voice signal is latched. The tri-state gate (TC5012 of Toshiba), on the other hand, gates the A/D converted digital voice signal regardless of the number of times of A/D conversions. In this way, 4-bit digital signals A and B obtained by two A/D conversions are produced from the latch 713 and the gate 714 respectively each time of completion of two A/D conversions.

In response to the fall of the operating signal 70.theta. for A/D conversion and the "1" level of the frequency divided signal Q.sub.4 of the counter 701, the one-shot multivibrator 715 produces a timing signal 70q of "0" level of about 200 .mu.s (FIG. 2(10)). As long as this timing signal 70q is "0", the divider counter 716 is ready to count and counts the clock pulses 70b from the reference clock circuit 709 with the result that the divider counter 716 produces pulse signals 70f' and 70i of "1" level at the timing shown in FIGS. 2(11) and 2(12) respectively at the terminals 2 and 4 thereof (FIG. 2(11) shows a signal 70f that has passed the NAND gate.).

When the count value (A.sub.0, A.sub.1, A.sub.2, . . . A.sub.14) representing the addresses of the memory unit 60 which is counted by the counters 706 and 707 does not reach a predetermined value (i.e., when the signal 70j is "0"), the NAND gate 717 produces a write control signal 70f which takes a reversed form of the pulse signal 70f' (FIG. 2(11)). At the timing when the reversed signal 70f is "0", each of the random access memories 602 of the memory unit 60 is actuated for storage. In view of the fact that the first address is designated at 0 by the resetting of the counters 706 and 707, the voice digital values A and B after the A/D conversion are stored (written) in the first address of the first random access memory group 60A.

Immediately following each storage, the pulse signal 70i (FIG. 2(12)) is applied to the counters 706 and 707 thereby to update the storage addresses (A.sub.0 to A.sub.14). As seen from above, the A/D conversion and the storage of the digital value following the A/D conversion is started by the closing of the recording switch R and repeated in response to the frequency signal of 6 KHz generated at the timing circuit 701 (The storage is effected at the timing of 3 KHz). After a series of A/D conversions, the addresses (A.sub.0 to A.sub.14) designated by the counters 706 and 707 are updated each time of completion of each storage. This process is repeated until the storage addresses are filled up.

Let the sampling frequency after A/D conversion be F, the number of bits thereof be B.sub.1 and the capacity of the memory unit 60 be B.sub.2 (bits).times.W (words). Then the recording time T is given as T=W.multidot.B.sub.2 /(F.multidot.B.sub.1). In the embodiment under consideration, T=4096.times.3.times.8/(6.times.10.sup.3 .times.4).apprxeq.4 sec. Thus the voice continuing for about 4 seconds after the closing of the recording switch R is stored as a digital value.

When the memory addresses are filled up, the count values A.sub.12 and A.sub.13 (FIGS. 2(15) and 2(16)) of the counters 706 and 707 both take the level "1", and the recording end signal 701 takes the level "1" at the same time. In response to this "1" signal, the flip-flop 703 of the mode determining circuit 70B is reset. As a result, the display light-emitting diode D is extinguished, thus informing the user of the end of recording. Until another period of about 1.3 seconds pass, the above-mentioned A/D conversions are repeated so that the counts of the counters 706 and 707 increase. For lack of a corresponding address in the memory unit 60, however, no data are stored actually.

At the time point about 5.3 seconds after the closing of the recording switch R, the count value A.sub.14 (FIG. 2(17)) of the counters 706 and 707 becomes "1", and is recovered as an automatic reproduction signal 70j. This signal is reversed and applied to one of the input terminals of the NAND gate 717. Thus, the write control signal 70f derived from the output thereof remains "1" regardless of the pulse signal 70f'. Each random access memory 602 making up the memory unit 60 transfers to a read mode and therefore fails to perform a storage operation.

The recording processes are thus completed. Even when the key switch 4 is opened after the completion of the recording operation, the voltage of the memory unit 60 is maintained by the voltage regulator 802 and therefore the recorded voice is held. When the voltage drop detector circuit 718 detects that the key switch 4 is open or when the apparatus is standing by (or when the flip-flop 702 is reset), the signal 70e is raised to "1" level via the OR gate 719, immediately followed by deactivation of the memory unit 60.

In the embodiment under consideration, the reproduction is automatically effected after recording to confirm the recording. The reproduction operation will be described. Following the recording operation mentioned above, the automatic reproduction signal 70j is "1", and therefore the write control signal 70f takes a level "1", thus prohibiting another recording. And the tri-state latch 713 and the tri-state gate 714 stop the latching and gating operations, whereas the latch and gating operation of the tri-state latch 720 and the tri-state gate 721 respectively are made possible.

In other words, the counter 701 still continues to divide the frequency of the clock signal 70b and therefore both the operation of A/D conversion and the generation of the address counting pulse signal 70i in the memory control circuit 70C are repeated (FIGS. 3(1) to 3(6)). In this case, the converting operation of the converter circuit 20 is meaningless, and this converter circuit 20 is used for determining the timing of generating at intervals of 3 KHz the address count pulses 70i (FIG. 3(6) for updating the addresses of the memory unit 60. The frequency-divided signals Q.sub.3 and Q.sub.4 (FIGS. 3(1) and 3(2) of the counter are partly reversed with the same phase and applied to the tri-state latch 720 and the tri-state gate 721 as control signals 70t, 70r and 70s thereof (FIGS. 3(8), 3(9) and 3(10)).

In view of the fact that the tri-state latch 720 and the tri-state gate 721 are impressed with memory data (voice digital data) updated and produced at intervals of 3 KHz in the 8-bit input-output signal line of the memory unit 60, low significant voice digital data A and high significant voice digital data B are applied 4 bits at a time from the tri-state gate 721 and the tri-state latch 720 in that order to the D/A converter circuit 30. Thus the D/A converter 301 accomplishes the D/A converting operation at the same timing as the A/D conversion of the A/D converter 201, thus producing a voice signal as a voltage value.

The sampling noise of this voice signal is cut by the low-pass filter 40, and the particular signal is amplified by the amplifier circuit 50, followed by the reproduction through the speaker 2.

After completion of reproduction, when the memory addresses are filled up and all the count values of A.sub.12, A.sub.13 and A.sub.14 take "1", the reproduction end signal 70k takes "1" and is applied to the one-shot multivibrator 22 of the mode determining circuit 70B. In response to this, the one-shot multivibrator 722 produces a pulse signal 70u of about 20 .mu.s and resets the flip-flops 702 and 705. By the resetting of the flip-flop 702, the counters 701, 706 and 707 are reset, thus providing a stand-by state. In this way, reproduction is automatically effected and confirmed by the user after recording.

Subsequently, it is also possible to reproduce the stored data when desired. Specifically, when the confirmation switch P is closed, the flip-flops 702 and 705 are set. By the setting of the flip-flop 702, the reset state of the counters 701, 706 and 707 is cancelled. By the setting of the flip-flop 705, on the other hand, the write control signal 70f is maintained at "1" (namely, fixed at the read mode). As in the case of reproduction mentioned above, the counting operation of the counter 701 updates the stored count values of the counters 706 and 707, in synchronism with which the latch 720 and the gate 721 are activated. As a result, the stored data are sequentially read out, and through D/A conversion, noise cut and amplification processes, are reproduced from the speaker 2. In this case, the reproduction is effected until all the count values A.sub.12, A.sub.13 and A.sub.14 take "1", that is, only twice. And the stand-by state is again restored at the timing when the reproduction end signal 70k takes "1".

As described above, the memory unit 60 is supplied with power regardless of the operating state of the key switch 4, and therefore the stored data are maintained even after the key switch 4 is opened.

When the same user or another user closes the key switch 4 after the opening thereof, the reproduction of the data thus kept stored is automatically started. This operation is shown in FIG. 4.

Assuming that the key switch 4 is closed again, the voltage regulator 801 generates a predetermined voltage, so that a sensor circuit 724 including a time constant circuit due to the capacitor C.sub.1 and R.sub.1 produces a "1" level detection signal 70d of about 2 s. (FIG. 4(1)) In response to the fall of the detection signal 70d, the one-shot multivibrator 725 produces a pulse signal of about 20 .mu.s (FIG. 4(2)), thus setting the flip-flops 702, 704 and 705. (The time constant due to the capacitor C.sub.2 and the resistor R.sub.2 of the power-on pulse generator circuit 708 is smaller than that due to the capacitor C.sub.1 and the resistor R.sub.1). By the setting of the flip-flops 702 and 705, the reproduction is effected twice as in the case of the closing of the confirmation switch P as described above.

In this way, the new user is informed of the voice data stored by the preceding user in the memory unit as a message.

After repetition of two announcements of the message, the reproduction end signal 70k is applied to the one-shot multivibrator 722 as mentioned above, and this one-shot multivibrator 722 resets the flip-flops 702 and 705. In view of the fact that the flip-flop 704 is still set (FIG. 4(5)), however, the flip-flop 702 alone is set again. In other words, the A/D conversion and storage are effected as in the case where the recording switch R is closed. No voice is supplied from the microphone 1, and therefore the voice digital value stored already in the memory unit 60 is substantially erased. The flip-flop 704 commanding the recording (erasure) is reset by the signal 70x generated at the time of another setting of the flip-flop 702, and therefore only one recording (erasure) is effected. And after another reproduction, the apparatus enters a stand-by state.

As explained above, after the key switch 4 is closed, the message is reproduced and announced twice, and then automatically erased.

In the foregoing described embodiments, the message is automatically erased after reproduction. As an alternative, if the flip-flop 704 is eliminated, the message may be repeated after the closing of the key switch.

Means responsive to the start of operation of the motor vehicle may include a switch responsive to the seating of the driver or a door open switch instead of the key switch 4 and the sensor switch 724.

Further, in place of the memory unit used in the above-mentioned embodiments, a memory unit such as a magnetic disc, a magnetic drum or a magnetic tape or a non-volatile semiconductor memory unit which does not require any back-up of a power supply may be used. Such a magnetic tape, drum or disc is capable of storing the voice signal as an analog signal.

It will be understood from the foregoing description that according to the present invention a voice message is capable of being transmitted from a user to the next user through the stationary condition of the vehicle involved.