Field Recognition Circuit

This invention relates to an apparatus for recognizing whether a field is an odd line field or an even line field of an interlaced composite video signal. More particularly, this invention relates to an apparatus for multiplexing two video signals at the field rate or decoding the multiplexed signal at the field rate (e.g. for use with signal associated with a stereoscopic television system employing alternate fields for left and right stereoscopic images and employing a PLZT viewer). The stereoscopic television system employing alternate fields for left and right eye images, which is the principal object of this invention, needs synchronization between the left and right eye images and the viewer's shutter operation. If the system falls out of sync so that the left eye image is shown to the right eye and the right eye image is shown to the left eye, the image perceived is confusing and not truly stereoscopic.

In most conventional methods of synchronization, the driving pulse of the viewer is triggered by a T-type flip-flop which is triggered by the vertical sync pulse derived from the composite video signal, but there is no way to define which field is which. In another method of synchronization, a discernible signal which is inserted in the vertical interval of the video signal prevents free editing of a video tape storing such a signal because of the fact that the discernible signal fades away after editing.

Yet another method of synchronizing by coincidence of the horizontal sync pulses with the pulses derived from the vertical sync signal cannot be expected to provide stable operation because of the critical adjustment required and its dependence upon temperature. (c.f. U.S. Pat. No. 4,145,713)

Therefore, there is a continuing need for an improvement for a stereoscopic television system which assures the identity of the odd and even line field.

This invention is directed to provide a means for the construction and viewing of the field sequential stereoscopic images and a multiplexed video signal in a stereoscopic television system. After receiving the composite video signal, the means derives the field recognition pulses and outputs them to the viewing devices. Therefore, the imaging stereoscopic images left and right eye signals can be multiplexed exactly, and when viewing, the shutter can operate surely so that the left eye image is always associated with the left eye and the right eye image is always associated with the right eye.

An object of this invention is an improvement of the stereoscopic television system.

Another object is to provide a circuit for recognizing the field from the composite video signal.

Yet another object is to make possible a stereoscopic television system which is compatible with a conventional video signal.

These and other objects of the invention will become more apparent from the following description when taken with the drawings in which:

FIG. 1 is a block diagram of the representative stereoscopic television system;

FIG. 2 is a circuit diagram of the invention;

FIG. 3 is another circuit diagram of the invention; and

FIG. 4 shows a timing diagram of a circuit of the present invention.

Referring now to the drawings, FIG. 1 shows a typical stereoscopic television system. Field recognition circuit 5 assures synchronization in this stereoscopic television system. Video signals from cameras 1 and 2, which are synchronized by sync generator 3, are multiplexed in a field-by-field fashion in multiplexer 4 by means of the field identified pulses from field recognition circuit 5 so that the left camera signal is assigned to an odd line field and the right camera signal is assigned to an even line field. The multiplexed signal is a conventional video signal; and through medium 6, which may correspond to standard broadcast transmission lines or video tape recorders and such other mediums, the signal is connected to a video monitor 7.

The multiplexed video signal is also fed to the field recognition circuit 8 which generates field identified pulses and drives the PLZT viewer 10 with driving circuit 9. The PLZT viewer 10 closes and opens synchronously in a field by field fashion with pulses derived from the field recognition circuit 8. Therefore, true stereoscopic images can be seen.

FIG. 2 depicts a detailed drawing of the field recognition circuits 5 and 8 in FIG. 1, and FIGS. 4(a) and 4(b) show the timing diagrams (FIG. 4(a) shows the odd line field and FIG. 4(b) shows the even line field).

Referring to FIG. 2 and FIG. 4(a) with respect to an odd line field, an input video signal is connected to sync separator means 11, and the derived composite sync pulse train A is shown in FIG. 4(a). From composite sync pulse A, a non-retriggerable monostable multivibrator 12 (this is one of the horizontal pulse deriving means) having typical pulse width T of 3/4 H (H refers to the horizontal scanning period) derives a continuous horizontal pulse train B. Because the monostable multivibrator 12 has the typical pulse width of 3/4 H, it is triggered by the rising edge of the composite sync pulse train A, but is not triggered by the equalizing pulses which are located between the horizontal sync pulses. Composite sync pulse train A is sampled at the rising edge of horizontal pulse train B by a D-type flip-flop 13 (e.g. Motorola Corporation's MC14013B) which is one of the first phase detector means, and derives the first vertical sync pulse C as shown in FIG. 4(a), which is typically delayed 3/4 H from the original vertical sync. The pulse width of the monostable multivibrator 12 is permitted to be between 1/2 H and H, and the rising edge of the pulse is in the period of the high level of the composite sync pulse train A as shown in FIG. 4(a).

On the other hand, composite sync pulse train A is integrated by the R-C filter (resistor 16 and capacitor 17) as waveform D in FIG. 4(a), and derives the second vertical sync pulse E which is typically delayed 1/2 H by a Schmitt trigger 18 and inverter 19. This vertical sync separator means 15 provide a 1/2 H delay for the vertical sync. The second phase detector means comprises a D-type flip-flop 14 which detects the phase difference between the two vertical sync pulses C and E (in this case pulse C is used for the clock input and pulse E is used for the data input), and derives a field identified pulse F changing from a Low to a High level. Now, since this D-type flip-flop is employed only as a phase detector, the two input signals can be connected to either the clock or data inputs. If connecting inversely to that shown in FIG. 2, for example, the field identified pulse F also inverts the output levels thereof.

Next, referring to FIG. 4(b) with respect to an even line field, the operations are almost same as those of FIG. 4(a) referred to above, but the first vertical sync pulse C sampled by the horizontal pulse train B is typically delayed 1/4 H from the original vertical sync signal. The second vertical sync pulse E is typically delayed 1/2 H as above, so that D-type flip-flop 14 derives the field identified pulse F changing from a High to a Low level. Because the first vertical sync pulse C which is sampled by the horizontal pulse train B has a delay time which is different by 1/2 H between odd line fields and even line fields, the delay time of the second vertical sync pulse E can be adjustable so as to be in the middle of that time. For use as the non-retriggerable monostable multivibrator 12, two units of a quad 2-input NOR gate (e.g. Motorola Corporation's MC14001B) are also applicable.

FIG. 3 shows another example circuit of this invention. The timing diagram of this circuit is the same as FIGS. 4(a) and 4(b). The difference from FIG. 2 is in the vertical sync separator means 15 which operates as a 1/2 H delay line for the vertical sync.

The composite sync pulse train A is connected directly to the clock input of the D-type flip-flop 20 and is also connected to the data input via an R-C filter with a time constant within 1/2 H. The data input D, as shown in FIG. 4 is latched by the rising edge of the composite sync pulse train A, and the D-type flip-flop 20 outputs the second vertical sync pulse E which is delayed 1/2 H from the original vertical sync.

Since the rising edge of second vertical sync pulse E is regulated by the rising edge of the composite sync pulse train A, the time constant of the R-C circuit is halved in this circuit, and improved operation is expected.

Obviously, many modifications and variations of the present invention are possible in the light of the above teachings, and it is therefore understood that the invention can be practiced otherwise than as specifically described.