Space Diversity Receiver With Means for Combining Signals From the Two Channels

1. Field of the Invention

This invention relates in general to space diversity receivers wherein the useful signals of the two receiving branches are combined in a summing circuit in the IF frequency range and in which an electronically controlled phase corrector is mounted in one of the receiving branches and a phase monitoring circuit is connected at the output of the phase corrector between the two receiving branches with the output signal of the phase monitoring circuit controlling the phase corrector.

2. Description of the Prior Art

In space diversity reception, there is a problem in that the two signals of identical frequencies must be summed in the proper phase. Such summation can occur in the radio frequency, intermediate frequency or base-band frequency stages. Thus, there are RF, IF or BF combiners. If the combination occurs in the radio frequency or intermediate frequency stages, then a variable phase corrector must be used to assure that the phase differences between the two received signals caused due to changing propagation conditions are sufficiently equalized. Thus, it is a problem to provide the so-called infinite phase corrector or goniometer with electronic means and automatic control of the phase corrector.

A radio frequency combiner is discussed in the article entitled "Elektronisches Raumdiversity-System fur Richtfunkanlagen" by U. H. Gysel which was published at the NTG conference for directional radio from Apr. 23 to Apr. 25, 1980, and which paper is dated Apr. 4, 1980.

An IF combiner is discussed in the report entitled "New Generation 6 GHz 1800 Channel/78 Mbits Radio System" by T. Furuya et al which was presented at the European Microwave Conference in 1978.

The present invention provides a space diversity receiver with IF combiner having the least possible electrical interference.

With a space diversity receiver of the type described above, the present invention achieves that the phase monitoring circuit consists of a phase discriminator to which the signal from one receiving branch is supplied through an automatically controlled amplifier without additional phase angle rotation and the signal coupled from the other reception branch is supplied through an identical automatically controlled amplifier and a 90-degree phase angle rotation element. The output signal of the phase discriminator is supplied to a comparator which depending on the direction of the phase deviation controls the counting direction of a forward/backward counter. The output of the phase discriminator is also supplied to a square law transfer element and depending on its absolute value, determines the clock frequency of a clock generator which drives the forward/backward counter. A memory receives the output of the forward/backward counter and controls the position of the phase corrector which can be set step-by-step to different correction angles which angles are determined by the output of the forward/backward counter.

Other objects, features and advantages of the invention will be readily apparent from the following description of certain perferred embodiments thereof taken in conjunction with the accompanying drawings, although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure, and in which:

FIG. 1 is a block diagram illustrating a space diversity receiver with IF combiner;

FIG. 2 is a block circuit diagram of the digital phase corrector;

FIG. 3 is a partial illustration of the phase corrector according to FIG. 2; and

FIG. 4 is a graph illustrating the individual phase correction steps according to the invention.

The two paths of the receiving signals in the space diversity receiver illustrated in FIG. 1 are indicated as I and II. In other words, these signals have been detected by space diversity receivers having antennas located at different locations and have been supplied in the radio frequency band with the levels Pe1 and Pe2 at the two input terminals. The first receiving path comprises a first receiving mixer or converter M1 followed by a preamplifier which receives an output of an oscillator G through a 3 dB coupler K. The second channel passes through the mixer converter M2 which is followed by a preamplifier and the converter/mixer M2 receives output of the oscillator G through the 3 dB coupler K. The output IF signal from the mixer/converter M1 passes through a IF cable having a transit time of .tau.0 which is in series between the converter mixer and the electronic phase corrector P. The transit time of the cable equalizes the differences in the length of the antenna feeds to the different receivers as well as corrects for the transit time through the phase corrector P. It can be assumed that the longer antenna feed line is connected to input II and that the difference of length is greater than the electrical length of the phase corrector P. A branching circuit A1 receives the output of the electronic phase corrector P and supplies an input to an amplifier V1 which supplies an output to a circuit breaker S1 which supplies an input to a summing circuit S. The second branching circuit A2 receives the output of the converter mixer M2 and supplies an input to an amplifier V2 which supplies an output to a circuit breaker circuit S2 which supplies its output to the summing circuit. The output of the summing circuit S is connected to a suitable IF output which also would include suitable detectors as in standard receivers wherein the intelligence is detected and supplied for useful purposes.

A phase monitoring circuit contains an automatically gain controlled amplifier RV1 which receives an output of the branching circuit A1 and supplies an output to a 90-degree phase shift circuit which has its output connected to a phase discriminator or detector D1. A second automatic gain control circuit RV2 receives the output of the branching circuit A2 and supplies an input to the phase discriminator/detector D1. The output of the phase detector/discriminator D1 is connected to a comparator KO which depending on the direction of the phase deviation controls the direction of counting of a forward/backward counter Z. The output of the phase discriminator D1 is also supplied to a square law transfer circuit QS and depending on the absolute value of the output determines the clock frequency of the clock generator T which drives the forward/backward counter Z. The clock generator T may be a voltage controlled oscillator (VCO). With small phase deviations, the voltage controlled oscillator VCO is switched off. When the larger phase deviations occur, the frequency increases with increasing phase deviations. The output of the forward/backward counter Z is connected to a memory SP which may be of a PROM type which supplies an output to the electronic phase corrector P so as to control its phase shift in a step-by-step manner.

A second phase discriminator D2 receives outputs of the two amplifiers RV1 and RV2. The output of the phase discriminator D2 provides outputs to control the circuit breaker circuits S1 and S2. An output monitoring signal Us is supplied from the logic circuit L to a signal and error display monitoring means. The control voltages from RV1 and RV2 drive the logic circuit L.

The phase corrector P is controlled with the memory SP, the counter Z, the clock generator D, the square law transfer circuit QS, and the comparator KO. Thus, phase changes of the radio field of any desired size can be corrected in a step-by-step manner. The phase corrector can be adjusted such that independently of the phase of the two incoming radio frequency signals, the phase between the signals at the summing circuit S remain approximately constant. If the two signals at the summing circuit have phase identity, the phase discriminator D1 will supply an output voltage of 0.

The memory SP which may be a PROM, is driven by the forward/backward counter Z which counts, for example, from 0 through 55. By applying the clock signal of the clock generator T to the counter circuit Z, the signal phase can be shifted step-by-step in both directions by any desired phase angle. Thus, the clock frequency of the clock generator T (VCO) is controlled, depending on the size of the phase deviation. The counting direction is controlled by the comparator KO. The control is shut off in certain phase ranges as, for example, +5.degree. in that the oscillation of the clock generator T is shut off for given small phase deviations.

The second phase discriminator D2 in the phase monitoring circuit monitors the absolute phase difference between the useful signals. If, for example, because of a device malfunction, the phase deviation becomes too great, for example greater than +60.degree., then the path in which the phase corrector P is mounted will be blocked. This occurs due to the action of the logic circuit L which is connected to the phase discriminator D2 with the logic circuit L having its output connected to the circuit breaker S1 which is in the receiving branch containing the phase corrector P.

In case the input power of the two receiving branches becomes different by an amount greater than 8 dB, the logic circuit L controlled by the control voltages RV1 and RV2 will cause the receiving branch with the smaller input power to be blocked due to disconnection in the circuit breakers S1 or S2 so as to prevent deterioration of the signal-to-noise ratio and the output of the summing circuit.

The phase corrector can be set in discrete steps by using diode switches. This has the advantage that the phase corrector connected in the signal path consists essentially of nothing but linear components which do not distort the signal even at its maximum amplitude. It is also advantageous that the digital phase corrector can be directly driven by the digital control electronics without the use of digital/analog converters.

FIG. 2 illustrates a basic circuit diagram of the phase corrector P. The diode switches are illustrated as relay contacts. The phae corrector consists of a 0.degree./90.degree. 3 dB coupler K1 which is capable of splitting the signal into two components of identical amplitude which are shifted by 90.degree., so that one has a 0.degree. and the other has a 90.degree. reference. A pair of 0.degree./180.degree. phase shifters P1 and P2 are respectively connected to the 0.degree. and 90.degree. outputs of the coupler K1 through switches x.sub.S and y.sub.S, as shown. At the output of the phase shifter P1 a switch x.sub.0 is connected to select 0.degree. or 180.degree. outputs. A switch y.sub.0 is connected at the output of the phase corrector P2 to select the 0.degree. to 180.degree. output. A first resistive network comprising resistors R1, R2, R3, and switches x1, x2 and x3 connected as shown, is connected to the output of switch x.sub. O. A second resistive network comprising switches y1, y2 and y3 and resistors R1', R2' and R3' is connected to the output of switch y0. A summing circuit SM is connected to the output of the resistive networks and provides the summed output.

The resistors R1, R2 and R3, as well as the resistors R1', R2' and R3' have the ratio of 1:2:4 and thus by closing the switches x1, x2, x3 or y1, y2, y3, the signals can be set to eight practical identical amplitude stages comprising 0, 1, 2, 3, 4, 5, 6, and 7. In this manner, the phase steps can be made as small as possible, as are the changes of the amplitude which occur so that approximation of a circular form can be achieved. The two weighted signals are again added, and form a summed signal which according to the setting of the various diode switches can be shifted in phase in discrete steps between 0.degree. and 360.degree.. The change of amplitude is smaller than .+-.0.6 dB. The switches x.sub.S and y.sub.S therefore cause a blockage of the x or, respectively, of the y signals and improve the opening of the diode switches x.sub.1, x.sub.2, x.sub.3 or, respectively, y.sub.1, y.sub.2, y.sub.3 in the resistor networks. The switches x.sub.S and y.sub.S are sequence switches which are only opened when the amplitude stage 0 of the x or, respectively, of the y path is to be utilized.

FIG. 3 is a partial illustration of a branch of the phase corrector showing how the diodes Di1, Di2 and Di3 are connected in series with the resistors R1, R2 and R3 of the resistor network. An interface IN is controlled by the memory SP. The interface contains change-over for selectively connecting a negative voltage of, for example 24 volts or a positive voltage of, for example, 5 volts to the switching circuit through RC element to the individual diodes Di1, Di2 and Di3 so that the diodes will function as switches to allow a signal to be blocked or pass therethrough. The resistance R and capacitance C connected as shown causes the change-over from blocking to pass of the diode switches not to be abrupt but allows a steady transition to be accomplished. This prevents noise peaks. A coupling resistor RE is connected between the RC components to each of the resistors R1, R2 and R3, respectively, and comprises a decoupling resistor. Capacitors C.sub.K are connected to each of the resistors R1, R2 and R3, respectively, and comprise coupling capacitors.

FIG. 4 is a diagram illustrating how the phase can be changed in steps with the corresponding amplitude changes. In the present example, the largest phase step is .DELTA..phi. which is the arc tg 1/7, or approximately 8.degree.. A total of 56 phase steps are provided over 360.degree., and these are numbered from 0 (equal 56) through 55. The 56 different positions of the diode switches are stored in the memory SP, and can be recalled by using the addresses 0 through 55. It is advantageous that with given successive steps of the phase corrector, that only one respective motion in a single direction x or y occurs, and thus, the x and y vectors need not change simultaneously.

It is seen that relative to the vector diagram of FIG. 4 that with the switch x.sub.0 set to receive the 0.degree. output of the phase comparator P1 and the switch y.sub.0 set to receive the 0.degree. output of the phase comparator P2, that the phase shifts illustrated between 0.degree. and 90.degree., or a total of 14 different phase shifts can be obtained. If the switch x.sub.0 continues to receive the 0.degree. output of the phase comparator, but the y.sub.0 switch is set to receive the 180.degree. output of the phase comparator P2 by adjusting the switches x1, x2, x3 and y1, y2 and y3, the positions between 15 and 28 illustrated in FIG. 4 can be obtained, wherein the x signals are positive and the y signals are negative. The other quardants can be obtained, for example, to obtain the positions 29 through 42 by providing that both switches x0 and y0 receive the 180.degree. outputs of the phase comparators P1 and P2. Positions 43 through 55 can be obtained by providing the 0 output on switch y.sub.0, and the 180.degree. output on switch x.sub.0.

It will be apparent to those skilled in the art that many modifications and variations may be effected without departing from the spirit and scope of the novel concepts of the present invention.