System for Reducing Access Time to Plural Memory Modules Using Five Present-Fetch and One Prefetch Address Registers

The present invention relates to a system for accessing memory modules and, more particularly, to a system for accessing memory modules by using an effective address which is composed of two or more parts, one of which is determined later than the others.

In general, in computer systems, address modification, which changes an address written in a program to an effective address which is actually used for accessing memory modules, has been known and carried out. The address modification is effected by means of a modifier, such as an address mapper or an address modification table. In a small scale computer system, such as a microcomputer system, the number of bits of an effective address is larger than that of an address written in a program. Contrary to this, in a large scale computer system, the number of bits of an effective address is smaller than that of an address written in a program. In any computer system, the lower order bits of an address written in a program serve as a part of an effective address without modification, while the other higher order bits of the address written in the program are changed to the other part of the effective address by a modifier. Therefore, one part of the effective address is determined later than the other part thereof.

In one prior art system for accessing memory modules by using an effective address, one part of which is determined later than the other part thereof, after the entire effective address is determined, the access operation for the memory modules is actually executed. Therefore, the total access time is composed of an address modification time and the actual access time, which means that the speed of access of the memory modules is low.

It is a principal object of the present invention to provide a system for accessing memory modules by using an effective address, one part of which is determined later than the other part thereof, with high speed access.

According to the present invention, the average time for accessing memory modules can be reduced by relying on the fact that successive access operations are very frequently executed on the same memory module. Because of this it is advantageous to begin an access operation when the row address portion of an effective address is available, without waiting until the column address and module designation portions of the effective address have been determined. This can be accomplished by providing a first memory address register for storing the column address and module designation portions of the current effective address, a second memory address register for storing the row address portion of the current effective address, and a third memory address register for storing the module designation portion of the prior effective address. The access operation is begun using the module designation portion of the prior effective address, which is stored in the third memory address register, and the row address portion of the current effective address, which is stored in the second memory address register. After the module designation and column address portions of the current effective address are available, a comparator circuit which is connected to the first and third memory address registers determines whether the current and prior effective addresses designate the same memory module. Assuming that the same module is designated, the access operation is completed using the column address portion of the current effective address. In the event that the designated modules are different, however, the modules are accessed again using the module designation, row address, and column address portions of the current effective address. Since the current and previous module designations are very frequently identical, the net result is that the average access time does not reflect the actual address modification time needed for transforming a program address into an effective address.

The present invention will be more clearly understood from the following description with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating the system for accessing memory modules of the prior art;

FIG. 2 is a block diagram of the memory module 47-i (i=0 through 31) of FIG. 1;

FIGS. 3(1) through 3(6) are timing diagrams showing the signals appearing in the circuits of FIGS. 1 and 2;

FIG. 4 is a block diagram illustrating an embodiment of the system for accessing memory modules of the present invention;

FIG. 5 is a block diagram of the control circuit 42' of FIG. 4;

FIG. 6 is a block diagram of the memory module 47'-i (i=0 through 31) of FIG. 4;

FIGS. 7(1) through 7(9) are timing diagrams showing the signals appearing in the circuits of FIGS. 4, 5 and 6; and

FIGS. 8(1) through 8(7) are block diagrams of the memory address registers 41-1, 41-2 and 41-3, for explaining the operation of the circuits of FIGS. 4, 5 and 6.

In FIG. 1, a central processing unit (hereinafter referred to as a CPU) 1 and a channel control unit (hereinafter referred to as a CHC) 2 serve as access sources for a memory unit 4 through a memory access control unit (hereinafter referred to as a MAC) 3. First, an address code of sixteen bits is transmitted from an address register 11 or 21 of the CPU 1 or CHC 2 of the MAC 3. In this case, the lower order seven bits of the address code are supplied to an address buffer 32 of the MAC 3 which produces seven signals MA12 through MA18, as indicated shown in FIG. 3(2), without modification, while the higher order nine bits of the address code are supplied to an address mapper 31 of the MAC 3, which produces twelve signals MA00 through MA11, as indicated in FIG. 3(1). In FIG. 3(1), T1 is the time which is necessary for modifying nine bits of the address code to the twelve signals MA00 through MA11. At time t.sub.0, the signals MA12 through MA18 are supplied to a memory address register (hereinafter referred to as a MAR) 41-2 of the memory unit 4 and, after that, at time t.sub.1, the signals MA00 through MA11 are supplied to a MAR 41-1. At the same time, a memory starting signal MSTA is supplied from a control circuit 33 of the MAC 3, which is also controlled by a control circuit 12 or 22 of the CPU 1 or CHC 2, to a control circuit 42 of the memory unit 4, as indicated in FIG. 3(3). The five signals MA00 through MA04 are supplied to a decoder 43 for selecting one module from thirty-two memory modules 47-0 through 47-31. On the other hand, the seven signals MA12 through MA18 are transmitted from the MAR 41-2 to the selected memory module and, after that, at time t.sub.2, the seven signals MA05 through MA11 are transmitted from the MAR 41-1 to the selected memory module, as indicated in FIG. 3(4). Such time divisional transmission is effected by a multiplexer 44 which is controlled by a control circuit 46, which receives the control signal MSTA through a delay circuit 45 whose delay time is T2, and each of the memory modules 47-0 through 47-31 has address input pins common for the signals MA05 through MA11 and the signals MA12 through MA18. It should be noted that the address mapper 31 comprises a random access memory (RAM) from which is read out data of twelve bits by using an address code of nine bits.

FIG. 2 is a block diagram of the memory module 47-i (i=0 through 31) of FIG. 1. In the memory module, two control signals TRAS and TCAS are supplied from the control circuit 42 (FIG. 1). In other words, the control signal TRAS is the same as the control signal MSTA, while the control signal TCAS is obtained by delaying the control signal MSTA. The delay time T3 (FIG. 3) is determined by a delay circuit 421. In the selected memory module, the potential of a control signal from the decoder 43 is high, so that a row access signal *RAS is the same as a control signal TRAS (the signal TRAS inverted) through a gate G1 as indicated in FIG. 3(5) and a column access signal *CAS is the same as a control signal TCAS (the signal TCAS inverted) through a gate G2 as indicated in FIG. 3(6). As a result, the signals MA12 through MA18 are applied to a cell array 471 in syncronization with the control signal *RAS and, after that, the signals MA05 through MA11 are applied to the cell array 471 in syncronization with the control signal *CAS.

However, in the system of FIGS. 1 and 2, the total access time T5 (FIG. 3) is determined by the sum of the modification time T1 and the actual access time T4, which means that the access speed is low.

FIG. 4 is a block diagram illustrating an embodiment of the system for accessing memory modules of the present invention. The elements illustrated in FIG. 4 which are identical to those of FIG. 1 are denoted by the same reference numerals. In FIG. 4, the control circuit 33' of the MAC 3 produces two kinds of memory starting signals MSTA1 and MSTA2. The memory unit 4 comprises three MARs 41-1, 41-2 and 41-3, two decoders 43-1 and 43-2, and a comparator circuit 48. In addition, the control circuit 42' of the memory unit 4 produces three kinds of control signals TRAS1, TRAS2 and TCAS. The control circuit 42' will now be explained in more detail.

FIG. 5 is a block diagram of the control circuit 42' of FIG. 4. In FIG. 5, the control circuit 42' comprises two control circuits 422 and 423 used mainly for refreshing dynamic memories, such as memory modules 47'-0 through 47'-31, two gates G3 and G4 controlled by the comparator circuit 48 (FIG. 4), two delay circuits 424 and 425 whose delay time is T3 and a gate G5. Assume that the potentials of two signals C1 and C2 are low, so that the gates G3 and G4 are closed. When the potential of the signal MSTA1 becomes high, the signal TRAS1 also becomes high. After that, when the potential of the control signal MSTA2 becomes high, the comparator circuit 48 (FIG. 4) begins to operate, so that the comparator circuit 48 raises either the potential of the signal C1 or the potential of the signal C2. For example, when the potential of the signal C1 becomes high, the potential of the signal TCAS becomes high. In this case, the signal TCAS is obtained by delaying the signal TRAS1 due to the presence of the delay circuit 424, whose delay time is T3. Contrary to this, when the potential of the signal C2 becomes high, the potential of the signal TRAS2 becomes high and, after that, the potential of the signal TCAS becomes high. In this case, the signal TCAS is obtained by delaying the signal TRAS2 due to the presence of the delay circuit 425, whose delay time is also T3. In summary, when the potential of the signal C1 is changed from low to high, the pontentials of the signals TRAS1 and TCAS become high, sequentially. Contrary to this, when the potential of the signal C2 is changed from low to high, the potentials of the signals TRAS1, TRAS2 and TCAS become high, sequentially.

FIG. 6 is a block diagram of the memory module 47'-i (i=0 through 31) of FIG. 4. The memory module 47'-i comprises a gate G6 for receiving signals from the decoders 43-1 and 43-2 (FIG. 4), two gates G7 and G8 for passing the signals TRAS1 and TRAS2, respectively, a gate G9 for generating a signal *RAS to a cell array 471 and a gate G10 for passing the signal TCAS. For example, when the memory module 47'-i is selected by the decoder 43-2 but not by the decoder 43-1, the signal TRAS1 passes through the gates G7 and G9, so that the signal *RAS is the same as TRAS1 (the signal TRAS1 inverted). After that, if the memory module 47'-i is not selected by the decoder 43-1, the signal TCAS is blocked by the gate G10. However, if the memory module 47'-i is selected by the decoder "43-1, the signal TCAS passes through the gate G10, so that the signal *CAS is the same as an inverted signal of the signal TCAS. Contrary to this, when the memory module 47'-i is selected by the decoder 43-1, the signal TRAS2 passes through the gates G8 and G9, so that the signal *RAS is the same as TRAS2 (the signal TRAS2 inverted). After that, the signal TCAS passes through the gate G10, so that the signal *CAS is the same as TCAS (the signal TCAS inverted). The operation of the circuits of FIGS. 4, 5 and 6 will now be explained.

FIGS. 7(1) through 7(9) are timing diagrams indicating the signals appearing in the circuits of FIGS. 4, 5 and 6. In more detail, these figures are as follows.

FIG. 7(1) indicates the signals MA00 through MA11, which are from the address mapper 31;

FIG. 7(2) indicates the signals MA12 through MA18, which are from the address buffer 32;

FIGS. 7(3) and 7(4) indicate the memory starting signals MSTA1 and MSTA2, respectively, which are from the control circuit 33';

FIG. 7(5) indicates the signals that are from the multiplexer 44;

FIGS. 7(6) and 7(7) indicate the signals *RAS and *CAS in the memory module 47'-2, and;

FIGS. 7(8) and 7(9) indicate the signals *RAS and *CAS in the memory module 47'-1.

FIGS. 8(1) through 8(7) are block diagrams of the memory address registers 41-1, 41-2 and 41-3, for explaining the operation of the circuits of FIGS. 4, 5 and 6. Referring to FIGS. 7(1) through 7(9) and FIGS. 8(1) through 8(7), the operations of the circuits of FIGS. 4, 5 and 6 are as follows.

(1) As indicated in FIG. 8(1), the higher order five bits (00010) of an address code used in a previous access have been transmitted from the MAR 41-1 to the MAR 41-3.

(2) As indicated in FIGS. 7(2), 7(3) and 8(2), the signals MA12 through MA18 (0110101) are transmitted from the address buffer 32 of the MAC 3 to the MAR 41-2 of the memory unit 4 and, simultaneously, the signal MSTA1 is transmitted from the control circuit 33' of the MAC 3 to the control circuit 42' of the memory unit 4. As a result, the data (0110101) is stored in the MAR 41-2 and, after that, is transmitted through the multiplexer 44 to all the memory modules 47'-0 through 47'-31 as indicated in FIG. 7(5). Since the data stored in the MAR 41-3 is (00010), the memory module 47'-2 is selected by the decoder 43-2, so that the signal TRAS1 is changed to the signal *RAS in the memory module 47'-2 as indicated in FIG. 7(6). Thus, the memory module 47'-2 is accessed by the signals MA12 through MA18 as indicated in FIGS. 7(5) and 7(6).

(3) As indicated in FIGS. 7(1), 7(4) and 8(3), the signals MA00 through MA11 (000011010011) are transmitted from the address mapper 31 of the MAC 3 to the MAR 41-1 of the memory unit 4 and, simultaneously, the control signal MSTA2 is transmitted from the control circuit 33' of the MAC 3 of the control circuit 42' of the memory unit 4. As a result, the data (000011010011) is stored in the MAR 41-1 and, after that, the higher five bit data (00001) of the MAR 41-1 is compared with the data (00010) stored in the MAR 41-3 by the comparator circuit 48. As a result of this, since the data stored in the MAR 41-3 is different from the data (00001), the comparator circuit 48 raises the potential of the signal C2, so that the control circuit 42' produces the signal TRAS2 and, after that, produces the signal TCAS. However, in the memory module 47'-2, the signals TRAS2 and TCAS are blocked by the gates G8 and G10 of FIG. 6, respectively, since the module 47'-2 is not selected by the decoder 43-1. As a result, the signal *CAS remains high, as indicated in FIG. 7(7), and accordingly, the access operation for the memory module 47'-2 is not completed. On the other hand, in the memory module 47'-1, the signal TRAS2 passes through the gates G8 and G9, so that the potential of the signal *RAS is changed from high to low, as indicated in FIG. 7(8), since the module 47'-1 is selected by the decoder 43-1. Therefore, the memory module 47'-1 is accessed by the data MA12 through MA18. After that, the signal TCAS also passes through the gate G10, so that the potential of the signal *CAS is changed from high to low, as indicated in FIG. 7(9). Simultaneously, the multiplexer 44 transmits the data MA05 through MA11 instead of the data MA12 through MA18 at time P1, as indicated in FIG. 7(5), which time is determined by a delay circuit 45 whose delay time is T2 and a control circuit 46. Therefore, the memory module 47'-1 is accessed by the data MA05 through MA11. Thus, the access operation for the memory module 47'-1 is completed. In this case, the total access time for the memory module 47'-1 is indicated by T6 in FIG. 7(9).

(4) As indicated in FIG. 8(4), the data (00001) stored in the MAR 41-1 is transmitted to the MAR 41-3. Next, the access operation for the memory module 47'-1 is again effected.

(5) As indicated in FIGS. 7(2), 7(3) and 8(2), the signals MA12 through MA18 (0110110) are transmitted from the address buffer 32 of the MAC 3 to the MAR 41-2 of the memory unit 4 and, simultaneously, the control signal MSTA1 is transmitted from the control circuit 33' of the MAC 3 to the control circuit 42' of the memory unit 4. As a result, the data (0110110) is stored in the MAR 41-3 and, after that, is transmitted through the multiplexer 44 to all the memory modules 47'-0 through 47'-31. Since the data stored in the MAR 41-3 is (00001), the memory module 47'-1 is selected by the decoder 43-1, so that the signal TRAS1 is changed to the signal *RAS in the memory module 47'-1, as indicated in FIG. 7(8). Thus, the memory module 47'-1 is accessed by the signals MA12 through MA18, as indicated in FIGS. 7(5) and 7(8).

(6) As indicated in FIGS. 7(1), 7(4) and 8(6), the signals MA00 through MA11 (000011010011) are transmitted from the address mapper 31 of the MAC 3 to the MAR 41-1 of the memory unit 4 and, simultaneously, the control signal MSTA2 is transmitted from the control circuit 33' of the MAC 3 to the control circuit 42' of the memory unit 4. As a result, the data (000011010011) is stored in the MAR 41-1 and, after that, the higher five bits (00001) of the MAR 41-1 are compared with the data stored in the MAR 41-3 by the comparator circuit 48. As a result of this, since the data stored in the MAR 41-3 is also (00001), the comparator circuit 48 raises the potential of the signal C1, so that the circuit 42' produces the signal TCAS. In the memory module 47'-1, the signal TCAS passes through the gate G10, so that the potential of the signal *CAS is changed from high to low as indicated in FIG. 7(9). Simultaneously, the multiplexer 44 transmits the data MA05 through MA11, instead of the data MA12 through MA18 at time P2, as indicated in FIG. 7(5). Therefore, the memory module 47'-1 is accessed by the data MA05 through MA11. Thus, the second access operation for the memory module 47'-1 is completed. In this case, the total access time for the memory module 47'-1 is indicated by T7 in FIG. 7(9), which is much shorter than the time T5 indicated in FIG. 3.

(7) As indicated in FIG. 8(7), the data (00001) stored in the MAR 41-1 is transmitted to the MAR 41-3.

Thus, if the higher order five bits of the MAR 41-1 are different from the data of the MAR 41-3, which was used in a previous access, the total access time, which is denoted by T6 in FIG. 7(9), is relatively long. Contrary to this, if the higher five bits of the MAR 41-1 are the same as the data of the MAR 41-3, the total access time, which is indicated by T7, is very short. In general, an executive program consists of routine programs, each of which may be stored in one memory module. Therefore, the higher order five bits of the MAR 41-1, which designate the selection of the memory modules, often coincide with those of the MAR 41-3. As a result, the average access time is nearly T7, which is very short.

As explained hereinbefore, the system for accessing memory modules according to the present invention has the advantage that the access time is very short, in other words, that the access speed is higher than that of the prior art, since before an entire current effective address is determined, the actual access for the memory modules is executed by using a part of the previous effective address.