Tri-Level Differential Line Receiver

This invention relates to a circuit for producing true differential line reception for a differentially driven tri-level signal.

Tri-level bipolar signals are often transmitted over a pair of lines. Such signals have no DC component and require relatively narrow bandwidth; however the transmission lines add noise. The receiver recovers and processes the bipolar signals to reproduce the transmitted data.

Various circuits have been used for recovering and processing such bipolar signals. Typical are the circuits shown by U.S. Pat. No. 3,894,288 to Musser, Jr.; 3,518,560 to Auiqnon and 4,007,382 to Warberg. This and other prior art use DC biasing techniques that compare each signal line to a locally generated DC bias. This technique degrades the signal to noise ratio, while eliminating any common mode noise rejection. It is an object of the present invention to provide a simple and true differential line receiver for differentially driven tri-level signals. Another object of the present invention is to provide an improved circuit for receiving and separating a differential tri-level serial data stream and converting the received serial data stream into data and clock for use with standard bi-level logic. Another object is to provide improved input biasing of differential tri-level inputs to permit a true differential comparison and signal detection. Another object is to provide high common mode rejection of noise that is developed during transmission.

The invention provides two comparators each having an initial offset voltage to level shift incoming return to zero (RZ) tri-level signals. Both the true tri-level signal and its complement are applied to the comparator networks. The output of one comparator represents a "zero" state detected while the output of the other comparator is an indication of a detected "one" state. These outputs are then simultaneously applied to a bistable RS flip-flop and a bistable NAND gate to produce the desired nonreturn to zero (NRZ) data and clock pulse outgoing signals, respectively. The input biasing of the differential tri-level inputs is accomplished with a pair of symmetrical resistive networks to permit a true differential comparison and signal detection. The phrase "resistive network" shall mean a network consisting of resistor elements only.

FIG. 1 is a schematic diagram, partly in block form, of a circuit in accordance with the present invention.

FIG. 2 is a waveform representative of a tri-level signal as utilized to convey data and clock information.

FIGS. 3A and 3B are waveforms representing respectively a true tri-level signal and its complement as applied to the input of the circuit of FIG. 1.

FIGS. 4A through 4H are waveforms representing signals appearing at various places in the circuit of FIG. 1.

Referring to FIG. 1 there is shown a pair of symmetrical bias networks each comprised of resistive elements. The first bias network is made up of serially connected resistors R1, R9 and R2 in conjunction with serially connected resistors R3 and R4. Serially connected resistors R3 and R4 are connected in parallel with resistor R9 while the junction between resistors R3 and R4 is connected to input terminal 11. Terminal 11 receives the true tri-level input signal as depicted in FIG. 3A. A tri-level signal is an encoded signal containing both clock and data as shown in FIG. 2. A logic "one" is denoted by a positive going pulse for a first half period of T.sub.p. During the second half period of T.sub.p the signal is always returned to zero volts.

FIGS. 3A and 3B show a differential RZ tri-level signal for transmission over a two wire cable. One side of resistor R2 is connected to a source of negative biasing potential, -E.sub.s, at a terminal 13. The other side of resistor R2 is connected as shown with resistors R4 and R9, point E2 in the network, and is also connected to the negative input terminal of a comparator 17. One side of resistor R1 is connected to a source of positive biasing potential, +E.sub.s, at a terminal 15. The other side of resistor R1 is connected as shown with resistors R3 and R9, point E1 in the network, and is also connected to the positive input of a comparator 16. This resistive network, made up of resistors R1, R2, R3, R4, and R9, forms a bias network functioning to offset the input signal applied to terminal 11 so that the comparators 16 and 17 may detect the "one" or the "zero" state of the input. The true input, shown in FIG. 3A, is attenuated and level shifted to a positive voltage equal to one half the new or attenuated amplitude excursion of a "one" or "zero" at point E1 and is attenuated a like amount and is level shifted to a negative voltage equal to one half the new or attenuated amplitude excursion of a "one" or "zero" at point E2. The attenuated and level shifted signals appearing at points E1 and E2 are respectively shown in FIGS. 4A and 4E.

The second bias network is made up of serially connected resistors R5, R10 and R6 in conjunction with serially connected resistors R7 and R8. Serially connected resistors R7 and R8 are connected in parallel with resistor R10 while the junction between resistors R7 and R8 is connected to input terminal 12. Terminal 12 receives the complement tri-level input signal as depicted in FIG. 3B. One side of resistor R5 is connected to the source of negative biasing potential, -E.sub.s, at terminal 13. The other side of resistor R5 is connected as shown with resistors R7 and R10, point E3 in the second network, and is also connected to the negative input terminal of comparator 16. One side of resistor R6 is connected to the source of positive biasing potential, +E.sub.s, at a terminal 14. Terminals 14 and 15 may be connected together. The other side of resistor R6 is connected as shown with resistors R8 and R10, point E4 in the network, and is also connected to the positive input of comparator 17. This second resistive network, made up of resistors R5, R6, R7, R8 and R10, forms a bias network functioning to offset the input signal applied to terminal 12 so that comparators 16 and 17 may detect the "one" or the "zero" state of the input. The complement input, shown in FIG. 3B, is attenuated and level shifted to a positive voltage equal to one half the new or attenuated amplitude excursion of a "one" or "zero" at point E4 and is attenuated a like amount and is level shifted to a negative voltage equal to one half the new or attenuated amplitude excursion of a "one" or "zero" at point E3. The attenuated and level shifted signals appearing at points E3 and E4 are respectively shown in FIGS. 4B and 4D.

Resistors R1, R2, R3, R4 and R9 of the first network are respectively of the same values as are resistors R6, R5, R8, R7 and R10 of the second network so that the first and second networks are symmetrical to produce equal attenuations and biases for the true and complement inputs. The positive and negative offsets and biases are respectively also equal in magnitude.

Comparators 16 and 17 are known in the art (may for example be of the LM119 type) and are constructed such that their outputs will change state only when the difference of the input voltages (the voltage at the negative input subtracted from the voltage at the positive input) changes polarity (E1-E3 for comparator 16 and E4-E2 for comparator 17). These relationships are shown at FIGS. 4A, B and C and FIGS. 4D, E and F respectively. FIGS. 4C and 4F respectively show the outputs from comparators 16 and 17. Comparator 16 is the "zero" (or first binary character) state detector and comparator 17 is the "one" (or second binary character) state detector. As may be seen from FIGS. 4A, B and C, the conditions for a change of state of comparator 16 are met at times c and d. As may be seen from FIGS. 4D, E and F, the conditions for a change of state of comparator 17 are met at times a and b.

The outputs from comparators 16 and 17 are fed to the clock and data extraction circuitry made up of RS flip-flop 18 and NAND gate 22. Flip-flop 18 is set by a "one" (e.g., a negative going pulse representing a "one") appearing on the output of comparator 17 over line 21 to the set, S, input of the flip-flop. Flip-flop 18 is reset by a "zero" (e.g., also a negative pulse representing a "zero") appearing in the output of comparator 16 over line 20 to the reset, R, input of the flip-flop. Thus, the output from flip-flop 18 over line 19 is the data contained in the input signals in NRZ form. The comparator outputs on lines 20 and 21 are also applied to NAND gate 22 to form clock pulses by combining the "one" and "zero" signals. The above circuitry and method of operation produces a true differential receiver having high common mode rejection of noise. Since each input signal to the comparators experiences the same attenuation, any common mode voltage (a voltage of equal direction and magnitude) will be ignored by the comparators. High common mode rejection is necessary to obtain reliable signal transmission between two units that operate in a high noise environment.

The resistor networks provided make use and selection of proper resistor values simple. The bias voltages are developed across resistors R9 and R10. Resistors R9 and R10 are of equal values and once this value is selected, the voltage developed across the resistor R9 or R10 remains constant for any value of signal input. This property permits a simple selection of components. Signal attenuation is determined by the ratio of R1/R1+R3 or the corresponding resistors in other legs. Resistors R9 and R10 are determined by the desired voltage drop across these resistors once the attenuation resistors R1, R3, etc. are selected.

While a particular embodiment of the invention has been shown and described, modifications may be made within the spirit and scope of the invention; and it is intended in the appended claims to cover such modifications.