Method of Manufacturing Semiconductor Device

(a) Field of the Invention

The present invention relates to a method of manufacturing a semiconductor device such as a static induction transistor and a semiconductor integrated circuit device in which such static induction transistor or transistors are integrated.

(b) Description of the Prior Art

Conventional method of manufacturing a static induction transistor or a static induction transistor logic device (hereinafter referred to as SITL device) usually comprises the following steps: (1) forming an aperture in the SiO.sub.2 film covering the entire surface of a semiconductor an aperture for doping a gate-forming-impurity so as to surround a channel region; thereafter, (2) forming a gate region by selectively diffusing the impurity through said aperture and at the same time therewith defining a region which will serve as a source region surrounded by said gate region; next, (3) after aligning a diffusion mask relative to the gate region, forming the source region within said region adapted to become the source region by selectively diffusing an impurity; and (4) after aligning an etching mask relative to said gate region, said source region and a drain region, forming contact apertures for these respective regions, and forming a gate contact, a source contact and a drain contact.

According to the conventional method described above, it was necessary to perform mask alignments twice for the gate region when the source region and the source contact portion are formed. Thus, this method not only has been troublesome and complicated in terms of steps, but also there has been required a surplus area on the surface of the substrate to provide for some marginal area for mask alignments. Accordingly, there has been a limitation to the minuteness of the circuit structure of the device, and the packing density has been limited greatly. Also, there has been the further inconvenience that, in order to establish self-alignment of the source region and the gate region, the number of masking steps had to be increased.

A basic object of the present invention is to provide a method of manufacturing a semiconductor device which simplifies the masking step in the manufacturing process.

A first object of the invention is to provide a method of manufacturing a semiconductor device as described above, which eliminates the necessity to perform mask alignments for masking the gate region and the provision of marginal space for mask alignments in case the source region and the source contact portion are formed.

A second object of the present invention is to provide a method of manufacturing a semiconductor device as described above, in which, at the time of formation of the source region, this source region is self-aligned relative to the gate region.

A third object of the present invention is to provide a method of manufacturing a semiconductor device as described above, in which, at the time the source contact portion is formed, this source contact portion is self-aligned relative to the source region and the gate region.

A fourth object of the present invention is to provide a method of manufacturing a semiconductor device as described above, such that, owing to the elimination of the marginal space in the surface of the semiconductor substrate for masking, the packing density of the device is improved.

FIGS. 1 to 6 show vertical sections of the semiconductor substrate, illustrating the successive steps of manufacturing an SITL device embodying the present invention though an additional or injector transistor is not shown.

The present invention will hereunder be described with respect to a preferred embodiment thereof by referring to the accompanying drawings.

FIGS. 1 to 6 show the steps of manufacturing an SITL device representing an embodiment of the present invention. The respective steps are detailed as follows.

(1) By relying on a conventional technique, an n.sup.- type silicon epitaxial growth semiconductor layer 12 is formed, leaving an n.sup.+ type buried layer 11, on a surface of a p type semiconductor substrate 10. And then, a p type impurity such as boron is selectively diffused into the n.sup.- type semiconductor layer 12 so as to reach the substrate 10 to thereby form a p.sup.+ type isolation region 13. During the above-mentioned steps, usually SiO.sub.2 film is thermally grown on the upper surface of the layer 12. Of course, another SiO.sub.2 film may be freshly formed in addition to or separately from the above-said SiO.sub.2 film. Either of these SiO.sub.2 films is illustrated conveniently as an insulation film 14 in FIG. 1. This insulation film 14 is then subjected to simultaneous formation of a closed loop-shaped aperture 15 for gate-doping by relying on a known photolithographic technique, an aperture 16 for source contact and surrounded by said gate-doping aperture 15, and an aperture 17 positioned separately from and on the outside of said aperture 15, to serve as a drain contact aperture, as shown in FIG. 1.

(2) Next, the exposed surface portions of the n- type semiconductor layer 12 is oxidized for a very short depth, and thereafter the resulting entire upper surface of the substrate is covered with a silicon nitride (Si.sub.3 N.sub.4) by relying on a conventional CVD (Chemical Vapor Deposition) technique. Thereafter, there are formed masking layers 18 and 19 made of Si.sub.3 N.sub.4 through patterning by relying on a photolithographic technique so as to retain the covered silicon nitride on the contact apertures 16 and 17. During this step, the gate-doping aperture 15 is exposed. Subsequently, the thin SiO.sub.2 film provided on the surface of the semiconductor body defined in the doping aperture 15 is etched away. FIG. 2 shows the article at this state. It should be noted here that the thin SiO.sub.2 film disposed beneath the masking layers 18 and 19 serves to mitigate thermal stress which can develop due to the difference in thermal expansion coefficient between silicon and silicon nitride.

(3) Then, boron is selectively diffused (more particularly it is driven-in after deposition of same) into the n- type semiconductor layer 12 through the doping aperture 15, to thereby form a p+ type impurity-doped gate region 20. Concurrently therewith, a region 12S for source region surrounded by said doped region 20 is defined. During this step, a fresh SiO.sub.2 film is formed, by a thermal process for driving-in the p type impurity of the gate region 20, on that portion of the surface of the semiconductor body located within the doping aperture 15. This SiO.sub.2 film will have a thickness greater than that of the SiO.sub.2 film provided beneath the masking layers 18 and 19, since oxidization of silicon is more facilitated at the exposed surface in the doping aperture 15 than the potions covered by the masking layers 18 and 19. See FIG. 3. Subsequently, these masking layers 18 and 19 and the thin SiO.sub.2 film disposed beneath them are etched away successively.

(4) Next, an n type impurity such as phosphorous or arsenic is selectively diffused (it is driven-in after deposition of same) into the n- type semiconductor layer 12 via the contact apertures 16 and 17 to form an n+ type doped region 21 for source region and an n+ type doped region 22 for drain contact as shown in FIG. 4. In this step, the source region 21 and the drain region 22 are rendered into self-alignment relationship relative to the gate region 20, and a fresh thin SiO.sub.2 film is formed on that portions of the surface of the semiconductor body located within the contact apertures 16 and 17 due to a thermal process for driving-in the n type impurity.

(5) Thereafter, a gate contact aperture 15a is formed by selective etching technique using, for example, a photoresist as a mask. Concurrently therewith, the thin SiO.sub.2 film located within the contact apertures 16 and 17 is etched away as shown in FIG. 5. As a result, there are exposed, in the respective contact apertures 15a, 16 and 17, corresponding portions of the surface of the semiconductor body, respectively.

(6) A electrode metal such as aluminum is deposited on the entire upper surface of the substrate. By appropriate patterning of this deposited metal, there are formed a gate electrode layer 23, a source electrode layer 24 and a drain electrode layer 25 as shown in FIG. 6. In this step, the source contact area between the source region 21 and the source electrode layer 24 is rendered into self-alignment relationship relative to the source region 21 and to the gate region 20. Also, the drain contact area between the drain region 22 and the drain electrode layer 25, too, is rendered into self-alignment relationship relative to the drain region 22 and the gate region 20.

In the above-described embodiment, the n- type semiconductor layer 12 has a low impurity concentration, such as 1.times.10.sup.19 to 1.times.10.sup.21 m.sup.-3, for the purpose of the formation of a static induction transistor, so that the formation of the isolation region 13 can be accomplished by a processing which is conducted at the same time with the selective diffusion intended to form the doped region 20 for the formation of the gate region. Also, in case a Schottky junction is required, the contact cutting step shown in FIG. 5 may be utilized, so that it is possible to form a Schottky junction at any desired location. It should be understood here that the above-said selective doping of impurity may be accomplished by selective ion-implantation technique, instead of the above-described selective diffusion technique.

It should be understood also that an operation by reversing the function of the source region and the drain region is possible.