High Speed Rectangle Function Generator

This invention relates generally to rectangle function generators and more specifically to high speed rectangle function generators wherein the output response of the rectangle function generator to an input voltage level is in the order of nanoseconds. In particular, this invention relates to rectangle function generators which produce an output voltage V.sub.o which is a rectangle function, the argument of which is an input voltage, V.sub.in, rather than time, t, i.e., V.sub.o =rect (V.sub.in) rather than V.sub.o =rect (t).

For many applications it is highly desirable, for the proper functioning of a circuit or a device, to be able to generate highly accurate high speed rectangular or square waves. Many circuits and devices are capable of generating rectangular waves, however, for high speed waves, i.e., waves with a period in the order of microseconds, it is necessary to have the circuit or device generate a rectangle function as close to instantaneously as possible and at least in the order of nanoseconds, in response to an input voltage. Such devices may be needed, for example, in the construction of specialized radar signal processors. Prior art devices, such as microcomputers or microprocessors, have been used to generate rectangular waves. However, the calculations required to produce an output, V.sub.o, in a microcomputer or microprocessor in response to an input voltage, V.sub.in, takes time to compute. This results in V.sub.o being delayed by this amount of time after V.sub.in is input to the computer.

It is therefore one object of this invention to provide a device that is capable of generating high speed rectangular waves as a function of an input voltage.

It is another object of this invention to provide a device that is capable of generating high speed rectangular waves that is simple and inexpensive.

It is a further object of this invention to provide a device that is capable of generating high speed rectangular waves with a period in the order of microseconds.

It is still a further object of this invention to provide a device that is capable of generating high speed rectangular waves with an output response to an input voltage in the order of nanoseconds.

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

These and other objects, features and advantages of the invention are accomplished by a device wherein a voltage divider provides a series of sequential switching points in response to a varying input voltage. These sequential switching points cause a series of inversion and non-inversion amplifiers to provide outputs which are summed into a single output.

The above and further objects and novel features of the invention will more fully appear from the following description when the same is read in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are for the purpose of illustration only, and are not intended as a definition of the limits of the invention.

FIG. 1 illustrates schematically one embodiment of the present invention.

FIG. 2 graphically illustrates an input voltage and a uniformly spaced output voltage.

FIG. 3 graphically illustrating an input voltage and a non-uniformly spaced output voltage.

FIG. 4 illustrates graphically the characteristics of an operational amplifier.

FIG. 5 illustrates schematically a specific embodiment of the present invention.

FIG. 6 illustrates schematically an alternate embodiment of the present invention.

FIG. 7 illustrates schematically one embodiment of an operational amplifier .

Referring now to the drawings, FIG. 1 is a schematic illustration of one embodiment of the present invention. Operational amplifiers 10-15 are connected to a voltage divider means made up of resistors R.sub.1 -R.sub.7. An example of an operational amplifier that can be used is the .mu.A715. The resistors R.sub.1 through R.sub.7 form a voltage divider and divide an impressed voltage represented by +V.sub.s and -V.sub.s between each successive resistor. For example, a voltage is provided at node F which is between the resistor pair made up of R.sub.1 and R.sub.2, a different voltage is provided at node E, which is between the resistor pair R.sub.2 and R.sub.3, etc. It can be appreciated by those of ordinary skill in the art that if resistors R.sub.2 through R.sub.6 are of equal value, the voltage differences between each node will be the same. Each successive node is connected to a successive operational amplifier and to an alternate input of each successive operational amplifier. For example, node F is connected to the positive input of operational amplifier 15, node E is connected to the negative input of operational amplifier 14, etc. It also can be appreciated by those of ordinary skill in the art that this method of connection causes the operational amplifiers to act as alternate inversion, non-inversion amplifiers. An input voltage V.sub.in is applied to the other alternate inputs of the operational amplifiers, i.e., V.sub.in is applied to the negative input of operational amplifier 15, to the positive input of operational amplifier 14, etc. The output of an operational amplifier depends upon how the amplifier is biased and the voltage relationship between the positive and negative inputs. With nodes A-F at fixed voltages determined by the voltage divider network made up of resistors R.sub.1 -R.sub.7 and voltages +V.sub.s and -V.sub.s, the instantaneous input voltage V.sub.in then determines the switching point of each operational amplifier. The resistors R.sub.8 -R.sub.13 form an adding network which combines the individual outputs of the operational amplifiers 10-15 into a single output.

FIG. 2 illustrates graphically an output voltage with uniform spacing between the high outputs and the low outputs. It is noted that the low output may be zero volts. Uniform spacing is achieved by making resistors R.sub.2 -R.sub.6 equal in value and making the input voltage V.sub.in linearly time variant.

FIG. 3 illustrates graphically an output voltage with non-uniform spacing. This is achieved by varying the size of resistors R.sub.2 -R.sub.6 so that the fixed voltages at nodes A-F vary non-uniformly.

FIG. 5 is a specific example of one embodiment of the present invention. This example is given for illustrative purposes only and is not to limit the scope of the present invention. The resistors R.sub.2 -R.sub.6 are of equal value, the operational amplifiers are biased at plus and minus 15 volts, plus and minus 15 volts is applied across resistors R.sub.1 -R.sub.7 and an input voltage V.sub.in is applied to the input. The operation of the high speed rectangle function generator will now be described: As long as the input voltage V.sub.in is below the fixed voltage at node A the outputs of operational amplifiers 10, 12 and 14 will be low, approximately -6 V, and the outputs of operational amplifiers 11, 13 and 15 will be high, approximately +6 V. As a result, the output behind the summing network, R.sub.8 -R.sub.13 will be balanced to zero volts. When the input voltage V.sub.in is larger than the fixed voltage present at node A the output of operational amplifier is a +6 V rather than a -6 V. If the input voltage V.sub.in is also lower than the fixed voltage present at node B the outputs of operational amplifiers 10, 11, 13 and 15 are + 6 V and the outputs of operational amplifiers 12 and 14 are -6 V. Therefore, there is an output of approximately +2 V behind the summing network. It is noted that the output of each operational amplifier will remain constant as long as V.sub.in is above the fixed voltage present at the appropriate node. This occurs because the operational amplifier goes into its saturation region as long as the relationship between V.sub.in and the node voltage is of the appropriate polarity, see FIG. 4, which is a graphical representation of the relationship between the output and input of a typical operational amplifier. For example, operational amplifier 10 switched from -6 V to +6 V when V.sub.in rose above the fixed voltage present at node A. Operational amplifier will then remain at +6 V as long as V.sub.in is above the fixed voltage at node A. When the input voltage V.sub.in rises above the fixed voltage present at node B operational amplifier 11 will switch from +6 V to -6 V. Therefore, as long as the input voltage V.sub.in is above the fixed voltage present at node B but less than the voltage at node C the outputs of operational amplifiers 11, 12, and 14 will be -6 V and the outputs of operational amplifiers 10, 13 and 15 will be +6 V thus causing the output behind the summing network to return to zero volts. This switching between zero volts and +2 V at the summing network output continues as V.sub.in reaches the appropriate voltage present at each node. With n operational amplifiers, there will be a maximum of n/2 cycles at the summing network output for a complete range of input voltage V.sub.in. To obtain a continuous rectangular wave output, it can easily be seen by one of ordinary skill in the art that by returning V.sub.in to its original value all of the operational amplifiers are returned to their original state and the cycle described in the above analysis begins again.

From the analysis above, it can easily be seen how the equal spacing shown in FIG. 2 is achieved. By having resistors R.sub.2 -R.sub.6 of equal value the fixed voltages at nodes A-F will differ by an equal amount. Then causing the input voltage V.sub.in to increase linearly, V.sub.in will reach the voltage at each node at equal intervals causing the spacing between the output pulses to be uniform. Similarly, by having the values of resistors R.sub.2 -R.sub.6 differ, the fixed voltages at nodes A-F differ by an unequal amount. Thus, the application of an input voltage V.sub.in that increases linearly, V.sub.in will reach the fixed voltage present at each node at different intervals thus causing the spacing between each output pulse to be non-uniform

An alternate embodiment of the present invention is illustrated graphically in FIG. 6. In this embodiment, the inversion is achieved at the amplifier outputs, i.e., the positive outputs of amplifier 10, 12 and 14 and the negative outputs of amplifiers 11, 13 and 15 are combined at the common load R.sub.L which also provides the output. An embodiment of a single operational amplifier shown at 10-15, FIG. 6 is shown in FIG. 7. It is noted that instead of bipolar transistors, FET's, tubes or any other similar elements could be used.

While I have described and illustrated several specific embodiments of the present invention, it will be clear that variations of the method and apparatus which are specifically illustrated and described may be resorted to without departing from the true spirit and scope of the invention as defined in the appended claims.