US 4,368,533 AGrant
Error Data Correcting System
Issue Date:1983-01-11
•5 Claims
•2 Drawing Sheets
Abstract
A data input signal having n data words and two check words expressed by W.sub.1 to WnPQ as one block is applied through a T.sup.-(n+1) operation circuit to a Q register where it is processed for a Q decoding. The data input signal is applied to a P register where it is processed for a P decode. Through those processings, the syndrome S.sub.1 derived from a P register and T.sup.c-(n+1) S.sub.2 obtained by shifting the Q.sub.1 register in accordance with the first error word summed by the Q register. S.sub.1 +T.sup.c-(n+1) S.sub.2 as the result of the addition is multiplied by the matrix data for decoding a specific bit, which is derived from a matrix generating circuit, in a multiplier gate circuit, so that it is decoded as the corrected data W.sub.de of the second error word Wd'. Then, the corrected data Wce is applied to a buffer circuit. In this case, the matrix generating circuit generates matrix data for decoding a specific bit by using interval data k representing the interval between the first error word Wc' and the second error word Wd'. The S.sub.1 is inputted into the buffer circuit. The W.sub.dc and the corrected data W.sub.ce (=S.sub.1 +W.sub.de) of the first error word W.sub.c' are read out from the buffer circuits, through gate circuits for multiplication and a gate circuit for addition. Those are added to the corresponding information words Wc and Wd of the input data signal coming through one block delay, by a gate circuit for addition, as that the error data is corrected.
Metadata
Assignee
- Tokyo Shibaura Denki Kabushiki Kaisha
Inventor
- Tadashi Kojima
Application Information
Application Number:US 1445219
Filing Date:1980-04-28
Priority Date:1979-05-10
Art Unit:236
Classifications
IPC:
G06F 1110
Field of Search:
37139;40;37;38
Patent Drawings (2 sheets)
Description
Field of the Invention
The invention relates to an error data correcting system adaptable for a system for transmitting, recording and reproducing digitized information signals by PCM (pulse code modulation), for example, and, more particularly, to improvements over an M matrix generator used in the error data correcting system.
Background of the Invention
In an error data correcting system of this type, which has been proposed heretofore in this field, n data words W1 to Wn each containing m/n bits and additionally include a first check code ##EQU1## as the sum of bits corresponding to the data words and a second check code ##EQU2## as the sum of the bits corresponding to the signals generated through the operation of a polynomial X.sup.m +X.sup.g +1 by an auxiliary matrix (T). The error data correcting system can correct up to two error words in the N data words by using an M matrix generator for decoding.
A ROM (read only memory) has generally been used from the M matrix generator for decoding, because of the time restriction in the decoding process.
In the case of an audio PCM recorder such as a record/reproduction system, one word commonly includes 12 to 16 bits. If the error data correcting system is applied to such a system, the memory capacity of the ROM that is used must be very large and an address counter capable of formulating the large address fields for the ROM is needed. The circuit construction for such an overall system is complicated. Additionally, very large number of components is necessary when the circuit is fabricated by LSI technology.
Objects of the Invention
Accordingly, an object of the invention is to provide an error data correcting system using a relatively simple decoding matrix generating circuit in place of a decoding M matrix generator having ROM and an address counter.
Another object of the invention is to provide an error data correcting system with a decoding matrix generating circuit that results in a considerable reduction of the number of the components normally required when fabricating the circuit by LSI technology.
According to the invention, there is provided an error data correcting system in which n data words (W1) to (Wn) each including m bits additionally have a check code ##EQU3## as an addition of the bits corresponding to the data words and another check code ##EQU4## as an addition of the bits corresponding to the signals formed through the operation by an auxiliary matrix (T) of a polynomial X.sup.m +X.sup.g +1, the error words being corrected by using a matrix generator for decoding, wherein a matrix generating circuit for generating only the matrix data to decode a specific bit of an M matrix is used as decoding matrix generator and a given operation is made of the check code while the matrix data is fixed.
With such a construction, the decoding matrix data may comprise a single bit, so there is no need for storing all matrix data in a read only memory (ROM). According, a ROM and an address counter associated with the ROM are not needed, with the result that the circuit construction is simplified and the number of elements necessary when the circuit is fabricated by LSI technology is considerably reduced.
Other objects and features of the invention will be apparent from the following description taken in connection with the accompanying drawings, in which:
Brief Description of the Drawings
FIGS. 1 to 3 schematically illustrate the principles of the error data correcting system of the instant invention and the use of shift registers in carrying out the invention;
FIG. 4 is another block diagram for illustrating the principle of the error data correcting system of the instant invention;
FIG. 5 is a block diagram of a decoding matrix generating circuit used in the invention;
FIG. 6 illustrates an alternate embodiment of the decoding matrix generating circuit of FIG. 5; and
FIG. 7 is a block diagram of an error data correcting system according to the invention.
Detailed Description of the Invention
It is assumed that n data words and two parity check codes are expressed below and that each data word is comprised of m bits. ##EQU5## Here codes P and Q of the check words are expressed by ##EQU6## The parity check matrix of those codes is ##EQU7## where T is a Q generator matrix and I is a unit matrix.
This will be further described. Rewriting the equations (1) and (2), we have ##EQU8##
When the ith and jth data are dropped, the solutions of the equations (3) and (4) are not "0" but syndromes S.sub.1 and S.sub.2 given by equations (5) and (6). Assuming again that the original series of data words is expressed by W.sub.1, W.sub.2 -(W.sub.i)-(W.sub.j)-W.sub.n and the series of data words of which the ith and the jth data are dropped is expresed by W'.sub.1, W'.sub.2 -(W'i)-(W'j)-W'n, and that W'i=Wi+Wie, W'j=Wj+Wje, and W'=W. ##EQU9## Further ##EQU10## From the equation (7), we have
putting the equation (9) into the equation (8), we have
This equation can be rewritten as
and hence
As seen from the equations (12) and (13), the data dropped, i.e., the error data words, may be decoded by using the syndromes S.sub.1 and S.sub.2. The data words, when decoded, are Wi+Wie and Wj+Wje and therefore if Wie and Wje are decoded, the ith and jth words Wi and Wj may be decoded.
In this way, the correct original data words Wi and Wj may be decoded by decoding Wie and Wje. The decode system according to the invention to be described later relates mainly to the generation of Wie and Wje.
There is another decoding method for obtaining the syndromes S.sub.1 and S.sub.2, wherein all of the data words except the error data words are summed. The error words Wi and Wj are directly obtained with the definitions S'.sub.1 =Wi+Wj and S'.sub.2 =T.sup.(n+1)-i Wi+T.sup.(n+1)-j Wj.
The former decoding method in which the error data is corrected with the definition ##EQU11## will further be described in detail. In the description to be given, it is assumed that the series of data words includes six words and that each word includes 4 bits. The T matrix is given by ##EQU12## This matrix is an auxiliary matrix of a polynomial 1+x+x.sup.4. Accordingly, if B=T.A. the signals of the respective 4 bits are
Such a T matrix operation will be understood when considering the Galois field GF(2.sup.4) formed by a polynomial ring with F(x)=x.sup.4 +x+1 as a modulus polynomial.
From the above-mentioned equations, it is seen that
Such an operation may be performed by using a shift register arranged in the form of a polynomial as shown in FIG. 1.
When data A is first loaded into the shift register and it is shifted by one, the T matrix of the data A is operated. When the data A is shifted by n, T.sup.n A is obtained.
The check codes P and Q of the data words W.sub.1 to W.sub.6 thus obtained are ##EQU13## Here, the P code is formed by addition of bits corresponding to the respective words W.sub.1 to W.sub.6. The addition is represented by the symbol .sym. which corresponds to the exclusive OR of corresponding bits, that is to say, the addition of mod 2. The Q code is generated by the data matrix-operated by the shift register shown in FIG. 1.
In the correcting method described above, even though errors occur in up to two words in the data words W.sub.1 to W.sub.6, the data words W.sub.1 to W.sub.6 may be completely decoded.
From the equations (12) and (13), we have
when S.sub.1 .sym.T.sup.i-7 S.sub.2 =m, the equation (17) is rewritten as below
where
In the equation (19), k=j-i When there are six data words, Mk includes M.sub.1 to M.sub.5.
For this reason, the decoding of Wi, Wj is generally performed by using an M matrix generator, but it is the conventional, general practice to store such M matrix data in a ROM (Read Only Memory) to permit it to be controlled due to its lack of regularity, time, restriction, etc.
The operation of T.sup.-n may be made by inverting the shift register shown in FIG. 1 in its connection, and then shifting the inverted one n times. When the T matrix is used as an auxiliary matrix of the polynomial 1+x+x.sup.4, M.sub.1 to M.sub.5 are ##EQU14##
The actual flow of the decoded data will be described in detail. Assume now that data words W.sub.1 to W.sub.2 of the W.sub.1 to W.sub.6 are erroneous. Since i=1 and j=2, k=1 by the equation k=j-i. First,
If
we have
obtained is ##EQU15## Therefore, if T.sup.-6 S.sub.2 =[l.sub.1, l.sub.2, l.sub.3, l.sub.4 ]
Let us obtain m, i.e. S.sub.1 +T.sup.-6 S.sub.2.
where
From the equation (18),
Here M.sub.1 of the M matrix is used for (1.sym.T.sup.-1).sup.-1.
When m.sub.1 to m.sub.3 of m.sub.4 to m.sub.1 are all summed, ##EQU16## Accordingly, b.sub.4 may be decoded.
Similarly, b.sub.3 is decoded by m.sub.1 and m.sub.2 ; b.sub.2 by m.sub.1 ; b.sub.1 by m.sub.1 to m.sub.4. W.sub.2e =M.multidot.m and M is already known as described above. Therefore, by multiplying M.sub.1 by m, W.sub.2e may be decoded.
Before proceeding with the description of M.sub.1 to M.sub.5, the operation of the Galois field will be described. The Galois field GF (2.sup.4) is formed by the polynomial ring of which the modulus polynomial is F(x)=x.sup.4 +x+1. The expression of the Galois field GF(2.sup.4) is tabulated in the following table. In the table, .alpha..sup.4 +.alpha.+1=0.
In the table, .alpha. is a root in the Galois field GF(2.sup.4) of x.sup.4 +x+1. As seen from the vector expression, the multiplication of .alpha..sup.i by .alpha. is performed in a manner that the vector expression of .alpha..sup.i is set in the circuit shown in FIG. 2 and it is shifted by one time. Accordingly, the multiplication of .alpha..sup.i by .alpha..sup.i is made by shifting it j times.
A circuit for effecting a division by .alpha., that is, the circuit for effecting .alpha..sup.-1, may be realized by inverting the circuit in FIG. 2 in its connection. Here, if x.sup.4 +x+1=0 and x=1/y, we have y.sup.-4 +y.sup.-1 +1=0 and if it is multiplied by x.sup.4,
In the version of the equation, apparently, .alpha..sup.15 =.alpha..sup.0. Further, .alpha.(1+.alpha..sup.3)=.alpha.+.alpha..sup.4 =1 and therefore, it is seen that .alpha..sup.-1 is equal to .alpha..sup.14.
If a dividend .alpha..sup.i =(a.sub.1, a.sub.2, a.sub.3, a.sub.4)=a.sub.1 +a.sub.2 x+a.sub.3 x.sup.2 +a.sub.4 x.sup.3, ##EQU17## When F(x)=x.sup.4 +x.sup.3 +1 is a modulus polynomial, ##EQU18##
As seen from the above, the division is made by the inversion of the circuit. The circuit divided by .alpha. is shown in FIG. 3.
In view of the above-mentioned points, the M matrix in the equation (18) will be described.
where
In this case, i and j each ranges from 1 to 6 and accordingly
When considering this in the Galois field GF(2.sup.4) with the modulus polynomial of F(x)=x.sup.4 +x.sup.3 +1,
(k=1.about.5)
When k=1, ##EQU19##
Rewriting this into a linear coupling of the Galois field with the modulus polynomial of F(x)=x.sup.4 +x+1, we have
It is seen that the equation (27) is equal to the M.sub.1 matrix (or the vector diagram) of the M matrix. Similarly, when k=2, ##EQU20## When the vector at this time is obtained, it is equal to the M.sub.2 matrix of the M matrix.
When k=1, the multiplication of x.sup.3 is made in F(x)=x.sup.4 +x.sup.3 +1. To be specific, S.sub.1 +T.sup.i-7 S.sub.2 is set in the circuit of FIG. 3 at an inverse position and it is shifted three times. The remaining signal left in the shift register after shifting three times is Wje.
When k=2, the shift register is shifted six times.
In investigating the Galois field GF(2.sup.4) with the modulus polynomial of F(x)=x.sup.4 +x+1, from the equation (23), we have ##EQU21## Accordingly, the equation (29) is equal to the equation (27).
In other words, (S.sub.1 .sym.T.sup.i-7 S.sub.2)=(m.sub.1, m.sub.2, m.sub.3, m.sub.4) is set in the shift register shown in FIG. 2 and (1+x+x.sup.2 =.alpha..sup.12) is shifted therein 12 times. At this time, the data left in the shift register is Wje, as seen from the above-mentioned table.
As seen from the foregoing description, the decoding may be performed on the basis of the polynomial upon which the matrix T depends. Accordingly, it is evident that decoding may be made by the shift register connected in the polynomial manner.
As seen from the foregoing description, it is apparent that the vector space in the Galois field GF(2.sup.4) with the modulus polynomial of F(x)=x.sup.4 +x+1 develops the T matrix, the M.sub.1 to M.sub.5 matrices and a T.sup.-1 matrix to be described later.
In the operation of T.sup.-1, F(x)=x.sup.4 +x.sup.3 +1 is used and this is a reciprocal polynomial for F(x)=x.sup.4 +x+1. Further, it is apparent that the angle of viewing the original data is also inverted.
Further, it is apparent that, when each data is comprised of 4 bits, the polynomial is of fourth degree and its vector spaces are 16 kinds only. That is, the operation of two elements a and b allows a maximum of 15 shifts when the operation circuit is embodied as a shift register.
When the operation circuit by mere shift registers is used, if the degree of the polynomial is large, it is necessary to shift the shift register by 2.sup.12 to 2.sup.14, so that the operation takes a long time. If the data words are being transmittal by PCM or the like, the time taken for decoding processing is limited. It is for this reason that the M matrix for decoding, such as the M.sub.1 to M.sub.5 matrixes are loaded into a ROM (read only memory) although such a process requires extensive hardware capability. The matrices are sequentially read out to select the signal S.sub.1 +T.sup.i-(n+1) S.sub.2 and decode it.
Data correction as accomplished by the data correcting system according to the instant invention will now be explained.
As described above, the check code Q depends on the auxiliary matrix of the polynomial X.sup.m +X.sup.g +1. It is also seen from the foregoing description that the M matrix for error correction comprises a space vector generated in the Galois field (2.sup.m) with the polynomial of x.sup.m +x.sup.g +1.
The nature of the M matrix will be described by rewriting the T matrix to have the same relations as the matrices M.sub.1 have to M.sub.5 to the respective bits. ##EQU22##
Columns (a.sub.1 a.sub.2 a.sub.3 a.sub.4) are assumed to be numerals set in a computing circuit with a modulus polynomial of F(x)=x.sup.4 +x+1. On this assumption, when (a.sub.1) in the shift register circuit shown in FIG. 4 is set with "1" and it is shifted by one, the column (a.sub.1) is generated. Similarly, when "1" is set to only the (a.sub.2) and it is shifted by one, the column (a.sub.2) is generated. When "1" is set to only the (a.sub.3) and is shifted by one, the column (a.sub.3) is produced. When only (a.sub.4) is set to "1" and shifted by one, the column (a.sub.4) is produced.
The relations may also be explained in the following. When "1" is set in only the (a.sub.1) in position FIG. 4 and is shifted by one, the column (a.sub.1) is produced. If "1" is set in the (a.sub.1) position and is shifted by two, the column (a.sub.2) is produced. Similarly, the column (a.sub.3) is produced by three shifts and the column (a.sub.4) is produced for four shifts.
Those relations will be considered by using the B row representing the result of the computation. The column b.sub.3 will be considered first.
A signal at the cross-point of b.sub.3 and a.sub.4, corresponds to a signal at the cross-point of b.sub.2 and a.sub.3. The signal at the cross-point of b.sub.2 and b.sub.3 corresponds to the sum of the signals at the cross-points b.sub.4 and a.sub.2 and b.sub.1 and a.sub.2. The signal at the cross point of b.sub.1 and b.sub.2 corresponds to the signal at the cross point of b.sub.4 and a.sub.1. Therefore, the signal at the cross point of b.sub.3 and a.sub.4 corresponds to the sum of the signals at the cross-points b.sub.4 and a.sub.1, and b.sub.4 and a.sub.2.
The signal for the b.sub.3 and a.sub.3 combination corresponds to the signal for the b.sub.4 and a.sub.4 combination; the signal for the b.sub.3 and a.sub.2 combination corresponds to the signal for the b.sub.4 and a.sub.3 combination; the signal for the b.sub.3 and a.sub.1 combination to that for the a.sub.4 and a.sub.2 combination. In this manner, the column b.sub.4 may be obtained by using the signal of the column b.sub.4.
For row b.sub.1, the signal at the cross point of b.sub.1 and a.sub.3 is the sum of the signals at the cross points b.sub.4 and a.sub.3, and b.sub.1 and a.sub.3. A signal at the cross point of b.sub.2 and a.sub.4 is the sum of the signals at the cross points b.sub.4 and a.sub.3 and b.sub.1 and a.sub.3. Similarly, the signal for the cross point b.sub.1 and a.sub.2 is the sum of the signals for the cross points b.sub.2 and a.sub.2, and b.sub.4 and a.sub.1 ; a signal for the cross point b.sub.1 and a.sub.1 is the sum of the signals for the cross points b.sub.2 and a.sub.2, and b.sub.4 and a.sub.1. A signal for the cross point b.sub.1 and a.sub.4 is equal to the signal for the cross point b.sub.4 and a.sub.3 ; a signal for b.sub.3 and a.sub.2 is equal to the signal for the cross point b.sub.2 and a.sub.1. Therefore, it is the total sum of the signals for the cross points b.sub.2 and a.sub.1, b.sub.2 and a.sub.2, and b.sub.4 and a.sub.4.
This relation may be expressed in terms of the circuit shown in FIG. 5 which is a decoding matrix generating circuit used in the present invention. All the shift registers SR1 to SR4 are first cleared. Then, a gate signal G-sig is activiated through gate circuits G.sub.1 to G.sub.4 and A.sub.1 to A.sub.4 for multiplication and addition, the output signals a.sub.1 to a.sub.4 derived from the output terminals of the shift register form the column b.sub.4. Then, the respective registers are shifted by one to deactivate the gate signal G-sig, so that the output signals from the output terminals a.sub.1 to a.sub.4 form the row b.sub.3. When an additional shift by one is performed, the terminals produce output signals to form the row b.sub.2. An additional shift by one to causes the output terminals to produce signals forming the row b.sub.1.
Let us consider the rewritten matrix from another aspect. The row b.sub.2 is formed depending on the contents of the rwo b.sub.3. The row b.sub.3 depends on the contents of the row b.sub.4. With respect to the columns b.sub.3 and b.sub.4, a signal at the cross point of b.sub.1 and a.sub.2 is equal to the signal at the cross point of b.sub.4 and a.sub.1 : a signal for the cross point b.sub.1 and a.sub.3 is equal to the signal for the cross point b.sub.4 and a.sub.2 ; a signal for the cross point b.sub.1 and a.sub.4 is equal to the signal for the cross point b.sub.4 and a.sub.3 ; a signal for the cross point b.sub.4 and a.sub.4 is equal to the signal for the cross point b.sub.2 and a.sub.2. Accordingly, the row b.sub.4 is equal to the sum of the signal for the cross point b.sub.1 and a.sub.1 and the signal for the cross point b.sub.4 and a.sub.1, that is, the sum of the signals for the cross points b.sub.1 and a.sub.1, and b.sub.1 and a.sub.2. Therefore, the row b.sub.4 is formed depending on the contents of the row b.sub.1.
FIG. 6 shows another decoding matrix circuit embodying the above relations. First, data of the row b.sub.1 is set in the respective registers SR11 to SR14. The output terminals a.sub.1 to a.sub.4 produce the data of the row b.sub.1. Then, the respective registers are shifted by one thereby to produce the data of the row b.sub.4. Similarly, additional one shift produces the data of the row b.sub.3 and an additional one shift provides the data of the row b.sub.2. It is evident that, if those shift registers are shifted in the opposite direction, those data are generated in the inverted order to that as mentioned above.
As described above, the data as seen from the row b may be formed. This feature is for the case of the M matrix.
In short, a specific matrix in the M matrix is selected by using the decoding matrix generating circuit shown in FIG. 5 or FIG. 6. An initial value is selected by an initial data generating portion (ID) which is not shown in FIG. 6. In this way, all of the matrix data M.sub.1 to M.sub.5 in the M matrix may be generated by a single circuit construction, without storing them in the read only memory.
The explanation to follow is for a case where the circuit shown in FIG. 6 is used in place of the conventional M matrix generator constructed by the ROM and AC (address counter).
Assume now that, in a series data of n data words, errors occur in the c-th and d-th word and W'c=Wc+Wce and Wd'=Wd+Wde. If d-c=k, from equations (7), (8), (12) and (13)
where S.sub.1 =Wce.sym.Wde
When Wde=(b.sub.1 b.sub.2 b.sub.3 b.sub.4) and S.sub.1 .sym.T.sup.c-(n+1) S.sub.2 =(m.sub.1 m.sub.2 m.sub.3 m.sub.4) and the row a for decoding b.sub.4 is given by (a.sub.1 a.sub.2 a.sub.3 a.sub.4), we have
Rearranging the equations (32), (33), (34) and (35), b.sub.4 to b.sub.1 are given as follow ##EQU23## Where
As seen from the equations (36), (37), (38), (39) and (40), b.sub.4 to b.sub.1 may be decoded when (m.sub.1 m.sub.2 m.sub.3 m.sub.4) is changed while (a.sub.1 a.sub.2 a.sub.3 a.sub.4) is fixed.
It is further understood that the signal (m.sub.1 m.sub.2 m.sub.3 m.sub.4) is equivalent to the vector change of the data computed by the matrix T.
Specifically, if S.sub.1 .sym.T.sup.c-(n+1) S.sub.2 =(m.sub.1 m.sub.2 m.sub.3 m.sub.4) and the computing matrix for decoding b.sub.4 is (a.sub.1 a.sub.2 a.sub.3 a.sub.4), it is multiplied by the respective bits and the total sum of them is b.sub.4. The set of values (m.sub.1 m.sub.2 m.sub.3 m.sub.4) is set in the shift register in FIG. 4 and is shifted by one. Then, the output signal from the shift register is multiplied by (a.sub.1 a.sub.2 a.sub.3 a.sub.4) thereby b.sub.1 '. Since b.sub.1 ' is b.sub.1 .sym.b.sub.4, b.sub.1 may be decoded by summing b.sub.4 as previously decoded and b.sub.1 '.
As seen from the foregoing, the error data correcting system according to the invention can perform decoding by computing the data of S.sub.1 .sym.T.sup.c-(n+1) S.sub.2 by using the matrix generating circuit for producing only the matrix to decode a bit, without the conventional complicated decoding M matrix generator.
Thus, when the matrix generating circuit according to the invention is used, a single bit matrix is satisfactory for the decoding matrix data generated, so that the circuit used is simplified and is operable at low speed. Therefore, the matrix generating circuit is useful when it is used for the case where the length of the data word is large.
FIG. 7 shows an error data correcting system constructed on the basis of the principle as mentioned above. A data input signal to be corrected is applied to an input terminal IN.sub.1 of the error data correcting system. In the data input signal, n data words and two check words expressed by W.sub.1 to WnPQ are used as one block or series of data words. The data input signal is applied to a Q register 21 as a Q decoding circuit, via a T.sup.-(n+1) computing or operation circuit 20 for performing T.sup.-(n+1). At this time, a switch SW is set to a contact a. The data input signal is also applied to a P register 22 as a P decoding circuit.
The Q register 21 may be the T matrix operation circuit as shown in FIG. 4 and has the contents of T.sup.-(n+1) S.sub.2 when the data input signal as mentioned above is supplied thereto. If the first error word is Wc, the Q register 21 is shifted C times to store the output of T.sup.c-(n+1) S.sub.2. The switch SW is then turned to a contact b, so that the syndrome S.sub.1 derived from the P register 22, which may be the mere exclusive OR as mentioned above, is added to the contents of the Q register 21 to provide S.sub.1 +T.sup.c-(n+1) S.sub.2.
An error word control circuit EC is provided where the interval data k between the first error word Wc and the second error word Wd is checked and is applied to an matrix generating circuit 25 comprised as mentioned above. Upon receipt of the interval data k, the matrix generating circuit 25 selects matrix data to decode a specific bit, and applies the selected matrix data to a gate circuit G11. The gate G11 multiplies the matrix data for the specific data decoding matrix with the data from the Q register 21 thereby to obtain the correcting data W.sub.de. At this time, the syndrome S.sub.1 is applied from the P register 22 to a buffer circuit 24.
The Wce, as decoded and generated, is added to the S.sub.1 in the adder A.sub.12, so that the W.sub.ce is decoded and generated. In this case, the corrected data Wce and the S.sub.1 are applied to the adder A.sub.12, through gate circuits G.sub.12 and G.sub.13 enabled by a signal derived from the error control circuit (EC).
Part of the input data signal is directly applied to an adder A.sub.13 through a delay circuit (DL) after being delayed by one data block. When the input data signal has no error, the decoding section produces "0". In this case, the input data signal is accordingly derived from the output terminal (OUT).
When the first error word Wc' comes in, the decoded Wce is transferred to an adder A.sub.13, so that the correct data Wc is reproduced and is supplied to the output terminal (OUT). When the second error word Wd' comes in, the gate circuit (G.sub.13) is disabled and therefore the addition of the S.sub.1 is not performed in the adder A.sub.13, so that the Wde is transferred directly to the adder A.sub.14. As a result, the correct data Wd is reproduced and derived from the output terminal (OUT).
As recalled, the Wce and Wde designate the dropped cth and dth data. Accordingly, through the above-mentioned operation, the data words W.sub.1 to W.sub.n including such error data are correctly decoded.
The error word control circuit (EC) controls the decoding matrix generator circuit 25 in such a way that the interval between the error words, i.e., the information k, is checked and the matrix data for the specific bit decoding is produced corresponding to the interval checked. Also this may easily be realized by detecting a cyclic redundancy check signal attached to the input data signal, for example by a known cyclic redundancy check codes generating circuit (CRCC) including a shift register and the like known as an error pointer. In this case the error pointer is applied through another input terinal (IN.sub.2).
If the T matrix is for a polynomial F(x)=x.sup.n +x.sup.t +1, when the decoding is made from Msb, the data succeeding to the (n-1).sym.1 is corrected by adding the data preceding the (n-t) to the elements. Incidentally, in FIG. 7, A.sub.11 to A.sub.13 and G.sub.11 to G.sub.13 are gate circuits for addition and multiplication.
Let us consider a case where the circuit shown in FIG. 6 is used in place of the conventional decoding M matrix generator including the ROM and the address counter AC. Assume that the information data consists of n words, that errors take place in the c-th and d-th words, and that Wc'=Wc+Wce and Wd'=Wd+Wde, and d-c=k.
As in the previous case, we have from (7), (8), (12) and (13)
where
when
Rearranging those equations (41).about.(44), b.sub.1 to b.sub.4 are
As evident from equations (45) to (48), the corrected data is decoded in a manner such that the matrix (a.sub.1 a.sub.2 a.sub.3 a.sub.4) for decoding b.sub.1 is fixed and S.sub.1 +T.sup.c-(n+1) S.sub.2 =(m.sub.1 m.sub.2 m.sub.3 m.sub.4) is computed.
In this example, the gate circuit is not used A.sub.11 in the FIG. 7 circuit. The order of the data inputted into the buffer circuit is not MSB (most significant bit) to LSB (least significant bit). The remainder of the example is the same as explained above with reference to FIG. 7. For inverting the decoding order, the shift register is inverted.
As seen from the foregoing, the error data correcting system according to the invention has an excellent performance with a simple matrix generating circuit.
The error data correcting system according to the invention is readily adaptable for a system for transmitting, recording and reproducing digitized information signals by PCM, for example, and other digital systems as well.
Claims
What is claimed is:
1. An error data correcting system in which a series of n data words W.sub.1 through W.sub.n each including m bits has associated therewith a P check code ##EQU24## and a Q check code ##EQU25## the system for correcting erroneous data words W.sub.c, and W.sub.d, to produce correct data words W.sub.c and W.sub.d (l.ltoreq.c<d.ltoreq.n), the system generating a first syndrome value ##EQU26## and a second syndrome value ##EQU27## when the series of data words includes erroneous data words W.sub.c', and W.sub.d', respectively, the system comprising: a first input terminal for receiving said series of data words and said associated first and second syndrome values; an auxiliary matrix circuit for multiplying said first syndrome value by an auxiliary matrix T.sup.-(n+1) ; a T matrix operation circuit for receiving the output of said auxiliary matrix circuit and for shifting said received value c positions to output T.sup.c-(n+1) S.sub.2 ; a P register coupled to said first input terminal for receiving said first syndrome value; switch means for selectively coupling the output of said P register to the input of said T matrix operation circuit to cause said T matrix operation circuit to store S.sub.1 +T.sup.c-(n+1) S.sub.2 ; a second input terminal for receiving an error data pointer; an error word control circuit coupled to said second input terminal for generating an interval signal k=d-c corresponding to the series positional difference between said second error word W.sub.d' and said first error word W.sub.c' in response to said error data pointer; a first gate circuit coupled to the output of said T matrix operation circuit; a matrix generating circuit for receiving said interval signal k from said error word control circuit, for generating a matrix signal corresponding to a specific bit in the output of said T matrix operation circuit, and for supplying said matrix signal to said first gate circuit, said first gate circuit for combining said output of said T matrix operation circuit (T.sup.c-(n+1) S.sub.2 with said matrix signal k to generate a second corrected data word W.sub.de ; a first buffer for storing said second corrected data word W.sub.de ; a second buffer coupled to said P register for receiving and storing said first syndrome value S.sub.1 ; and means coupled to said first buffer for receiving said second corrected data word W.sub.de and to said second buffer for receiving said first syndrome value S.sub.1 and for combining said second corrected data word W.sub.de and said first syndrome value S.sub.1 to generate a first corrected data word W.sub.ce.
2. An error data correcting system according to claim 1 wherein said receiving and combining means comprises: an adder coupled to said first buffer for receiving said second corrected data word W.sub.ce ; and a second gate circuit coupled to said second buffer and said adder to selectively supply said first syndrome value S.sub.1 to said adder to enable said adder to add said first syndrome value S.sub.1 and said second corrected data word W.sub.de to generate said first corrected data word W.sub.ce.
3. An error data correcting system according to claim 2 further including: an output terminal; means for transferring said series of data words W.sub.l through W.sub.n including said error data words W.sub.c' and W.sub.d' from said input terminal to said output terminal; and means for replacing said first and second error data words W.sub.c' and W.sub.d' with said first and second corrected data words W.sub.ce and W.sub.de, respectively, as said series of data words are transferred from said input terminal to said output terminal.
4. An error data correcting system according to claim 3 wherein said transferring means comprises a delay circuit.
5. An error data correcting system according to claim 1 wherein said T matrix operation circuit comprises: a serial to parallel converter for converting said output of said auxiliary matrix to a plurality of parallel data words; a plurality of shift registers, each of said shift registers being associated with a different one of said plurality of parallel data words; a plurality of adder circuits, each of said adder circuits being connected between a different pair of said shift registers; a pluraity of gate circuits in one-to-one association with said plurality of parallel data words, each of said gate circuits being coupled to said adder circuit preceding said shift register associated with said parallel data word associated with said gate circuit; and means for controlling said gate circuits to enable the selective transfer of said parallel data words to said associated shift registers.
Patent Citations (12)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3418630 | 1968-12-01 | Van Duuren | |
| US3629824 | 1971-12-01 | Bossen | |
| US3697948 | 1972-10-01 | Bossen | |
| US3745528 | 1973-07-01 | Patel | |
| US3868632 | 1975-02-01 | Hong et al. | |
| US4052698 | 1977-10-01 | Ragle | |
| FRX2448255 | 1980-01-01 | ||
| GBX1198510 | 1970-07-01 | ||
| GBX1224423 | 1971-03-01 | ||
| GBX1313488 | 1973-04-01 | ||
| GBX1369725 | 1974-10-01 | ||
| GBX1468604 | 1977-03-01 |
Non-Patent Literature (3)
- Art.: "Encoder and Decoder for the 2-Redundant B-Adjacent Perfect Codes" from IBM Technical Disclosure Bulletin, vol. 14, No. 3, pp. 680-682, by D. C. Bossen and A. M. Patel.
- Art.: "Optimal Rectangular Code for High Density Magnetic Tapes" from IBM Journal of Research and Development, Nov. 1974, pp. 579-588, by A. M. Patel and S. J. Hong.
- Art.: "A General Class of Maximal Codes for Computer Applications" from IEEE Transactions on Computers, vol. C-21, No. 12, Dec. 1972, pp. 1322-1331, by Se June Hong and Arvind M. Patel.