Alphanumeric Display Controlled by Microprocessor

This invention relates to an information display system and more particularly to a display device for performing a new and unique display operation in an electronic dictionary and the like.

It is very convenient if information represented by one or more English sentences or one or more Japanese sentences are displayed in an easy-reading manner in an electronic dictionary or the like. The assignee of this application has proposed one approach in our copending application Ser. No. 058,666 "DISPLAY DEVICE FOR ELECTRONIC CALCULATORS OR THE LIKE" filed on July 18, 1979 and now U.S. Pat. No. 4,298,865, wherein a visual display of a display panel is shifted digit by digit every given period of time. However, more attractive methods for displaying information on a display panel of a limited digit capacity appear possible.

Accordingly, it is an object of the present invention to provide a new display system different from the conventional manner.

In summary, according to the present invention, information such as an English sentence "May I ask you to post this letter?" is first stored word by word in a first memory means. "May I ask you to post" is fetched from the first memory means and loaded into a second memory means for displaying the same on a display panel. After a predetermined period of time has gone on, the display is shifted by the number of characters in the next succeeding word to be displayed, i.e., four characters in "this" to establish a length of blank digits necessary for displaying "this". Subsequent to the shift operation the blank digits of the display panel are filled with "this".

For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic view of a programmable calculator according to one preferred form of the present invention;

FIG. 2 is a block diagram of an internal arrangement of the calculator of FIG. 1;

FIG. 3 is a block diagram showing details of a display control contained in FIG. 2;

FIGS. 4A through 4D are schematic block diagrams of a typical central processor unit (CPU);

FIG. 5 is an equivalent circuit diagram of the CPU of FIGS. 4A through 4D;

FIG. 6 is a view showing an example of a dot matrix display pattern on a display panel according to the present invention;

FIG. 7 is a view for explanation of a storage area in a display data memory;

FIG. 8 is a view showing a sequence of information display mode according to the present invention;

FIG. 9 is an illustration of operation by which information contained in an external memory is transferred into the display data memory in the preferred embodiment of the present invention;

FIG. 10 is a flow chart of a particular operation according to the preferred embodiment of the present invention;

FIG. 11 is a flow chart of the subroutine of display for a limited period of time as shown in FIG. 10;

FIG. 12 is a flow chart of the subroutine of blank decision in FIG. 10;

FIG. 13 is a view showing a sequence of information display mode according to another preferred embodiment of the present invention; and

FIG. 14 is a flow chart showing a particular operation in the last embodiment of the present invention.

FIG. 1 shows the appearance of a programmable calculator equipped with a display panel constructed according to one preferred embodiment of the present invention, wherein the display panel DSP is typically a 21-digit dot matrix display panel or a segmented display panel. A keyboard K has a plurality of alphabet keys A-Z through which information to be displayed is introduced. Upon actuation of a display key DIS the information introduced via the keyboard K is displayed on the display panel DSP.

FIG. 2 is a schematic block diagram of the calculator shown in FIG. 1. A central processor unit (CPU) includes a random access memory RAM for data storage and a read only memory for program storage. The keyboard K is operatively connected to key strobe output terminals w.sub.1 -w.sub.8 and key input terminals k.sub.1 -k.sub.4 of the CPU. The display panel DSP on the other hand is connected to opposite electrode signal output terminals h.sub.1 -h.sub.7. Operatively associated with the CPU are a display control circuit DSC and a pair of external memories MU.sub.1 and MU.sub.2 both serving as a first memory means. The display control circuit DSC may be implemented with a conventional random access memory having a display data storage DRM. The display control circuit DSC is connected to the CPU via a read/write signal terminal R/W, a display/disable control signal output terminal DIS, a memory digit address output terminal B.sub.L T, a memory file address output terminal B.sub.M T, an address bus AB and a data bus DB.

The display control circuit DSC included in FIG. 3, is best shown in FIG. 2, wherein the display data storage DRM is connected to an address decoder DC which decodes information sent from the memory digit address output terminal B.sub.L T and the memory digit address output terminal B.sub.M T of the central processor unit CPU via an address buffer ADB. A read/write control circuit RWC allows information to be read from or written in the display data storage DRM via the data input and output terminals DI/O in response to a read/write signal from the read/write terminal R/W. The contents of the display data storage DRM are supplied to and decoded by a segment driver SED. The display data appear at the output terminals S.sub.1 -S.sub.126. The segment driver SED delivers enable waveform signals to enable the display panel DSP when the display/disable control signal DIS assumes a logic "1" level, and disable waveform signals to disable the display panel DSP when the said control signal assumes a logic "0" level.

FIG. 5, a composite diagram of FIGS. 4A-4D, shows a logic wiring diagram of a typical example of the CPU scheme in the calculator whereby the display operation of the present invention is effected. It is understood that the illustrated CPU architecture is designed for general purposes and some of its functions are not concerned with the present invention.

Referring to FIG. 4A, a random access memory RAM is of a 4 bit input and output capacity and accessible to any specific input digit position thereof as identified by a digit address and a file address. The RAM includes a digit address counter with its output terminal BL1, a digit address decoder DC.sub.1, a file address counter BM with its output terminal BM1, a file address decoder DC.sub.2 and an adder AD.sub.1 which serves as an adder and a subtractor respectively in the absence and presence of a control instruction 14 . It further includes a second adder AD.sub.2 and a gate G.sub.1 for providing either a digit "1" or an operand I.sub.A to an input to the adder/subtractor AD.sub.1 and delivering 1 or I.sub.A when a control instruction 15 or 16 is developed, respectively. The memory digit address counter BL has a countdown circuit SB. An input gate G.sub.2 is provided for the memory digit address counter BL, which enables the output of the adder/subtractor AD.sub.1, the operand I.sub.A, the other operand I.sub.B and the output of the countdown circuit SB to pass therethrough respectively when control instruction 10 , 11 , 12 and 74 are developed. A gate G.sub.3 is disposed to provide a digit "1" or the operand I.sub.A to an input to the adder/subtractor AD.sub.2, the former being provided upon the development of an instruction 5 and the latter upon the development of an instruction 6 . A circuit EO supplies to a gate G.sub.4 an exclusive OR sum of the both counts of the memory file address counter BM and the accumulator ACC. The gate G.sub.4 is an input gate to the memory file address BM which enables the output of the adder AD.sub.2, the operand I.sub.A, the contents of an accumulator ACC and the output of EO to pass upon the development of instructions 7 , 8 , 9 and 75 . A file selection gate G.sub.5 is further provided for the memory RAM. A decoder DC.sub.3 translates the operand I.sub.A and supplies a gate G.sub.6 with a desired bit specifying signal. The gate G.sub.6 is an input gate to the memory RAM and contains a circuit arrangement for introducing a binary code "1" into a specific bit position of the memory RAM identified by the operand decoder DC.sub.3 and a binary code "0" into a specific bit position of the memory RAM identified by DC.sub.3, respectively, when a control instruction 2 or 3 is developed. Upon the development of an instruction 4 the contents of the accumulator ACC are read out. There are further provided display controlling flags N.sub.1 and N.sub.2. An input gate G.sub.46 to N.sub.1 and N.sub.2 is enabled with 69 . A read/write circuit RWA with an output terminal R/W directs read and write operations in response to 70 and 71 , respectively.

Referring to FIG. 4B, in conjunction with FIG. 4A, a read only memory ROM has its associated program counter PL which specifies a desired step in the read only memory ROM. The read only memory ROM further contains a step access decoder DC.sub.4 and an output gate G.sub.7 which shuts off transmission of the output of the ROM to an instruction decoder DC.sub.5 when a judge flip flop (F/F) J is set. The instruction decoder DC.sub.5 is adapted to decode instruction codes derived from the ROM and divide them into an operation code area I.sub.O and operand areas I.sub.A and I.sub.B, the operation code being decoded into any one of the control instructions 1 - 75 . The decoder DC.sub.5 is further adapted to output the operand I.sub.A or I.sub.B as it is when sensing an operation code accompanied by an operand. An adder AD.sub.3 increments the contents of the program counter PL by one. An input gate G.sub.8 associated with the program counter PL provides the operand I.sub.A and transmits the contents of a program stack register SP when the instructions 20 and 61 are developed, respectively. When the instructions 20 , 61 and 60 are being processed, any output of the adder AD.sub.3 is not transmitted. Otherwise the AD.sub.3 output is transmitted to automatically load "1" into the contents of the program counter PL. A flag flip flop FC has an input gate G.sub.9 therefor which introduces binary codes "1" and "0" into the flag flip flop FC when the instructions 17 and 18 are developed, respectively. A key signal generating gate G.sub.10 provides the output of the memory digit address decoder DC.sub.1 without any change when the flag F/F FC is in the reset state (0), and renders all outputs I.sub.1 -I.sub.n "1" whatever output DC.sub.1 provides when FC is in the set state (1). There are further provided a clock generator CG, a divider DV, a displaying counter H and an opposite electrode select signal generator BP for the liquid crystal display panel with opposite electrode signal output terminals h.sub.1 -h.sub.7. Referring to FIG. 4C, the accumulator ACC is 4 bits long and a temporary register X is also 4 bits long. An input gate G.sub.11 for the temporary register X transmits the contents of the accumulator ACC and the stack register SX respectively upon the development of the instructions 29 and 59 . Hereinafter, "F/F" and "flip-flop" are used interchangeably.

An adder AD.sub.4 executes binary addition on the contents of the accumulator ACC and other data. The output C.sub.4 of the adder AD.sub.4 assumes "1" when the most significant bit or fourth bit binary addition yields a carry. A carry F/F C has its associated input gate G.sub.12 which sets "1" into the carry F/F C in the presence of "1" of the fourth bit carry C.sub.4 and "0" into the same in the absence of C.sub.4 (0). "1" and "0" are set into F/F C upon the development of instructions 21 and 22 , respectively. A carry (C) input gate G.sub.13 enables the adder AD.sub.4 to perform binary addition with a carry and thus transmits the output of the carry F/F C into the adder AD.sub.4 in response to the instruction 25 . An input gate G.sub.14 is provided for the adder AD.sub.4 and transfers the output of the memory RAM and the RAM and the operand I.sub.A upon the development of instructions 23 and 24 , respectively. An output buffer register F has a 4 bit capacity and an input gate G15 which enables the contents of the accumulator ACC to enter into F upon the development of instruction 31 . An output decoder SD decodes the contents of the output buffer F into display segment signals SS.sub.1 -SS.sub.n. An output buffer register W has a shift circuit SHC which shifts the overall bit contents of the output buffer register W one bit to instruction the right at a time in response to 32 or 33 . An input gate G.sub.16 for the output buffer register W leads "1" and "0" into the first bit position of the said register W upon instructions 32 and 33 , respectively. Immediately before "1" or "0" enters into the first bit position of the output buffer register W the output buffer shift circuit SHC becomes operative.

An output control flag F/F NP has an input gate G.sub.17 for receiving "1" and "0" upon the development of instructions 34 and 35 , respectively.

The buffer register W is provided with an output control gate G.sub.18 for providing the respective bit outputs thereof at one time only when the output control flag F/F NP is in the set state (1). The outputs of the output buffer register W are available as key strobe signals. There are further provided a judge F/F J, (see FIG. 4B) an inverter IV.sub.1 and an input gate G.sub.19 to the judge F/F J for transferring the state of an input KN.sub.1 into J upon the development of instruction 36 . In the case where KN.sub.1 =0, J=1 because of intervention of the inverter IV.sub.1. An input gate G.sub.20 to the judge F/F J is adapted to transfer the state of an input KN.sub.2 into J upon instruction 37 . It is noted that, when KN.sub.2 =0, J=1 via the inverter IV.sub.2. As input gate G.sub.21 to the judge F/F J is adapted to transfer the state of the input KF.sub.1 into J upon instruction 38 . When KF.sub.1 =0, J=1 because of intervention of the inverter IV.sub.3. An input gate G.sub.22 to the judge F/F J is adapted to transfer the state of the input KF.sub.2 into J upon instruction 39 . When KF.sub.2 =0, J=1 because of the intervened inverter IV.sub.4. An input gate G.sub.23 is provided for the judge F/F J for transmission of the state of an input AK into J upon the development of instruction 40 . When AK=1, J=1. An input gate G.sub.24 is provided for the judge F/F J to transmit the state of an input TAB into J pursuant to instruction 41 . When TAB=1, J=1. A gate G.sub.28 is provided for setting the judge F/F J upon the development of instruction 46 . A comparator V.sub.1 (FIG. 4B) compares the contents of the memory digit address counter BL with preselected data and provides an output "1" if there is agreement. The comparator V.sub.1 becomes operative either instruction 43 or 44 is developed. The data to be compared are derived from a gate G.sub.26 which is an input gate to the comparator V.sub.1. The data n.sub.2 to be compared are specific higher address values which are often available in controlling the RAM. A comparison input gate G.sub.26 provides n.sub.1 and n.sub.2 for comparison purposes upon the development of instructions 43 and 44 , respectively.

An input gate G.sub.27 is provided for the judgment F/F J to enter "1" into F/F J when the carry F/F C assumes "1" upon the development of instruction 45 .

A decoder DC.sub.6 decodes the operand I.sub.A and helps decide as to whether or not the content of a desired bit position of the RAM is "1". A gate G.sub.28 transfers the contents of the RAM as specified by the operand decoder DC.sub.6 into the judge F/F J when instruction 46 is derived. When the specified bit position of the RAM assumes "1", J=1. A comparator V.sub.2 decides whether or not the contents of the accumulator ACC are equal to the operand I.sub.A and provides an output "1" when the affirmative answer is provided. The comparator V.sub.2 becomes operative according to instruction 47 . A comparator V.sub.3 decides under instruction 48 whether the contents of the memory digit address counter BL are equal to the operand I.sub.A and provides an output "1" when the affirmative answer is obtained. A comparator V.sub.4 decides whether the contents of the accumulator ACC agree with the contents of the RAM and provides an output "1" in the presence of the agreement. A gate G.sub.29 transfers the fourth bit carry C.sub.4 occurring during addition into the judge F/F J. Upon the development of instruction 50 C.sub.4 is sent to F/F J. J=1 in the presence of C.sub.4. A flage flip flop FA has an input gate G.sub.31 which provides outputs "1" and "0" upon the development of instructions 52 and 53 , respectively. An input gate G.sub.32 is provided for setting the judge F/F J when the flag flip flop FA assumes "1". A flag flip flop F.sub.B also has an input gate G.sub.33 which provides outputs "1" and "0" upon instructions 55 and 56 , respectively. An input gate G.sub.34 for the judge F/F J is adapted to transfer the contents of the flag flip flop F.sub.B into the F/F J upon the development of instruction 52 . An input gate G.sub.44 to the judge F/F J is enabled to transfer an input .alpha. in response to instruction 68 . An input gate G.sub.35 associated with the judge F/F J is provided for transmission of the contents of the input .beta. upon instruction 19 . When .beta.=1, J=1. An output gate G.sub.45 from the accumulator ACC transfers the contents of the accumulator ACC to the data input/output terminals DIO of the display data storage DRM in response to instruction 73 . An input gate G.sub.35 associated with the input of the accumulator ACC is provided for transferring the output of the adder AD.sub.4 upon instruction 26 and transferring the contents of the accumulator ACC after inverted via an inverter IV.sub.5 upon instruction 27 . The contents of the memory RAM are transferred upon instruction 28 , the operand I.sub.A upon instruction 13 , the 4 bit input contents k.sub.1 -k.sub.4 upon instruction 57 , the contents of the stack register SA upon instruction 59 and the data from the data storage DRM via DIO upon instruction 72 . A stack register SA provides the output outside the present system. A stack register SC also provides the output outside the system. An input gate G.sub.37 associated with the stack register SA transfers the contents of accumulator ACC upon instruction 58 . An input gate G.sub.38 associated with the stack register SX transfers the contents of the temporary register X upon instruction 58 . A program stack register SP has an input gate G.sub.39 for loading the contents of the program counter PL plus "1" through the adder into the program stack register, upon instruction 60 .

An illustrative example of the instruction codes contained within the ROM of the CPU structure, the name and function of the instruction codes and the control instructions developed pursuant to the instruction codes will now be tabulated in Table 1 wherein A designates the instruction codes, B designates the instruction name, and D designates the CPU control instructions. The instruction descriptions are given in narrative sequence in the order of the instruction names B.

SKIP: Only the program counter PL is incremented without executing a next program step instruction, thus skipping a program step.

AD: A binary addition is effected on the contents of the accumulator ACC and the contents of the RAM, the addition results being loaded back into the accumulator ACC.

ADC: A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry F/F C, the results being loaded back to the accumulator ACC.

ADCSK: A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry flip flop C, the results being loaded into the accumulator ACC. If the fourth bit carry C.sub.4 occurs in the results, then a next program step is skipped.

ADI: A binary addition is achieved upon the contents of the accumulator ACC and the operand I.sub.A and the results are loaded into the accumulator ACC. If the fourth bit carry C.sub.4 is developed in the addition results, then a next program step is skipped.

DC: The operand I.sub.A is fixed as "1010" (a decimal number "10") and a binary addition is effected on the contents of the accumulator ACC and the operand I.sub.A in the same way as in the ADI instruction. The decimal number 10 is added to the contents of the accumulator ACC, the results of the addition being loaded into ACC.

SC: The carry F/F C is set ("1" enters into C).

RC: The carry F/F C is reset ("0" enters into C).

SM: The contents of the operand I.sub.A are decoded to give access to a desired bit position of the memory specified by the operand ("1" enters).

RM: The contents of the operand I.sub.A are interpreted to reset a desired bit position of the memory specified by the operand ("0" enters).

COMA: The respective bits of the accumulator ACC are inverted and the resulting complement to "15" is introduced into ACC.

LDI: The operand I.sub.A enters into the accumulator ACC.

L: The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the file address counter BM.

LI: The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the memory file address counter BM. At this time the memory digit address counter BL is incremented. If the contents of BL agree with the preselected value n.sub.1, then a next program step is skipped.

LD: The contents of the memory RAM are exchanged with the contents of ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is decremented. In the event that the contents of BL agree with the preselected value n.sub.2, then a next program step is skipped.

X: The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is loaded into the memory file address counter BM.

XI: The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is incremented. In the event that BL is equal to the preselected value n.sub.1, a next program step is skipped.

XD: The contents of the memory RAM replaces the contents of the accumulator ACC, the operand I.sub.A being sent to the memory file address counter BM. The memory digit address counter BL at this time is incremented. If the contents of BL are equal to n.sub.2, then a next program step is skipped.

LBLI: The operand I.sub.A is loaded into the memory digit address counter BL.

LB: The operand I.sub.A is loaded into the memory file address counter BM and the operand B to the memory digit address counter BL.

ABLI: The operand I.sub.A is added to the contents of the memory digit address counter BL in a binary addition fashion, the results being loaded back to BL. If the contents of BL are equal to n.sub.1, then no next program step is carried out.

ABMI: The operand I.sub.A is added to the contents of the memory file address counter BM in a binary fashion, the results being into BM.

T: The operand I.sub.A is loaded into the program step counter PL.

SKC: If the carry flip flop C is "1", then no next program step is taken.

SKM: The contents of the operand I.sub.A are decoded and a next program step is skipped as long as a specific bit position of the memory specified by the operand I.sub.A assumes "1".

SKBI: The contents of the memory digit address counter BL are compared with the operand I.sub.A and a next succeeding program step is skipped when there is agreement.

SKAI: The contents of the accumulator ACC are compared with the operand I.sub.A and if both are equal to each other a next program step is skipped.

SKAM: The contents of the accumulator ACC are compared with the contents of the RAM and if both are equal a next program step is skipped.

SKN.sub.1 : When the input KN.sub.1 is "0", a next program step is skipped.

SKN.sub.2 : When the input KN.sub.2 is "0", a next program step is skipped.

SKF.sub.1 : When the input KF.sub.1 is "0", a next program step is skipped.

SKF.sub.2 : When the input KF.sub.2 is "0", a next program step is skipped.

SKAK: When the input AK is "1", a next program step is skipped.

SKTAB: When the input TAB is "1", a next program step is skipped.

SKFA: When the flag F/F F/A assumes "1" a next program step is skipped.

SKFB: When the flag F/F F.sub.B assumes "1", a next program step is skipped.

SKFD: When the flag F/F F.sub.D assumes "1", a next program step is skipped.

SKFE: When the flag F/F F.sub.E assumes "1", a next program step is skipped.

WIS: The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position) receiving "1".

WIR: The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position being loaded with "0").

NPS: The output control F/F N.sub.p for the buffer register W is set ("1" enters).

NPR: The buffer register output control flip flop N.sub.p is reset ("0" enters therein).

ATF: The contents of the accumulator ACC are transferred into the output buffer register F.

LXA: The contents of the accumulator ACC are unloaded into the temporary register X.

XAX: The contents of the accumulator ACC are exchanged with the contents of the temporary register X.

SFA: The flag F/F FA is set (an input of "1").

RFA: The flag F/F FA is reset (an input of "0").

SFB: The flag flip flop F.sub.B is set (an input of "1").

RFB: The flag flip flop F.sub.B is reset (an input of "0").

SFC: An input testing flag F/F F.sub.C is set (an input of "1").

RFC: The input testing flag F/F F.sub.C is reset (an input of "0").

SFD: The input testing flag F/F F.sub.D is set (an input of "1").

RFD: The input testing flag F/F F.sub.D is reset (an input of "0").

SFE: The input testing flag F/F F.sub.E is set (an input of "1").

RFE: The input testing flag F/F F.sub.E is reset (an input of "0").

SKA: When an input .alpha. is "1", a next program step is skipped.

SKB: When an input .beta. is "1", a next program step is skipped.

KTA: The inputs k.sub.1 -k.sub.4 are introduced into the accumulator ACC.

STPO: The contents of the accumulator ACC are sent to the stack register SA and the contents of the temporary register X to the stack register SX.

EXPO: The contents of the accumulator ACC are exchanged with the stack register SA and the contents of the temporary register X with the stack register SX.

TML: The contents of the program counter P.sub.L incremented by one are transferred into the program stack register SP and the operand I.sub.A into the program counter P.sub.L.

RIT: The contents of the program stack register SP are transmitted into the program counter P.sub.L.

LN.sub.1 : The operands I.sub.A and I.sub.B enter the display and key input controlling flag F/Fs N.sub.1 and N.sub.2, respectively.

READ: Data externally applied to D.sub.I/O are introduced into the accumulator ACC.

STOR: The contents of the accumulator ACC are unloaded into D.sub.I/O.

EX: The contents of the memory RAM are exchanged with that of the accumulator ACC and an exclusive-OR'ed output of the operand I.sub.A and the contents of the memory file address counter B.sub.M is supplied to B.sub.M.

DECB: The memory digit address counter B.sub.L is decremented by "1". When the contents of B.sub.L are equal to the preset value n.sub.2, a next instruction is skipped.

Table 2 sets forth the relationship between the operation codes contained within the ROM of the CPU structure and the operand.

Taking an example wherein the output of the read only memory ROM is 10 bit long, the instruction decoder DC.sub.5 decides whether the instruction AD or COMA (see Table 1) assumes "0001011000" or "0001011111" and develops the control instructions 23 , 26 , or 27 . SKBI is identified by the fact that the upper six bits assume "000110", the lower 4 bits "0010" being treated as the operand I.sub.A and the remaining ninth and tenth bits "11" as the operand I.sub.B. The operand forms part of instruction words and specifies data and addresses for next succeeding instructions and can be called an address area of an instruction.

Major processing operations (a processing list) of the CPU structure will now be described in sufficient detail.

(I) A same numeral N is loaded into a specific region of the memory RAM (NNN.fwdarw.X)

(II) A predetermined number of different numerals are loaded into a specific region of the memory (N.sub.1, N.sub.2, N.sub.3, . . . .fwdarw.X)

(III) The contents of a specific region of the memory are transferred into a different region of the memory (X.fwdarw.Y)

(IV) The contents of a specific region of the memory are exchanged with that of a different region (X.rarw..fwdarw.Y)

(V) A given numeral N is added or subtracted in a binary fashion from the contents of a specific region of the memory (X.+-.N)

(VI) The contents of a specific region of the memory are added in a decimal fashion to the contents of a different region (X.+-.Y)

(VII) The contents of a specific region of the memory are one digit shifted (X right, X left).

(VIII) A one bit conditional F/F associated with a specific region of the memory is set or reset (F set, F reset) (IX) The state of the one bit conditional F/F associated with a specific region of the memory is sensed and a next succeeding program address is changed according to the results of the state detection.

(X) It is decided whether the digit contents of a specific region of the memory reach a preselected numeral and a next succeeding program step is altered according to the results of such decision.

(XI) It is decided whether the plural digit contents of a specific region of the memory are equal to a preselected numeral and a program step is altered according to the results of the decision.

(XII) It is decided whether the digit contents of a specific region of the memory are smaller than a given value and a program step to be next executed is changed according to the decision.

(XIII) It is decided whether the contents of a specific region of the memory are greater than a given value and the results of such decision alter a program step to be next executed.

(XIV) The contents of a specific region of the memory are displayed. (XV) What kind of a key switch is actuated is decided.

(XVI) The external memory is shifted digit by digit within the same memory file address.

The above processing events in (I)-(XVI) above are executed according to the instruction codes step by step in the following manner.

P.sub.2 . . . After the overall contents of the register W are one bit shifted to the right, its first bit is loaded with "0". This procedure is repeated via P.sub.4 until C.sub.4 =1 during P.sub.3, thus resetting the overall contents of W.

P.sub.3 . . . The operand I.sub.A is decided as "1111" and AC+1111 is effected (this substantially corresponds to ACC-1). Since ACC is loaded with n.sub.1 during P.sub.1, this process is repeated n.sub.1 times. When the addition of "1111" is effected following ACC=0, the fourth bit carry C.sub.4 assumes "0". When this occurs, the step is advanced to P.sub.4. Otherwise the step is skipped up to P.sub.5.

P.sub.4 . . . When the fourth bit carry C.sub.4 =0 during ACC+1111, the overall contents of W are reduced to "0" to thereby complete all the pre-display processes. The first address P.sub.6 is set for the memory display steps.

P.sub.5 . . . In the event that the fourth bit carry C.sub.4 =1 during ACC+1111, the overall contents of W have not yet reduced to "0". Under these circumstances P.sub.2 is reverted to repeat the introduction of "0" into W.

P.sub.6 . . . The first digit position of the memory region which contains data to be displayed is identified by the file address m.sub.A and the digit address n.sub.A.

P.sub.7 . . . After the contents of the register W for generating the digit selection signals are one bit shifted to the right, its first bit position is loaded with "1" and thus ready to supply the digit selection signal to the first digit position of the display.

P.sub.8 . . . The contents of the specific region of the memory are unloaded into ACC. The file address of the memory still remains at m.sub.A, whereas the digit address is decremented for the next succeeding digit processing.

P.sub.9 . . . The contents of the memory is shifted from ACC to the buffer register F. The contents of the register F are supplied to the segment decoder SD to generate segment display signals.

P.sub.10 . . . To lead out the contents of the register W as display signals, the conditional F/F N.sub.p is supplied with "1" and placed into the set state. As a result of this, the contents of the memory processed during P.sub.9 are displayed on the first digit position of the display.

P.sub.11 . . . A count initial value n.sub.2 is loaded into ACC to determine a one digit long display period of time.

P.sub.12 . . . ACC-1 is carried out like P.sub.3. When ACC does not assume "0" (when C.sub.4 =1) the step is skipped up to P.sub.14.

P.sub.13 . . . A desired period of display is determined by counting the contents of ACC during P.sub.12. After the completion of the counting P.sub.15 is reached from P.sub.13. The counting period is equal in length to a one-digit display period of time.

P.sub.14 . . . Before the passage of the desired period of display the step is progressed from P.sub.12 to P.sub.14 with skipping P.sub.13 and jumped back to P.sub.12. This procedure is repeated.

P.sub.15 . . . N.sub.p is reset to stop supplying the digit selection signals to the display. Until N.sub.p is set again during P.sub.10, overlapping display problems are avoided by using the adjacent digit signals.

P.sub.16 . . . The register W is one bit shifted to the right and its first bit position is loaded with "0". "1" introduced during P.sub.7 is one bit shifted down for preparation of the next succeeding digit selection.

P.sub.17 . . . It is decided whether the ultimate digit of the memory to be displayed has been processed and actually whether the value n.sub.E of the last second digit has been reached because the step P.sub.8 of B.sub.L -1 is in effect.

P.sub.18 . . . In the event that ultimate digit has not yet been reached, P.sub.8 is reverted for the next succeeding digit display processing.

P.sub.19 . . . For example, provided that the completion of the display operation is conditional by the flag F/F FA, FA=1 allows P.sub.20 to be skipped, thereby concluding all the displaying steps.

P.sub.20 . . . If FA=1 at P.sub.19, the display steps are reopened from the first display and the step is jumped up to P.sub.6. ##STR15## P.sub.1 . . . The bit number n.sub.1 of the buffer register W is loaded into ACC to reset the overall contents of the buffer register W for generating digit selection signals effective to drive a display panel on a time sharing basis.

P.sub.2 . . . After the overall contents of the register W are one bit shifted to the right, its first bit is loaded with "0". This procedure is repeated via P.sub.4 until C.sub.4 =1 during P.sub.3, thus resetting the overall contents of W.

P.sub.3 . . . The operand I.sub.A is decided as "1111" and AC+1111 is effected (this substantially corresponds to ACC-1). Since ACC is loaded with n.sub.1 during P.sub.1, this process is repeated n.sub.1 times. When the addition of "1111" is effected following ACC=0, the fourth bit carry C.sub.4 assumes "0". When this occurs, the step is advanced to P.sub.4. Otherwise the step skipped up to P.sub.5.

P.sub.4 . . . When the fourth bit carry C.sub.4 =0 during ACC+1111, the overall contents of W are reduced to "0" to thereby complete all the pre-display processes. The first address P.sub.6 is set for the memory display steps.

P.sub.5 . . . In the event that the fourth bit carry C.sub.4 =1 during ACC+1111, the overall contents of W have not yet reduced to "0". Under these circumstances P.sub.2 is reverted to repeat the introduction of "0" into W.

P.sub.6 . . . The upper four bits of the first digit position of the memory region which contains data to be displayed are identified by the file address m.sub.A and the digit address m.sub.A.

P.sub.7 . . . The contents of the specific region of the memory are unloaded into ACC. The file address of the memory still remains at m.sub.A, whereas the digit address is decremented to specify the lower four bits.

P.sub.8 . . . The contents of ACC, the upper four bits, are transmitted into the temporary register X.

P.sub.9 . . . The contents of the specific region of the memory are unloaded into ACC. The file address of the memory still remains at m.sub.A, whereas the digit address is decremented to specify the upper four bits of the next succeeding digit.

P.sub.10 . . . The contents of ACC are unloaded into the stack register SA and the contents of the temporary register X into the stack register SX.

P.sub.11 . . . After the contents of the register W for generating the digit selection signals are one bit shifted to the right, its first bit position is loaded with "1" and thus ready to supply the digit selection signal to the first digit position of the display.

P.sub.12 . . . To lead out the contents of the register W as display signals, the conditional F/F N.sub.p is supplied with "1" and placed into the set state. As a result of this, the contents of the memory processed during P.sub.10 are displayed on the first digit position of the display.

P.sub.13 . . . A count initial value n.sub.2 is loaded into ACC to determine a one digit long display period of time.

P.sub.14 . . . ACC-1 is carried out like P.sub.3. When ACC assumes "0" P.sub.15 is reached and when ACC.noteq.0 (when C.sub.4 =1) the step is skipped up to P.sub.16. This procedure is repeated.

P.sub.15 . . . A desired period of display is determined by counting the contents of ACC during P.sub.14. After the completion of the counting P.sub.17 is reached from P.sub.15. The counting period is equal in length to a one-digit display period of time.

P.sub.16 . . . Before the passage of the desired period of display the step is progressed from P.sub.14 to P.sub.16 with skipping P.sub.15 and jumped back to P.sub.14. This procedure is repeated.

P.sub.17 . . . N.sub.p is reset to stop supplying the digit selection signals to the display. Until N.sub.p is set again during P.sub.10, overlapping display problems are avoided by using the adjacent digit signals.

P.sub.18 . . . The register W is one bit shifted to the right and its first bit position is loaded with "0". "1" introduced during P.sub.7 is one bit shifted down for preparation of the next succeeding digit selection.

P.sub.19 . . . It is decided whether the ultimate digit of the memory to be displayed has been processed and actually whether the value n.sub.E of the last second digit has been reached because the step p.sub.9 of B.sub.L -1 is in effect.

P.sub.20 . . . In the event that ultimate digit has not yet been reached, P.sub.7 is reverted for the next succeeding digit display processing.

P.sub.20 . . . The step is jumped to P.sub.30 as long as any one of the keys connected to the key input KN.sub.1 is actuated.

P.sub.22 -P.sub.27 . . . It is decided whether any one of the keys each connected to the respective key inputs KN.sub.2 -KF.sub.2 and in the absence of any actuation the step is advanced toward the next succeeding step. To the contrary, the presence of the key actuation leads to P.sub.30.

P.sub.28 . . . When any key is not actuated, F/F FC is reset to thereby complete the decision as to the key actuations.

P.sub.29 . . . The step is jumped up to P.sub.6 to reopen the display routine.

P.sub.30 . . . When any key is actually actuated, the memory digit address is set at n.sub.1 to generate the first key strobe signal I.sub.1.

P.sub.31 . . . It is decided if the first key storbe signal I.sub.1 is applied to the key input KN.sub.1 and if not the step is advanced toward P.sub.33.

P.sub.32 . . . When the first key strobe signal I.sub.1 is applied to the key input KN.sub.1, which kind of the keys is actuated is decided. Thereafter, the step is jumped to P.sub.A to provide proper controls according to the key decision. After the completion of the key decision the step is returned directly to P.sub.1 to commence the displaying operation again (P.sub.Z is to jump the step to P.sub.1)

P.sub.33 -P.sub.38 . . . It is sequentially decided whether the keys coupled with the first key strobe signal I.sub.1 are actuated. If a specific key is actuated, the step jumps to P.sub.B -P.sub.D for providing appropriate controls for that keys.

P.sub.39 . . . This step is executed when no key coupled.

P.sub.1 . . . The file address m.sub.A and the digit address n.sub.E of the memory step P.sub.5 are selected.

P.sub.2 . . . The contents of the accumulator ACC are loaded in the register X for the time being.

P.sub.3 . . . ACC is loaded with the contents specified at the step P.sub.1.

P.sub.4 . . . The contents of the register X set all during the step P.sub.2 are returned to the accumulator ACC through exchange between the both.

P.sub.5 . . . The memory as specified by P.sub.1 is loaded with the contents of ACC.

P.sub.6 . . . The contents of the register X are transmitted into ACC through the exchange process.

P.sub.7 . . . The digit address counter is decremented. By defining the final digit value as "n.sub.2 " the file selected at the step n.sub.2 is shifted as a whole shifted.

P.sub.8 . . . The program address is set at the step P.sub.2 and the steps P.sub.2 -P.sub.7 are repeatedly executed until BL=n.sub.2.

The foregoing is the description of the respective major processing events in the CPU architecture.

By reference to FIG. 6 an example of the display operation implementing the present invention will now be described in detail. For example, if the displaying of a character "I" is desired, the display panel for each digit being a 7.times.5 dot matrix is divided into an upper half and a lower half and encoded information is defined as "11F1144744" in the descending order. This is accomplished by sending selected ones of the segment signals s1-s126 and selected ones of the opposite electrode signals h1-h7 to dot positions necessary for the displaying of the character "I". As indicated in FIG. 5(b), each digit 0, 1, 2, . . . 9, A, B, . . . F of the encoded information consists of their unique combination of 4 bits. The enabling waveform signals and disabling waveform signals are provided when the respective bits have "1" and "0", respectively.

The display data storage section DRM as shown in FIG. 7 is to temporarily store those display encoded data. The respective segments (1)-(21) store independently the encoded information characteristic of characters to be displayed. In the illustrated example, the segment (1) stores the encoded information "11F1144744" associated with the character "I".

The display data storage section DRM has a 21 digit capacity. The display regions 1-21 of the display data storage DRM correspond to the respective display digits of the display panel DSP and constitute the first storage means of FIG. 1. The information of multiple words introduced via the keyboard K is stored within the external memory MU.sub.1 and is shifted sequentially through the display regions 1, 2, 3, 4 . . . . The display data in the display regions 1-21 are visually displayed on the display panel DSP.

FIG. 7 is a typical information display state according to one embodiment of the present invention. For example, if it is desired to display information "MAY I ASK YOU TO POST THIS LETTER?", this sentence is displayed word by word on the 21-digit display panel. First of all, information "MAY I ASK YOU TO POST" is displayed for a given interval of time as depicted in FIG. 8(1). The display panel is then left-shifted by the number of characters to be next displayed, i.e., 5 digits so that the lowest (last) 5 digit positions of the display panel DSP are blank as shown in FIG. 8(2). Upon the completion of the shift operation "THIS" is inserted into the blank digit positions as in FIG. 8(3). Similarly, the display panel is left-shifted by the number of the next succeeding character "LETTER" so that the lowest (last) 7 digits are blank. "LETTER" is displayed on the blank digit positions after the shift operation. In order to display "?" behind "LETTER", the display panel is left-shifted by two characters to locate "?" thereat.

FIG. 9 is an illustration of operation according to the illustrated embodiment of the present invention by which information is unloaded from the external memory to the display data storage. FIG. 10 is a flow chart of explanation of a specific display control operation according to the illustrated embodiment of the present invention. FIG. 11 is a flow chart showing a subroutine for limited time display in FIG. 10. FIG. 12 is a flow chart of a subroutine for blank decision steps in FIG. 10.

The illustrated embodiment of the present invention operates in the following manner as is clear in FIGS. 1 through 12. The display data storage DRM contains the information "MAY I ASK YOU TO POST" as indicated in FIG. 9(1), while the external memory MU.sub.1 contains "THIS LETTER?" The counter CO in a particular region of the RAM of the CPU scheme of FIG. 4A is first reset. While the information in the external memory MU.sub.1 is shifted into the external memory MU.sub.2, the counter CO counts the number of such shifts and in other words the number of characters in the word being shifted from the external memory MU.sub.1 to the other external memory MU.sub.2. After the counter CO is reset, the contents of the external memory MU.sub.1 are shifted to the left by a character and at the same time the contents of the display data storage DRM are left-shifted by a single character. It is decided whether the most significant bit of the external memory MU.sub.1 contains a blank code indicative of the boundaries of words. If the leading character from the external memory MU.sub.1 is blank, then the blank code is sent to the display control circuit DRM. The leading character "T" of the next information "THIS" to be displayed is sent to the external memory MU.sub.2. The counter CO is incremented.

The contents of the external memory MU.sub.1 and the display data storage DRM are shifted to the left by a character. The following step is a decision as to whether the leading character of the external memory MU.sub.1 is blank. If not, the next character "H" is transferred into the external memory MU.sub.2 and the counter CO is incremented. This procedure is repeated to place the next information into the external memory MU.sub.2 in succession. Simultaneously, the contents of the display data storage DRM are left-shifted by the number of the characters in "THIS" (i.e., 40) plus a space (a total of 5 characters). When "THIS" is fetched, the most significant bit of the external memory MU.sub.1 becomes blank. If the CPU senses this blank position, then the contents of the external memory MU.sub.2 are shifted word by word to the display data storage DRM. Each time a character is transferred, the counter CO is decremented until its count reduces to "0". When the count of the counter CO reaches "0", the contents of the display data storage DRM are displayed on the display panel DSP for a limited period of time.

It is noted that the respective steps in FIG. 10 may be achieved by respective ones of the above defined processing list. For example, "CO reset" and "blank DRM" are achieved by processing list (II), "MU2.fwdarw.DRM" and "MU1.fwdarw.MU2" by type (4) of list (III), "CO=0?" by list (X), "CO-1.fwdarw.CO" and "CO+1.fwdarw.CO", by list (V) or (VI), "MU1, DRM shift" and "MU2 shift" by list (XXII).

The limited time display is performed pursuant to the subroutine of FIG. 11. A value N indicative of the limited interval of time is introduced into a particular region of the CPU scheme. The display control signal DIS is supplied to the segment decoder SED of the display control circuit DSC. Furthermore, the contents of the storage region X of the RAM are decremented until they reduce to "0". If the contents of the storage region X are "0", then the display control signal DIS is interrupted to discontinue display operation. In the subroutine of FIG. 11, the steps "N.fwdarw.X", "X-1.fwdarw.X" and "X=0?" are performed by processing lists (II), (V) and (X), respectively.

The blank decision step may be achieved by the subroutine of FIG. 12. In the given example, this is accomplished by deciding if the BM and BL addresses 02 and 12 of the display data storage DRM contain "0". These regions contain data corresponding to the longitudinal, center 7 dots of the most significant digit position of the display panel DSP when they are next shifted. Any character defined by 5.times.7 dots is displayed by energizing any of the 7 dots except for special symbols. Based upon this fact, any blank digit position can be determined by deciding if the longitudinal, center 7 dots in the 5.times.7 dot matrix are in a disabled state.

FIG. 13 is an illustration of operation by which the information in the external memory is transferred into the display data storage according to another embodiment of the present invention and FIG. 14 is a flow chart showing a particular operation according to the second embodiment of the present invention.

The following will set forth the second embodiment of the present invention by reference to FIGS. 1 through 7, FIG. 9 and FIGS. 11 through 14. The second embodiment is adapted such that, when the blank digit position is about to display the next succeeding word, that word is displayed character by character as illustrated in FIG. 13.

Operation of the second embodiment is substantially similar to that in FIG. 10 except for the following aspects. The contents of the external memory MU.sub.1 containing the next succeeding word to be displayed are fetched therefrom character to character and loaded into the external memory MU.sub.2. The contents of the display data storage DRM are correspondingly left-shifted by the number of those characters. If the blank code enters the most significant bit of the external memory MU.sub.1, the shift operation is interrupted on the display data storage DRM and "T" at the most significant bit of the external memory MU.sub.2 is shifted to the fourth least significant bit of the display data storage DRM. Upon the passage of the limited period of time the counter CO is decremented. The next succeeding character "H" is transferred from the external memory MU.sub.2 to the display data storage DRM. The above procedure is repeated until the count of the counter CO reaches "0". The result is that the lowest five digit positions of the display panel DSP are blank and only "T" of the next word "THIS" is displayed, followed by a succession of "H", "I" and "S". Consequently, the contents of display are emphasized by displaying the next word sequentially from character to character.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.