Knock Detecting Method

The present invention relates to a knock detecting method for detecting the presence or absence of knock in internal combustion engines (hereinafter referred to as engines).

In the past, many different types of knock detecting methods have been proposed in which the presence of knock in an engine is determined by sensing engine vibration sound, mechanical vibration accelerations or vibrations due to cylinder combustion pressures and by determining the presence of knock in accordance with the resulting output signal. However, none of these methods has been considered to be relatively free from errors due to aging, etc., and capable of accurately detecting the presence of engine knock.

It is the object of the present invention to provide an improved knock detecting method and apparatus which is capable of accurately determining the presence of engine knock without being affected by aging, noise and the like.

Thus, the method of this invention and apparatus therefore has among its advantages the fact that by detecting the vibrations induced by combustion phenomena of an engine, extracting from the resulting detection signal the output generated in a predetermined time interval at around the top dead center, storing such extracted output a predetermined number of times, computing the average value of the stored output values, determining that there exists knocking when the proportion of those extracted outputs whose ratio to the said average value is greater than a predetermined value is in excess of a predetermined value and then generating an output, it is possible to accurately detect the presence of knock statistically and practically without being affected by engine speed and load, aging, noise and the like.

Another advantage is that by detecting the combustion pressure vibrations of each cylinder in a multi-cylinder engine and by selecting the frequency outputs of over several kHz from the combustion pressure vibration outputs of each cylinder to detect the knock induced vibrations, it is possible to detect the presence of knock in each of the engine cylinders.

FIG. 1 is a block diagram showing an embodiment of this invention.

FIGS. 2 and 3 are front views showing respectively the crank angle measuring senscylinder discrimination sensor 3 in the apparatus shown in FIG. 1.

FIG. 4 shows a plurality of waveforms which are useful for explaining the operation of the apparatus shown in FIG. 1.

FIG. 5 is a circuit diagram showing an embodiment of the first waveform shaping circuit 5.

FIG. 6 is a circuit diagram showing an embodiment of the timing pulse generating circuit 7.

FIG. 7 is a circuit diagram showing an embodiment of the peak hold circuit 8.

FIG. 8 is a circuit diagram showing an embodiment of the frequency rate computing circuit 10.

FIG. 9 is a flowchart for the microcomputer 240 in the circuit shown in FIG. 8.

FIG. 10 is a circuit diagram showing an embodiment of the indication circuit 12 in the apparatus shown in FIG. 1.

FIG. 11 is a circuit diagram showing an embodiment of an integrator circuit 8a used in place of the peak hold circuit 8 in the apparatus shown in FIG. 1.

Referring now to FIG. 1,, an embodiment is illustrated which is applied to an in-line four-cylinder engine to detect the vibrations due to the internal pressures of an engine. In the Figure, numerals 1a to 1d designate combustion pressure sensors each comprising a piezoelectric element which is in the form of a spark plug washer, and each of the sensors is mounted, along with one of the spark plugs, in the engine, that is, the sensor 1a with the No. 1 cylinder spark plug, the sensor 1b with the No. 2 cylinder spark plug, the sensor 1c with the No. 3 cylinder spark plug, and the sensor 1d with the No. 4 cylinder spark plug.

Numeral 2 designates a crank angle measuring sensor which is constructed as shown in FIG. 2. In the Figure, numeral 2a designates an iron disk mounted on the crankshaft and having projections at six positions a.sub.1 to a.sub.6 thereon such that the position a.sub.1 corresponds to a position of 10 degrees after the top dead center of the No. 1 and 4 cylinders, a.sub.2 to a position of 30 degrees after the top dead center of the No. 1 and 4 cylinders, a.sub.3 to a position of 10 degrees after the top dead center of the No. 3 and 2 cylinders, a.sub.4 to a position of 30 degrees after the top dead center of the No. 3 and 2 cylinders, a.sub.5 to a position of 110 degrees after the top dead center of the No. 1 and 4 cylinders and a.sub.6 to a position of 110 degrees after the top dead center of the No. 3 and 2 cylinders. Numeral 2b designates an electromagnetic pickup of a known type which generates a signal when it is opposite to one of the projections on the disk 2a.

Numeral 3 designates a cylinder discrimination sensor which is constructed as shown in FIG. 3 and the sensor 3 is incorporated in the ignition distributor. In the Figure, numeral 3a designates an iron disk formed with a projection at a position thereon, and 3b an electromagnetic pickup of the same type as the pickup 2b shown in FIG. 2 which generates a signal when it is positioned opposite to the projection on the disk 3a. The position of the projection corresponds to about 20 degrees before the top dead center of the No. 1 cylinder. Numerals 4a to 4d designate amplifiers of the same circuit construction each thereof comprising a buffer and an amplifier, and they will not be described in detail since they are well known in the art. Numeral 5 designates a first waveform reshaping circuit for reshaping the output signal of the pickup 2b. Referring to FIG. 4, (A) shows the output signals of the electromagnetic pickup 2b, (B) the output signal of the electromagnetic pickup 3b, and (C) the output signals of the first waveform reshaping circuit 5.

FIG. 5 shows the internal circuitry of the first waveform reshaping circuit 5. In the Figure, numeral 51 designates an input terminal, and a resistor 52 has its one end connected to the input terminal 51 and its other end connected to a resistor 53, the anode of a diode 54 and the cathode of a diode 55 in common. The other end of the resistor 53 is connected to the inverting input terminal of a comparator 59 comprising the Motorola IC MC3302P, and the anode of the diode 55 is grounded. One end of a resistor 56 is connected to the cathode of the diode 54. A resistor 57 has its one end connected to the cathode of the diode 54 and its other end connected to one end of a resistor 58 whose other end is grounded. The junction between the resistors 57 and 58 is connected to the noninverting input terminal of the comparator 59. The comparator 59 has an open-collector output and consequently a resistor 60 is connected between its output and a power supply V.sub.C. The resistance values are selected such that the impedance seen looking into the resistors from the noninverting input terminal of the comparator 59 becomes equal to the impedance seen looking into the resistors from the comparator inverting input terminal. The non-inverting input terminal of the comparator is at about 1/3 V.sub.C. As a result, if the electromagnetic pickup 2b is connected to the input terminal 51, a voltage of about 1/3 V.sub.C will be applied to the input terminal of the comparator 59. The diode 55 is provided so that a negative voltage of less than -0.5 V is not applied to the inverting input terminal, and the diode 54 prevents the application of a positive voltage of over +(V.sub.C +0.5 V) to the inverting input terminal. In operation, when the disk 2a is rotated, the waveform shown in (A) of FIG. 4 is generated each time the projections on the disk 2a successively pass the electromagnetic pickup 2b. When this occurs, the comparator 59 generates at its output the reshaped pulses shown in (C) of FIG. 4.

A second waveform reshaping circuit 6 is the same in circuit construction with the first waveform reshaping circuit 5 and will not be described. In operation, when the disk 3a is rotated so that the waveform shown in (B) of FIG. 4 is generated each time its projection passes the electromagnetic pickup 3b, the reshaped pulse in (D) of FIG. 4 is correspondingly generated at the output of the second waveform reshaping circuit 6.

Numeral 7 designates a timing pulse generating circuit which is responsive to the output signals of the cylinder discriminator sensor 3 and the crank angle measuring sensor 2 to generate signals applied to the control inputs of analog switches 13a to 13d, a signal applied to the control input of a peak hold circuit 8 and a trigger signal applied to an A-D converter circuit 9 for A-D conversion starting purposes. Its internal circuitry is shown in FIG. 6. In the Figure, an input terminal 131 is connected to the output of the first waveform reshaping circuit 5, and an input terminal 132 is connected to the output of the second waveform reshaping circuit 6. An input terminal 133 is connected to receive the pulses C.sub.1 (200 kHz) from a clock generating circuit 11. The input terminal 132 is also connected to one terminal of an OR gate 135 by way of an inverter 134. The other end of the OR gate 135 is connected to the "3" output terminal of a divider/counter 136. The output of the OR gate 135 is connected to the reset terminal R of the divider/counter 136. The clock input CL of the divider/counter 136 is connected to the input terminal 131. The divider/counter 136 also has its "0" output terminal connected to the clock input of a divider/counter 137 and its "1" connected to the reset terminal of a divider/counter 142. Each of the dividers/counters 136, 137 and 142 is comprised of the RCA IC CD4017. The divider/counter 137 has its "0" output terminal connected to the input of a buffer 138, its "1" output connected to the input of a buffer 139, its "2" output terminal connected to the input of a buffer 140 and its "3" output terminal connected to the input of a buffer 141. Each of the buffers 138, 139, 140 and 141 is comprised of the RCA IC CD4050. The divider/counter 142 has its clock input CL connected to the input terminal 133 and its clock enable terminal connected to its "9" output terminal. The divider/counter 142 has its "1" output terminal connected to the input of an inverter 143. The buffers 138, 139, 140 and 141 are respectively connected to output terminals 145, 146, 147 and 148 of the timing pulse generating circuit 7. The divider/counter 136 has its "1" output terminal connected to an output terminal 149 through a buffer 144, and the inverter 143 is connected to an output terminal 150.

With the construction described above, the operation of the timing pulse generating circuit 7 is as follows. The pulse signal shown in (D) of FIG. 4 is applied to the input terminal 132. As a result, the inverted pulse of the pulse (D) is applied to the reset terminal R of the divider/counter 136 so that the divider/counter 136 is reset when the pulse (D) is at "0". When this occurs, the pulses shown in (C) of FIG. 4 are applied to the clock input of the divider/counter 136. Thus, in response to the positive-going transition of the third pulse a "1" is applied to the OR gate 135 so that the divider/counter 136 is reset and its "0" output terminal has the waveform shown in (E) of FIG. 4. Also the divider/counter 137 is reset when the pulse (D) is at "0" so that the waveform (E) is applied to the clock input of the divider/counter 137 which in turn generates the waveforms which are the same as those shown in (F) to (I) of FIG. 4 at its "0", "1", "2" and "3" output terminals, respectively. As a result, the outputs of the buffers 138, 139, 140 and 141 respectively become the waveforms shown in (F), (G), (H) and (I) of FIG. 4.

On the other hand, the waveform shown in (J) of FIG. 4 is generated at the "1" output of the divider/counter 136. As a result, the divider/counter 142 is reset when the pulse of the waveform (J) goes to "1" and it starts counting the clocks C.sub.1 of 200 kHz when the pulse (J) goes from "1" to "0". When the ninth pulse is counted, a "1" is applied to the clock enable terminal so that the count is maintained until the divider/counter 142 is reset. As a result, when the pulse of the waveform (J) of FIG. 4 goes from "1" to "0", a narrow pulse of 5 .mu.s shown in (K) of FIG. 4 is generated from the "1" output. This pulse is inverted by the inverter 143 and the resulting waveform shown in (L) of FIG. 4 is generated at the output terminal 150 of the timing pulse generating circuit 7. The output of the buffer 144 becomes the waveform shown in (J) of FIG. 4.

The analog switches 13a to 13d are each so designed that it is turned on when its control input goes to "1" and it is turned off when the control input goes to "0". The output signals (F), (I), (G) and (H) of the timing pulse generating circuit 7 are respectively applied to the control input of the analog switches 13a to 13d, respectively. The analog switches 13a to 13d deliver their outputs to a common output line. The analog switch 13a is turned on when the signal (F) of FIG. 4 goes to "1" and it is turned off when the signal (F) goes to "0". The analog switch 13c is turned on when the signal (G) goes to "1" and it is turned off when the signal goes to "0". The analog switch 13d is turned on when the signal (H) goes to "1" and it is turned off when the signal (H) goes to "0". The analog switch 13b is turned on when the signal (I) goes to "1" and it is turned off when the signal goes to "0". As a result, the outputs of the analog switches 13a to 13d respectively correspond to the combustion pressure waveforms generated from the No. 1 cylinder during the interval between 110 degrees after TDC of the No. 2 cylinder and 110 degrees after TDC of the No. 1 cylinder, the combustion pressure waveform generated from the No. 3 cylinder during the interval between 110 degrees after TDC of the No. 1 cylinder and 110 degrees after TDC of the No. 3 cylinder, the combustion pressure waveform generated from the No. 4 cylinder during the interval between 110 degrees after TDC of the No. 3 cylinder and 110 degrees after TDC of the No. 4 cylinder and the combustion pressure waveform generated from the No. 2 cylinder during the interval between 110 degrees after TDC of the No. 4 cylinder and 110 degrees after TDC of the No. 2 cylinder. The reason for selecting the points of 110.degree. after TDC of the respective cylinders as the switching points of the analog switches 13a to 13d is that while the switching at these switching points tends to generate and deliver high frequency noise to the following high-pass filter 14 and while the required waveforms will in fact be produced during the interval between 10.degree. and 30.degree. after TDC of the respective cylinders thus making it possible to select any points outside this interval as the required switching points, it is preferred to select points which are as remote from the interval as possible, thus resulting in the selection of the points of 110.degree. after TDC of the respective cylinders.

The high-pass filter 14 is a high-pass active filter of over 5 kHz and it comprises the NF Circuit Block Design DV4BH with a capacitor being connected to each of its input and output.

Numeral 15 designates an AC amplifier having an amplification factor of about 100 times and it will not be described in detail since it is well known.

The output waveform of the AC amplifier 15 is shown in (N) of FIG. 4. In (N) of FIG. 4, t.sub.1 represents the waveform produced on the power stroke of the No. 1 cylinder, t.sub.2 the noise produced by the transition between the analog switches 13a and 13c, t.sub.4 the ignition noise from the No. 3 cylinder, t.sub.5 the waveform produced on the power stroke of the No. 3 cylinder, t.sub.6 the noise produced by the transition between the analog switches 13c and 13d, t.sub.7 the ignition noise from the No. 4 cylinder, t.sub.8 the waveform produced on the power stroke of the No. 4 cylinder, t.sub.9 the noise produced by the transition between the analog switches 13d and 13b, t.sub.10 the ignition noise of the No. 2 cylinder, t.sub.11 the waveform produced on the power stroke of the No. 2 cylinder, and t.sub.12 the noise produced upon the transition between the analog switches 13b and 13a. The noise waveforms t.sub.2, t.sub.6, t.sub.9 and t.sub.12 include those produced by the opening of the intake and exhaust valves of the respective cylinders.

Numeral 16 designates an absolute value circuit having the circuit construction stated on page 163 of the "Operational Amplifier Handbook", published in 1976 by the Electronics Digest Ltd., but using different circuit constants and thus it will not be described in detail. In operation, the absolute value circuit 16 converts its negative input waveform to a positive waveform and it generates the waveform shown in (O) of FIG. 4.

Numeral 8 designates a peak hold circuit and its internal circuitry is shown in FIG. 7. An input terminal 210 receives the signal (J) from the timing pulse generating circuit 7, and the input terminal 210 is connected to the input 1B of a monostable multivibrator 212 comprising the Texas Instruments IC SN74123. The other input 1A is grounded. A capacitor 213 is connected beween the terminals 14' and 15' of the monostable multivibrator 212 and a resistor 214 is connected between the terminal 15' and the power supply V.sub.C (=5 V). Thus, a signal having a pulse width of about 100 .mu.s as determined by the capacitor 213 and the resistor 214 is generated at the output Q as shown in (P) of FIG. 4 in response to the positive-going transition of the signal (J) from the timing pulse generating circuit 7. The output Q is connected to the control terminal of an analog switch 215. An input terminal 211 is connected to the absolute value circuit 16 and the input terminal 211 is also connected to the anode of a diode 216. The cathode of the diode 216 is connected to the noninverting input of a buffer amplifier 220 through a resistor 217. The analog switch 215 has its input connected to the noninverting input of the buffer amplifier 220 through a resistor 219 and its output grounded. A capacitor 218 is connected between the noninverting input of the buffer amplifier 220 and the ground. The inverting input of the buffer amplifier 220 is connected to its output. The output of the buffer amplifier 220 is also connected to an output terminal 221 of the peak hold circuit 8.

With the above-described construction, the operation of the peak hold circuit 8 is as follows. When the signal shown in (J) of FIG. 4 arrives at the input terminal 210 from the timing pulse generating circuit 7, the pulse shown in (P) of FIG. 4 is generated at the output of the monostable multivibrator 212. The analog switch 215 is closed for the time width of the pulse (P) so that the charge on the capacitor 218 is discharged through the resistor 219 and the voltage on the capacitor 218 is reset to zero V. Then, the output (O) of the absolute value circuit 16 is charged into the capacitor 218 through the diode 216. As a result, the voltage on the capacitor 218 represents the peak value for the time interval between its successive resetting operations. The voltage on the capacitor 218 is applied to the input of the following high input impedance buffer amplifier 220. The waveform of its output becomes as shown in (Q) of FIG. 4. The circuit 8 may be replaced with the peak value rectifier circuit shown on page 135 of the "Latest Practical Application Techniques of OP AMPs", published in February 1975 by the Seibundo Shinkosha, in Japan.

Numeral 9 designates an A-D converter comprising the Micronetwork IC MN5120 8-bit A-D converter. When the output signal (L) of the timing pulse generating circuit 7 is applied to the start-conversion terminal of the A-D converter 9, the A-D converter 9 starts its A-D conversion and the pulse shown in (M) of FIG. 4 is generated at its terminal EOC upon completion of the A-D conversion. The length of this conversion time is about 10 .mu.s. In this case, since the signal in (L) of FIG. 4 is the waveform generated at 30 degrees after TDC of each cylinder and since the voltage of the peak hold circuit 8 up to 10 .mu.s from this waveform is subjected to A-D conversion, the resulting 8-bit binary code value from the A-D converter 9 represents the peak value of the signal waveform generated during the interval of 10 to 30 degrees after TDC of each of the cylinders. The EOC (end of conversion) output and the 8-bit binary code output of the A-D converter 9 are respectively coupled to the interrupt terminal and the I/O terminals of a frequency rate computing circuit 10.

The frequency rate computing circuit 10 will now be described. FIG. 8 shows the internal circuitry of the frequency rate computing circuit 10. An input terminal 230 is connected to the output terminal EOC of the A-D converter 9. An input terminal 231 is connected to receive the output (F) of the timing pulse generating circuit 7, and input terminals 232, 233, 234, 235, 236, 237, 238 and 239 are connected to receive the 8-bit binary code output of the A-D converter 9 in the order of their significance with the input terminal 232 receiving the least significant bit. Numeral 240 designates a microcomputer comprising the Toshiba TLCS-12. Although the circuit construction and operation of the microcomputer 240 are well known and will not be described, it utilizes the internal clock frequency (2 MHz) such that when it is energized, it is initialized and brought into operation starting at the designated address of its ROM. The microcomputer 240 includes eight interrupt signal lines one of which is connected to the input terminal 230. Terminals 241, 242 and 243 are respectively connected to signal lines SE.sub.0, SE.sub.1 and SE.sub.2 which are three of the sixteen device address select signal lines of an input/output control unit (hereinafter referred to as a DCU) which is incorporated in the microcomputer 240, thereby connecting the devices to the bus lines. The terminals 241, 242 and 243 are respectively connected to one input terminal of NAND gates 246 and 247 and an AND gate 249, respectively.

A terminal 244 is connected to the input/output command line of the DCU so that data are transferred from the devices to the processor (hereinafter referred to as a CPU) in the microprocessor 240 when the terminal 244 goes to "1" and data are transferred to the devices from the CPU when the terminal 244 goes to "0". The terminal 244 is connected to the other input terminal of the NAND gates 246 and 247, respectively, and also to the other input terminal of the AND gate 249 through an inverter 248.

Numeral 245 designates a 12-bit bus line group comprising twelve lines BUS.sub.0 to BUS.sub.11. The BUS.sub.11 is the least significant bit line and the BUS.sub.0 is the most significant bit line. Numeral 250 designates a buffer circuit comprising a noninverting buffer circuit with 3-state output and the Toshiba TC5012P is used for this circuit. Its input I.sub.1 is connected to the input terminal 231 of the frequency rate computing circuit 10, and disable terminals D.sub.4 and D.sub.2 are both connected to the output of the NAND gate 246. Its output O.sub.1 is connected to the bus line BUS.sub.0. Numeral 251 designates a circuit which is identical with the buffer circuit 250 and whose inputs I.sub.1, I.sub.2, I.sub.3, I.sub.4, I.sub.5 and I.sub.6 are respectively connected to the input terminals 232, 233, 234, 235, 236 and 237 of the frequency rate computing circuit 10. Its disable terminals D.sub.4 and D.sub.2 are both connected to the output of the NAND gate 247. Its ouputs O.sub.1, O.sub.2, O.sub.3, O.sub.4, O.sub.5 and O.sub.6 are respectively connected to the bus lines BUS.sub.11, BUS.sub.10, BUS.sub.9, BUS.sub.8, BUS.sub.7 and BUS.sub.6.

Numeral 252 designates a circuit comprising the same TC5012P as the buffer circuit 250. Its inputs I.sub.1 and I.sub.2 are respectively connected to the input terminals 238 and 239 of the frequency rate computing circuit 10. The remaining inputs I.sub.3, I.sub.4, I.sub.5 and I.sub.6 are grounded in common. Its disable terminals D.sub.4 and D.sub.2 are connected in common to the output of the NAND gate 247. Its outputs O.sub.1, O.sub.2, O.sub.3, O.sub.4, O.sub.5 and O.sub.6 are respectively connected to the bus lines BUS.sub.5, BUS.sub.4, BUS.sub.3, BUS.sub.2, BUS.sub.1 and BUS.sub.0. Numeral 253 designates a memory comprising the RCA IC CD40174 having its clock input CL connected to the output of the AND gate 249, its inputs D.sub.1, D.sub.2, D.sub.3, D.sub.4, D.sub.5 and D.sub.6 respectively connected to the bus lines BUS.sub.0 to BUS.sub.5 and its reset terminal connected to the power supply V.sub.C (=5 V). The outputs of the memory 253 are the output terminals 254, 255, 256, 257, 258 and 259 of the frequency rate computing circuit 10.

With the construction described above, the operation of the frequency rate computing circuit 10 will now be described with reference to the flowchart shown in FIG. 9. When the key switch (not shown) is turned on, the circuit is energized and it starts operating. A step 1 clears all the memories in the microcomputer 240 except the ROM. A step 2 clears a location U.sub.0 of a memory area U in the RAM, and a step 3 clears a location U.sub.1 to set its content h to 0. A step 4 clears a location U.sub.2 to set its content i to 0, and a step 5 clears a location U.sub.3 to set its content j to 0. A step 6 sets a master mask and executes a swap command to permit the application of an interrupt request signal. Then, when the engine is started and comes into operation, the A-D converter 9 initiates its A-D conversion in response to the pulse shown in (L) of FIG. 4 and applied from the timing pulse generating circuit 7. When this conversion is completed, the EOC pulse shown in (M) of FIG. 4 is generated so that the microcomputer 240 is interrupted through the input terminal 230 of the frequency rate computing circuit 10 causing the microcomputer 240 to start computing. This is done by a step 7. If there is no EOC pulse, the arrival of it is waited upon. When the EOC pulse is applied, the control is transferred to a step 8. The step 8 is such that a device address select signal SE.sub.0 is generated at the terminal 241 after the input/output command signal has been changed to "1" by the device control unit (DCU) in the microcomputer 240. When both the input/output command signal and the device address select signal go to "1", the output of the NAND gate 246 goes to "0" so that the input and the output of the buffer circuit 250 are interconnected and the data appearing on the bus lines is loaded into the register of the processor in the microcomputer 240. A step 9 determines whether only the most significant bit of the 12-bit data stored in the register of the processor is "1" or "0". If it is, or "yes", the control is transferrd to a step 10, and if it is not or "no", the control is transferred to a step 11. The step 10 sets the location U.sub.0 of the memory U to 1 and then the control is transferred to the step 11. The step 11 determines whether the content of the memory location U.sub.0 is 1, so that if it is, or "yes", the control is transferred to a step 12, whereas if it is not, or "no", the control is returned to the step 7. Once the memory location U.sub.0 is set to 1, the control will be passed unconditionally up to the step 12 and the steps 8, 9, 10 and 11 are such that the data are successively stored in the memory starting with the data of the No. 1 cylinder. The step 12 is the process including the step 8 and 9 and it determines by the same processes as the steps 8 and 9 whether the data just entered is the data of the No. 1 cylinder. If it is, the control is transferred to a step 13, and if it is not, the control is transferred to a step 14.

The step 13 increases the content h of the memory location U.sub.1 by 1 and stores it again in the memory location U.sub.1. Then, the location U.sub.2 is cleared to set its content i to 0. As a result, initially 0+1 or 1 is stored. In the like manner, the step 14 increases the content i of the memory location U.sub.2 by 1 and then stores it again in the location U.sub.2. Thus, since initially i=0, 0+1 or 1 is stored. A step 15 multiplies the content i of the memory location U.sub.2 by a preset frequency N.sub.R (=100) preliminarily programmed into the ROM and stores the result in the memory location U.sub.3.

A step 16 adds the content h of the location U.sub.1 to the content j of the location U.sub.3 and stores the resulting sum in the location U.sub.4. A step 17 is such that the data introduced from the inputs 232 to 239 of the frequency rate computing circuit 10 is stored in an address or location X.sub.k of a memory area X designated by the content of the location U.sub.4. A step 18 determines whether the content k of the location U.sub.4 is greater than 4.times.N.sub.R. If it is not, the control is returned to the step 7. If it is, the control is transferred to a step 19. By the processing of the steps 7 to 18, assuming that the preset frequency N.sub.R is 100, of the data subjected to the A-D convertion the data of the No. 1 cylinder are stored in the locations X.sub.1 to X.sub.100, the data of the No. 3 cylinder are stored in the locations X.sub.101 to X.sub.200, the data of the No. 4 cylinder are stored in the locations X.sub.201 to X.sub.300 and the data of the No. 2 cylinder are stored in the locations X.sub.301 to X.sub.400, each in regular succession.

The step 19 resets the master mask and then executes the swap command to inhibit interruptions. A step 20 clears a location U.sub.5 to set its content m to 0, and a step 21 clears a location U.sub.11 to set its content t to 0. A step 22 multiplies the content m of the location U.sub.5 by the preset frequency N.sub.R preprogrammed into the ROM and stores the result in a location U.sub.6. A step 23 sets the content n of a location U.sub.7 to 1. A step 24 sets the content S of a location Y.sub.0 of a memory area Y to 0. A step 24 adds the content n of the location U.sub.7 to the content l of the location U.sub.6 and stores the sum in a location U.sub.8. Thus, since initially m=0 and n=1, there results p=1. A step 26 is such that the content D.sub.P in a location X.sub.p of the memory area X which was designated by the content p of the location U.sub.8 is added to the content S of the location Y.sub.0 in the memory area Y and the result is stored in the location Y.sub.0. A step 27 increases the content n of the location U.sub.7 by 1 and stores the result in the location U.sub.7. A step 28 determines whether the content n of the location U.sub.7 is greater than the preset frequency N.sub.R so that if it is, the control is transferred to a step 29. If it is not, the control is returned to the step 25. As a result, if now m=0 and N.sub.R =100, the processing of the steps 23 to 28 has entered the data D.sub.1 +D.sub.2 + . . . +D.sub.100 of the No. 1 cylinder as the content S of the location Y.sub.0.

A step 29 divides the content S of the location Y.sub.0 by the preset frequency N.sub.R and the resulting quotient value D.sub.m is stored in a location Y.sub.1. The value D.sub.m represents the average value. A step 30 sets the contents q of a location U.sub.9 to 1. A step 31 clears a location U.sub.10 and sets its content r to 0. A step 32 divides the data D.sub.q of a location X.sub.q designated by the content q of a location U.sub.9 by the content D.sub.m of the location Y.sub.1 and stores the resulting quotient value E.sub.q in a location Y.sub.2.

A step 33 determines whether the content E.sub.q of the location Y.sub.2 is smaller than a preset value E.sub.R preprogrammed into the ROM. If it is, the control is transferred to a step 36. If it is not, the control is transferred to a step 34. The step 34 increases the content r of the location U.sub.10 by 1 and stores it in the location U.sub.10. Thus, initially r=0. The step 35 increases the content t of the location U.sub.11 by 1 and stores it in the location U.sub.11. The steps 34 and 35 differ from each other in that while the location U.sub.10 is cleared for each of the cylinders, the location U.sub.11 is cleared after the completion of the processing on all the cylinders.

A step 36 increases the content q of the location U.sub.9 by 1 and stores it again in the location U.sub.9. Thus, the values of the content q are such that initially it is set to q=1 and then increased to 2, 3, . . . A step 37 determines whether the content q of the location U.sub.9 is greater than the preset frequency N.sub.R. If it is, the control is transferred to a step 38. If it is not, the control is returned to the step 32. Thus, by the processing of the steps 30 to 37, the data D.sub.1, D.sub.2, . . . , D.sub.nR stored in the locations X.sub.1, X.sub.2, . . . , X.sub.nR are each divided by the average value D.sub.m so that the number of those of the resulting quotients E.sub.1, E.sub.2, . . . , E.sub.nR which are greater than the preset value E.sub.R is stored as the content r of the location U.sub.10 .

The step 38 is such that the content r of the location U.sub.10 is stored in a register R.sub.2 which is one of the eight general registers in the processor and then the preset frequency N.sub.R is read from the ROM thus dividing the content r by the frequency N.sub.R. The resulting quotient F is held in the registers R.sub.2 and R.sub.3. A step 39 reads the number 100 from the ROM and multiplies the contents of the registers R.sub.2 and R.sub.3 by 100. The resulting product H represents the frequency rate and it is held in the registers R.sub.2 and R.sub.3. The register R.sub.2 retains the higher significant digit and the register R.sub.3 retains the lower significant digit.

A step 40 determines whether the contents of the registers R.sub.2 and R.sub.3 are greater than a preset value H.sub.R. If it is, the control is transferred to a step 41. If it is not, the control is transferred to a step 42. The step 41 reads out the content m of the location U.sub.5 and sets the mth bit of a location U.sub.12 to "1". The step 42 sets the mth bit of the location U.sub.12 to "0". Since initially m=0, the most significant bit of the location U.sub.12 will be set. A step 43 increases the content m of the location U.sub.5 by 1 and stores it in the location U.sub.5. A step 44 determines whether the content m of the location U.sub.5 is greater than 4. If it is not, the control is returned to the step 22. If it is, the control is transferred to a step 45. Thus, with the preset frequency N.sub.R being 100, the steps 20 to 44 perform the process of obtaining the data D.sub.1, D.sub.2, . . . , D.sub.100 of the No. 1 cylinder, obtaining the average value D.sub.0 of these data, dividing each data by the average value D.sub.0 to obtain their relative magnitudes, and then setting the 0th bit of the location U.sub.12 to "1" if the number of the data having the greater magnitudes than the preset value E.sub.R is greater than the preset value H.sub.R % and setting to "0" if the number of such data is less than the preset value H.sub.R %. Then, similarly the data D.sub.101, D.sub.102, . . . , D.sub.200 of the No. 3 cylinder are obtained, their average value D.sub.1 is obtained, and then the data are each divided by the average value D.sub.1 to determine their relative magnitudes, whereby the first bit of the location U.sub.12 is set to "1" is the number of the data having the greater magnitudes than the E.sub.R is greater than the H.sub.R %, and the first bit is set to "0" if the number of such data is less than the H.sub.R %. In the like manner, the data D.sub.201, D.sub.202, . . . , D.sub.300 of the No. 4 cylinder are obtained, the average value D.sub.2 of these data is obtained and then each of these data is divided by the average value D.sub.2 to determine their relative magnitudes, whereby the second bit of the location U.sub.12 is set to "1" if the number of the data having the greater magnitudes than the E.sub.R is greater than the H.sub.R %, and the second bit is set to "0" if the number of such data is less than the H.sub.R %. Also, the data D.sub.301, D.sub.302, . . . , D.sub.400 of the No. 2 cylinder are obtained, the average value D.sub.3 of these data is obtained and then each of these data is divided by the average value D.sub.3 to determine their relative magnitudes, whereby the third bit of the location U.sub.12 is set to "1" if the number of the data having the greater magnitudes than the E.sub.R is greater than the H.sub.R %, and the third bit is set to "0" if the number of such data is less than the H.sub.R %.

The step 45 performs the operation of multiplication on the number of cylinders and the preset frequency programmed into the ROM and generates the resulting product N.sub.R', and a step 46 divides the content t of the location U.sub.11 by the product value N.sub.R' and generates the resulting quotient F.sub.T. A step 47 reads the number 100 from the ROM and multiplies the quotient value F.sub.T by 100. The resulting product H.sub.T represents the average frequency rate of all the cylinders. A step 48 determines whether the product value H.sub.T is greater than a preset value H.sub.R'. If it is, the control is transferred to a step 49. If it is not, the control is transferred to a step 50. The step 49 sets the fourth bit of the location U.sub.12 to "1", and the step 50 sets the fourth bit of the location U.sub.12 to "0". By the processing of the steps 45 to 50, the average value of the frequency rates of the cylinders (hereinafter referred to as an all-cylinder frequency rate) is obtained so that if the all-cylinder frequency rate is greater than the preset value H.sub.R', the fourth bit of the location U.sub.12 is set to "1", and a fourth position is set to "0" if the all-cylinder frequency rate is less than the preset value H.sub.R'. A step 51 determines whether the content of the location U.sub.12 is greater than 1. If it is, the control is transferred to a step 52. If it is not, the control is transferred to a step 53. The step 52 sets the fifth bit of the location U.sub.12 to "1", and the step 53 sets the fifth bit of the location U.sub.12 to "0".

The processing of the steps 51 to 53 are such that if the frequency rate of at least one cylinder is greater than the preset value, any one of the 0th to third bits of the location U.sub.12 is set to "1", and the fourth bit of the location U.sub.12 is set to "1" if the all-cylinder frequency rate is greater than the preset value. As a result, where the engine is considered in the knocking condition if there exists one or the other of two conditions, that the frequency rate of at least one of the cylinders is greater than the preset value and that the all-cylinder frequency rate is greater than the preset value, this is the case where any one of the bits in the location U.sub.12 is set to "1". Thus, if the content of the location U.sub.12 is greater than 1, any one of the 0th to fifth bits should have been set to "1".

A step 54 delivers the content of the location U.sub.12 to the I/O bus lines. In this case, an input/output command signal is generated from the terminal 244 and the signal goes to "0". Practically simultaneously, a device address select signal SE.sub.2 is generated from the terminal 242 and it goes to "1". Almost simultaneously, the content of the location U.sub.12 is delivered to the I/O bus lines. When the previously mentioned condition is satisfied by the input/output command signal and the device address select signal, the inverter 248 and the AND gate 249 generates a signal which goes from "0" to "1" so that in response to the signal the memory 253 stores the required higher six bits of the data delivered to the I/O bus lines. When this occurs, the microcomputer 240 returns to the step 2 in the flowchart of FIG. 9.

With the flowchart of FIG. 9, in the case of a determination such as the one performed by the step 7 the operation may involve more detailed steps and such steps may also be involved in cases where the control is returned to any previous step. However, these detailed steps are well known in the art and will not be described.

The results of the above-described operation are generated at the outputs of the memory 253 or the output terminals of the frequency rate computing circuit 10, that is, the result of the computation of the No. 1 cylinder is generated at the output terminal 254, the similar result on the No. 3 cylinder at the output terminal 255, the similar result on the No. 4 cylinder at the output terminal 256, the similar result on the No. 2 cylinder at the output terminal 257, the result of the computation on all the cylinders at the output terminal 258, and the result of the final knock discriminating computation at the output terminal 259. The signal at the output terminal 259 is generated as a knock discrimination signal to an indicator circuit 12 and to other devices such as an electronic ignition timing control system.

The indicator circuit 12 is constructed as 261 has its one end connected to the output terminal 254 of the frequency rate computing circuit 10 and its other end connected to the base of a transistor 263. The emitter of the transistor 263 is grounded. A resistor 262 is connected between the base and emitter of the transistor 263 whose collector is connected to the cathode of a light-emitting diode 265 through a resistor 264. The anode of the light-emitting diode 265 is connected to the power supply V.sub.C.

With the construction described above, the operation of the indicator circuit 12 is as follows. When a voltage is applied to the terminal 254, a base current flows to the base of the transistor 263 through the resistor 261 and the transistor 263 is turned on. Thus, the light-emitting diode 265 is turned on. When no voltage is applied to the terminal 254, the transistor 263 is turned off and the light-emitting diode 265 is turned off. Numeral 270 designates an indicator for the No. 3 cylinder, 280 an indicator for the No. 4 cylinder, 290 an indicator for the No. 2 cylinder, 300 an indicator for all the cylinders, and 310 an overall indicator. These indicators operate in the same manner as the indicator 260.

The clock generating circuit 11 will now be described. The clock generating circuit 11 comprises an oscillator with a crystal unit and a counter for dividing the frequency of the oscillator. Its circuit construction and details are well known in the art and will not be described.

The other .+-.15 V power supply for operational amplifiers, power supply V.sub.C =5 V, microcomputer power supply circuit and offset regulating circuit for operational amplifiers are well known in the art and will not be described.

While, in the embodiment described above, the peak hold circuit 8 and the A-D converter 9 are used for detecting the peak value of the waveform generated in the interval of 10 to 30 degrees after TDC, the presence of knock can also be determined by replacing the peak hold circuit 8 with an integrator circuit 8a constructed as shown in FIG. 11 for the purpose of obtaining an integrated value of the waveform produced in the same interval of 10 to 30 degrees after TDC. In FIG. 11, numeral 211' designates a diode for passing only the positive components of the waveform. An integrator is formed by a resistor 212', an amplifier 213', a capacitor 214', an analog switch 215' and a resistor 216'. Numerals 212, 213 and 214 designate an IC forming a monostable multivibrator, a capacitor and a resistor which are the same with those shown in FIG. 7, and they are responsive to the signal (J) from the timing pulse generating circuit 7 to generate the output of about 100 .mu.s shown in (P) of FIG. 4. The analog switch 215' is closed by the pulse (P) of FIG. 4 which is applied to its control input so that the charge on the capacitor 214' is discharged so as to start an integration action. In this case, since the input to the integrator is a positive voltage, its output is a negative voltage.

As a result, this negative voltage is inverted by an inverting amplifier 217' having a gain of 1.0 and the resulting positive voltage is generated. This integration action is started at about 10 degrees after TDC so that after the integration has been completed, at 30 degrees after TDC the voltage is subjected to A-D conversion by the A-D converter 9 at a rate of about 10 .mu.sec and thus the resulting converted value represents an integrated value of the waveform generated during the interval between 10.degree. and 30.degree. after TDC. If the engine is knocking, this integrated value increases with the intensity of the knock. Thus, by processing this integrated value by the frequency rate computing circuit 10 in the same manner as mentioned previously and then indicating the result by the indicator circuit 12, it was possible to obtain practically the same results as obtained previously.

Further, while, in the embodiment described above, the sampling period is the interval between 10.degree. and 30.degree. after TDC, it is possible to effect the desired knock discrimination by selecting a predetermined period of time after each ignition or a predetermined degrees of crankshaft rotation after each ignition as the desired sampling period.

With the construction described above, experiments conducted showed that with the preset values of N.sub.R =100, E.sub.R =2, H.sub.R =9 (%) and H.sub.R '=5 (%), as compared with the knock discrimination effected by the flashing of the light-emitting diodes in the indicators 260, 270, 280 and 290 of the indicator circuit 12 which were provided one for each cylinder and the knock discrimination effected by the all-cylinder indicator 300, the knock discrimination effected by the overall indicator 310 was in excellent conformity with the knock discrimination effected by means of organoleptic or sensory testing based on the operator's ears.

Thus, in the presence of the knock, the ignition timing is controlled in accordance with the knock signal generated at the output terminal 259 of the frequency rate computing circuit 10 (e.g., the ignition timing is retarded when there is the knock), thereby making it possible to control the occurrence of knock to the minimum value. As regards the method of controlling the ignition timing, it is only necessary to arrange so that when knock occurs, the points of the distributor are forcibly moved into a retarded position by a solenoid, the advance by the vacuum advance unit is stopped by an electromagnetic change-over valve or the ignition timing is retarded by a delay circuit, and it should be apparent to those skilled in the art that in the case of engines equipped with any of electronic ignition timing control systems which are now used increasingly recently, it is only necessary to construct the electronic circuitry such that the ignition timing is retarded in response to the occurrence of knock.

Still further, while, in the above-described embodiment, the vibrations induced by the combustion pressures in the respective cylinders are detected, a vibration sensor may be mounted on a portion of the engine such that the mechanical vibration accelerations of the cylinder block are detected and the vibration waveforms are applied to the amplifier circuit 15 of FIG. 1, thus storing in the memory of the frequency rate computing circuit the data corresponding to the vibration waveforms associated with the respective cylinders. Thus, with this vibration sensor, it is possible to accomplish the knock discrimination in the like manner as the embodiment of this invention. Also, it should be apparent that the method of this invention is equally applicable not only to spark ignition engines but also to Diesel engines, etc.