Electronic Timepiece With Electro-Optic Display

This invention relates to an electronic timepiece and more especially to a timepiece with liquid crystal display elements simulating an hour hand and minute hand and, if desired, a second hand.

There has been heretofore a liquid crystal display device in which as the contents to be displayed on the display device are quickly changed by means of an adjusting means, the display of the display device is not capable of responding to the quick changing of the contents to be displayed, so that one display on the display device disappears or represents meaningless contents. Accordingly in an electronic timepiece provided with such a display device, as the contents in the counters for counting time are changed at a high frequency, one time-display on the display device is not capable of responding to the quickly changed contents, and as a result, a correct time display is not made. Consequently it has been a fear that one who adjusts the time has doubts that there may have been some trouble with the display device.

One object of this invention is to provide a new electronic timepiece.

Another object of this invention is to provide an electronic timepiece having a plurality of liquid crystal display elements which are radially arrayed and circuitry operable during normal time display for time-divisionally selecting timing signals representative of units of time and converting the selected signals to pulsed voltages which are applied to the display elements, and operable during time adjustment for stopping the selection of predetermined timing signals and increasing the period during which timing signals corresponding to time units being adjusted are selected so that the pulsed voltages corresponding to the time units being adjusted are applied to the display elements for a longer period of time as compared to the normal time display thereby increasing the effective value of the pulsed voltages so as to improve the contrast between display and non-display portions of the display elements, and even if the time adjustment is quickly made, the time adjusting contents are always displayed by the display elements.

The invention is illustrated in and further explained in connection with the accompanying drawings, in which:

FIGS. 1A, 1B and 1C are a diagramatic block circuit representation of one embodiment of the invention;

FIG. 2 is a plan view of the segment electrode system of a liquid crystal display device used in the embodiment of FIG. 1;

FIG. 3 is a plan view of the common electrode system of the display device the segment electrode system of which is shown in FIG. 2;

FIG. 4 is a diagram illustrating the output conversion circuit and the segment voltage supply circuit in the embodiment of FIG. 1;

FIG. 5 is a diagram illustrating the voltage selector 12 in the embodiment of FIG. 1;

FIG. 6 is a diagram illustrating the common voltage supply circuit in the embodiment of FIG. 1; and

FIG. 7 is a voltage table for illustrating the operation of FIG. 1.

Referring to FIGS. 1A, 1B and 1C block 1 represents a crystal controlled time standard oscillator the output of which is divided down in frequency by a multi-stage frequency divider 2 the reduced frequency output from which is fed to a decimal counter 3 counting a time unit of seconds. A carry output of the decimal counter 3 is fed to a divide-by-six counter 4. A decimal counter 5 and a divide-by-six counter 6 count time units of minutes, and a decimal counter 7 and a divide-by-six counter 8 count time units of hours. All the aforementioned counters produce timing signal outputs in the form of binary decimal coded outputs. A duodecimal counter 9 counts a carry output pulse of the counter 4 or time adjusting pulses described later herein. A timing pulse generator 10 receives output pulses such as pulses of 128 Hz from the frequency divider 2 and successively produces timing pulses at terminals P.sub.1 P.sub.3. Perodical pulses produced at the terminal P.sub.1 trigger a flip-flop circuit 11 which produces pulses at an output terminal Q thereof which are fed to a voltage selector 12. The voltage selector 12 produces periodically relative voltages 0, v.sub.0, 2v.sub.0 and 3v.sub.0 at terminals S.sub.0, S.sub.1, C.sub.0, and C.sub.1, respectively. The pulses at the terminal P.sub.2 of the timing pulse generator 10 are fed to an input terminal of OR gate circuit 13 via a line L.sub.4 and the pulses at the terminal P.sub.1 are fed to an input terminal of AND gate circuits 14 and 15 via a line L.sub.5. An output appears along a resistor 16 depending upon the ON or OFF operation of a manual switch 17 connected to a positive potential E.sub.0 and the output is directly fed to the other input terminal of the AND gate circuit 15 and is also fed via an inverter 18 to the other input terminal of the AND gate circuit 14. Gate circuits 19 to 21 having AND logic function control passage of input data thereof responsive to pulses fed via lines M.sub.2, M.sub.1 and L.sub.3, respectively. Gate circuits 22 to 24 having AND logic function control passage of input data thereof responsive to the pulses fed via the lines M.sub.2, M.sub.1 and L.sub.3, respectively. Gate circuit 25 having OR logic function feeds time data from the gate circuits 19 to 21 to a decoder 26 for converting code of input data thereof. Gate circuit 27 having OR logic function feeds time data from the gate circuits 22 to 24 to a decoder 28 for converting code of input data thereof. The output of the decoder 26 is fed to an output conversion circuit 29 for changing the order of outputs produced from output terminals z.sub.0 to z.sub.9 responsive to inputs fed directly and via an inverter 30 from a 2.sup.0 terminal of the gate circuit 27. The outputs of the output conversion circuit 29 are fed to a segment voltage supply circuit 31 for producing voltages to be applied to segment electrodes explained later herein. The outputs of the decoder 28 are fed to a common voltage supply circuit 32 to be applied to common electrodes explained later as well as the segment electrodes. Block 33 represents a time adjusting pulse generator the output pulses from which are generated in accordance with a rotation of a rotary means which is mounted to be rotated around an axis by manual operation. As an example thereof, reference is made to U.S. Pat. No. 4,196,584 and West German patent application No. P2805005.7 (Offenlegungsschrift No. 2805005) which were filed prior to the present application. The time adjusting pulses are fed to the counter 9 via an AND gate circuit 34 and an OR gate circuit 35.

The display device is of the liquid crystal type and includes segment electrodes, generally designated 36 in FIG. 2, consisting of 60 radial segment electrodes 36a equally spaced round a circle. The first ten of the segment electrodes 36a--36a are respectively connected to the terminals e.sub.1 to e.sub.10 of the segment voltage supply circuit 31. The remaining segment electrodes are connected with the following relations. The count order of the segment electrodes designated below is in the clockwise direction starting with the segment electrode 36a which is connected to the terminal e.sub.1 as the first one. The 10th segment electrode 36a is connected to the 11th; the 9th segment electrode is connected to the 12th--and the 1st segment electrode being connected to the 20th which is connected to the 21st; the 19th segment electrode being connected to the 22nd--the 11th segment electrode being connected to the 30th.

The display device also includes common electrodes, generally designated 37 in FIG. 3. The common electrodes consist of six similar inner common electrodes 37a and six similar outer common electrodes 37b. The radial spaces 37c which separate the individual common electrodes 37a and 37b from one another radially are located between the 10th segment electrode and the 11th; between the 20th segment electrode and the 21st; between the 30th segment electrode and the 31st; between the 40th segment electrode and the 41st; between the 50th segment electrode and 51st, and between the 60th segment electrode and the 1st (counting in the clockwise direction).

The segment electrode system is positioned over the common electrode system and a layer of liquid crystal material (not shown) is interposed between the two systems in a sealed housing (not shown) through which the display given can be observed.

FIG. 4 shows in some detail the output conversion circuit 29 and the segment voltage supply circuit 31 of FIG. 1. Reference numerals 38 to 47 denote AND gate circuits; 48 to 52 denote OR gate circuits; 53 to 62 are switching circuits which may be like those in FIG. 1; and 63 to 67 are inverters.

FIG. 5 shows in some detail the voltage selector 12 of FIG. 1A. References 68 to 75 denote switching circuits which may be constructed in the same manner as described in FIG. 1A; 76 is inverter.

FIG. 6 shows in some detail the common voltage supply circuit 32 of FIG. 1C. Reference numerals 77 to 82 denote AND gate circuits; 83 to 92 are switching circuits which may be constructed in the same manner as described above; and 93 to 97 are inverters.

A description will now be given of the relative voltages to be applied to the segment electrodes and the common electrodes.

Let it be assumed that values of the relative voltages are predetermined and that the liquid crystal display device used in this embodiment will not exhibit a display due to the periodical voltage differences between one of the segment electrodes and one of the common electrodes beneath it if the voltage differences are smaller than .vertline.v.sub.0 .vertline. but will exhibit a display if the voltage differences are 3.vertline.v.sub.0 .vertline. or more. On this assumption, a voltage of 0(zero) is applied to terminals 1.sub.1 and 1.sub.4 ; a voltage v.sub.0 is applied to terminals 1.sub.2 and 1.sub.7 ; a voltage 2v.sub.0 is applied to terminals 1.sub.3 and 1.sub.6 ; and a voltage 3v.sub.0 is applied to terminals 1.sub.0 and 1.sub.5.

In FIG. 1, when periodical pulses are produced at the terminal P.sub.1 of the timing pulse generator 10, the respective pulses therefrom trigger the flip-flop circuit 11 thereby producing periodical pulses at the output terminal Q thereof. Consequently in FIG. 5, the voltages 0 and 3v.sub.0 are alternately produced at the terminal S.sub.0 ; the voltages v.sub.0 and 2v.sub.0 are alternately produced at the terminal S.sub.1 ; the voltages 0 and 3v.sub.0 are alternately produced at the terminal C.sub.0 ; and the voltages 2v.sub.0 and v.sub.0 are alternately at the terminal C.sub.1. The relations of those voltages are illustrated in a Table of FIG. 7. In this Table the voltages v.sub.s are those which may be assumed by the terminals S.sub.0, S.sub.1 and the voltages v.sub.c are those which may be assumed by the terminals C.sub.0, C.sub.1. Among these two groups of voltages, those on the left are voltages that will be produced at the terminals S.sub.0, S.sub.1, C.sub.0 and C.sub.1 every time a pulse is produced at the terminal P.sub.1. In the remainder of the Table voltage differences between the respective voltages produced at the terminals S.sub.0, S.sub.1 and the respective voltages produced at the terminals C.sub.0, C.sub.1, namely the voltages of v.sub.s-c are illustrated. As will be seen from the Table, when a voltage is applied between the terminals S.sub.0 and C.sub.0 a display element corresponding to the electrodes connected thereto is displayed.

Under the aforementioned assumption, a description will now be given of the operation of the timepiece. When no time adjusting operation is being made, the manual switch 17 of FIG. 1C is kept open. Therefore the logic level on the line L.sub.6 is a logic "0", which is inverted to a logic "1" by the inverter 18 to open the AND gate circuit 14. Therefore periodical pulses at the terminal P.sub.1 of the timing pulse generator 10 appear at the output terminal of the AND gate circuit 14. Meanwhile periodical pulses at the terminal P.sub.2 of the timing pulse generator 10 appear at the output terminal of the OR gate circuit 13 via the line L.sub.4.

In order to explain a time display on the basis of a concrete example, let it be assumed that the counters 3 to 8 have counted 0 seconds 5 minutes past 10. In this case, the counter 3 counts "0"; the counter 4 counts "0"; the counter 5 counts "5"; the counter 6 counts "0"; the counter 7 counts "0"; the counter 8 counts "5"; and the counter 9 counts "5". In this state, when the periodical pulses are at the terminal P.sub.1 of the timing pulse generator 10, the gate circuits 19 and 22 are opened to feed output data corresponding to time units of a second from the counter 3 to the gate circuit 25 and to feed another output data corresponding to time units of a second from the counter 4 to the gate circuit 27. Therefore a logic "0" is produced at the 2.sup.0 to 2.sup.3 terminals of the gate circuit 25 and also at the 2.sup.0 to 2.sup.2 terminals of the gate circuit 27. Consequently a logic "1" is produced at the terminal h, a logic "0" is produced at the terminal h, and a logic "1" is produced at the terminal x.sub.0 of the decoder 26. Meanwhile referring to the circuit of FIG. 4, a logic "1" is produced at both output terminals of the AND gate circuit 38 and the OR gate circuit 48 so that voltages being fed to the terminal S.sub.0 produce at the terminal e.sub.1. Furthermore the switching circuits 54 to 56, 58 to 60, and 62 are turned ON to produce voltages being fed to the terminal S.sub.1 at the terminals e.sub.2 to e.sub.10. In addition the decoder 28 produces a logic "1" at the terminal y.sub.0 to produce voltages being fed to terminal C.sub.0 at the terminal k.sub.1 of FIG. 6. Meanwhile the AND gate circuits 77 to 82 are opened in consequence of that a logic "1" is produced at the terminal P.sub.3. The above logic level of the terminal P.sub.3 is for the reason that while a pulse is being produced at the terminal P.sub.1 there is no pulse produced at the terminal P.sub.3, as a result, a logic at the terminal P.sub.3 being "0", therefore a logic "1" is resulted from the terminal P.sub.3 which an inverted output from the terminal P.sub.1 is produced.

Now since the gate circuits 77 to 82 are opened, the switching circuit 83 is turned ON to produce voltages fed to the terminal C.sub.0 at the terminal g.sub.1. Meanwhile voltages fed to the terminal C.sub.1 produce at the terminals k.sub.2 to k.sub.6 and g.sub.2 to g.sub.6. Since the voltages described hereinbefore are fed to the terminals, as will be seen from the Table of FIG. 7, the display element denoting a time unit of a second corresponding to the segment electrode S of FIG. 2 is displayed.

In case the periodical pulses are produced at the terminal P.sub.2 of the timing pulse generator 10 in FIG. 1A, the AND gate circuits 20 and 23 are opened to permit the counted time data "5" and "0" of the counters 5 and 6, respectively to pass therethrough. Therefore a logic "1" produces at the terminal x.sub.5 of the decoder 26, at the terminal y.sub.0 of the decoder 28 and at the terminal h, and further a logic "0" produces at the terminal h. Consequently a logic "1" produces at the output terminal of the gate circuit 50 of FIG. 4 and the switching circuit 57 is turned ON, so that voltages fed to the terminal S.sub.0 produce at the terminal e.sub.6. Voltages fed to the terminal S.sub.1 produce at the terminals e.sub.1 to e.sub.5 and e.sub.7 to e.sub.10. In FIG. 6 voltages fed to the terminal C.sub.0 produce at the terminals g.sub.1, k.sub.1 and voltages fed the terminal C.sub.1 produce at the terminal g.sub.2 to g.sub.6 and k.sub.2 to k.sub.6. As will be seen from the Table of FIG. 7, there is displayed a display element of minute which is constructed of the segment electrode M(see for FIG. 2) connected to the terminal e.sub.6 and the common electrodes connected to the terminals g.sub.1, k.sub.1.

In case periodical pulses are produced at the terminal P.sub.3 of the timing pulse generator 10, the AND gate circuits 21 and 24 are opened to permit the counted time data "0" and "5" from the counters 7 and 8 to pass therethrough. Consequently voltages being fed to the terminal S.sub.0 produce at the terminal e.sub.10 of the segment voltage supply circuit 31, voltages being fed to the terminal C.sub.0 produce at the terminal k.sub.6 and voltages being fed to the terminal C.sub.1 produce at the terminals k.sub.1 to k.sub.5. While one pulse produces at the terminal P.sub.3 a logic level of which comes to "1" and thus that on the terminal P.sub.3 is kept at "0", the outputs of the AND gate circuits 77 to 82 comes to a logic "0". Consequently voltages being fed to the terminal C.sub.1 produce at the terminals g.sub.1 to g.sub.6. Therefore a display element, which comprises a segment electrode H of FIG. 2 electrically connected with the terminal e.sub.10 and a common electrode connected to the terminal k.sub.6, is displayed.

The voltages periodically applied by the segment voltage supply circuit 31 and the common voltage supply circuit 32 to the terminals e.sub.1 to e.sub.10, g.sub.1 to g.sub.6 and k.sub.1 to k.sub.6 comprise pulse signals which, in a manner known in the art, energize the segment and common electrodes of the display device.

As will be apparent hereinbefore, the display elements corresponding to the segment electrodes H, M and S display 10 hours 5 minutes 0 seconds.

Below is explained the time adjusting operation. When the manual switch 17 of FIG. 1C is closed, the frequency divider 2 and the contents of time units of seconds are reset, so that the contents in the counters 3 and 4 become "0". Furthermore the AND gate circuit 34 is opened to enable time adjusting pulses to pass therethrough. A logic "1" produced on the line L.sub.6 opens the AND gate circuit 15, so that pulses produced at the terminals P.sub.1 and P.sub.2 of the timing pulse generator 10 appear at the terminal M.sub.2. Consequently the AND gate circuits 19 and 22 of time units of seconds are held in a closed condition, the AND gate circuits 20 and 23 of time units of minutes are opened during selection of the time units of seconds and minutes, and the AND gate circuits 21 and 24 of time units of hours are opened responsive to pulses produced at the terminal P.sub.3. In this state, as pulses are generated from the time adjusting pulse generator 33 by manual operation, the contents in the counters 5 to 8 are changed every time the respective pulses are inputed, by which speed shifting a display portion from one to the next display element is altered depending upon a period when the contents in the counters 5 and 6 are successively changed.

Here, in the case of adjusting the time, the AND gate circuits 20 and 23 are opened twice during the time of a period when they are opened when the usual time display (in no time adjustment is being carried out), so that in the time adjusting state the effective value of voltage to be applied to the liquid crystal comes to be larger by .sqroot.2 multiple to accordingly increase the response speed of the liquid crystal and enhance the display contrast. Therefore even if the frequency of pulses for adjusting the time becomes relatively higher, the display elements for minute will be turned on.

It is understood that the control time of the AND gate circuit 20 and 23 is not limited to that of the embodiment described hereinbefore. For example, in case of adjusting the time, it may be also possible to make the effective value of the voltages larger than in the case of the usual time display by time-divisionally controlling the gate circuits for minutes and hours under keeping the gate circuits 19, 22 for seconds at a closed state. As mentioned above in detail, according to this invention since the effective value of voltages to be applied to the display elements for adjusting the time is a larger value than that of the usual time display, even if the frequency of pulses for adjusting the time comes to be relatively higher, a display element to be adjusted will be turned on. In this manner, when the time is being adjusted, the contrast between the display and non-display portions is enhanced, and as a result it is easy to recognize the shifting of the adjusting display portion.