Waveform Synthesizer Arrangement

This invention relates to a waveform synthesizer arrangement for use in various audible output devices.

Generally, in the case where digital information signals which are to be eventually converted into an analog form are derived in a sequence of time, noise in a resulting synthesized waveform varies in nature according to the physical density of digitally encoded data and resolution of quantized values.

While noise can be actually reduced by increasing sampling frequency and the amount of quantized bits, this is disadvantageous due to an increase in the number of data to be treated.

The inventors have recognized that a synthesized waveform with a minimum generation of noise may be easily recoverable when a given process is executed on the data to be reproduced with a consideration of the total nature of the waveform of interest. Since respective values of the data subject to a time sequential process are affected by previous data and have the effect on the frequency construction of resulting waveforms in conjunction with the relative position of the data, it has been found that it is possible to minimize noise harsh to the human's ear by carrying out the time sequential process to exhibit some filtering effect.

Accordingly, it is a general object of the present invention to provide a waveform synthesizer arrangement which may produce any synthesized waveforms with a minimum level of noise depending on the foregoing findings by the inventors.

Briefly, according to the present invention a waveform synthesizer arrangement is provided which comprises memory means for storing quantized waveform information in the form of digital signals, means for obtaining said waveform information as a parameter of sampling time, means for executing arithmetic operations in response to said parameter information, means for providing proper waveform adjustment for a desired one of the parameters in accordance with the results of the arithmetic operations, and means for converting said digital waveform information into analog information.

The foregoing as well as other objects, features and advantages of the present invention will become more readily appreciated upon the consideration of the following detailed description of the illustrated embodiments, together with the accompanying drawings, wherein:

FIG. 1 is a waveform diagram plotting amplitude as a function of time for explanation of a waveform synthesizer arrangement constructed in accordance with the present invention;

FIG. 2 is a schematic block diagram of the waveform synthesizer arrangement of the present invention;

FIG. 3 is a flow chart illustrating the operation of the arrangement of FIG. 2;

FIG. 4 is a waveform diagram for explanation of another embodiment of the present invention;

FIG. 5 is a schematic block diagram of the embodiment of the present invention as shown in FIG. 4;

FIG. 6 is a flow chart illustrating the operation of the arrangement of FIG. 5;

FIG. 7 is a schematic block diagram of a modification in a part of the above illustrated arrangements; and

FIG. 8 is a flow chart associated with the modification of FIG. 7.

Referring initially to FIG. 1, there is illustrated a waveform diagram for explanation of operation of a waveform synthesizer arrangement constructed in accordance with one preferred embodiment of the present invention, wherein quantized amplitude is plotted as a function of time. Briefly speaking, a specific waveform of interest is previously sampled and qualified values (sampled values) N.sub.0 -N.sub.i are derived every sampling frequency.

The waveform as shown in full lines is derived in the case when the synthesizer arrangement does not utilize the present invention, whereas the counterpart as shown in broken lines is derived in the case that present invention is embodied in the synthesizer arrangement. In other words, according to the principle of the present invention, the respective values N.sub.4, N.sub.5, N.sub.6 and N.sub.10 as identified by O are modified or adjusted to respective values of amplitude as identified by X for provision of outputs, thus flattening accute changes in waveform and providing desirable synthesized waveforms with a minimum noise.

FIG. 2 is a schematic block diagram of an arrangement for implementing the present invention, wherein a memory generally designated 1 may be, for example, a read only memory (ROM). This ROM stores the previously sampled and quantized digital values N.sub.i. Buffer memories 2, 3, 9, 10 and 13 store temporarily the data derived from the memory 1. A coincidence detector 4 is provided to decide if the data stored in the buffer register 2 is equal in amplitude to that in the register 3. A comparator 6 compares the count of a counter 5 with a preselected value n. A subtractor 7 subtracts the contents of the buffer register 3 from the contents of the buffer register 2 and executes such subtraction only if both the data stored in the buffer registers 2 and 3 are equal in amplitude to each other. A divider 9 divides the results of such subtraction by the count of the counter 5, while an adder 11 adds the contents of the buffer register 9 to that of the buffer register 10. A selector 12 selects the output of the adder 11 and the output of the buffer register 3 and feeds such selection to the input of the buffer register 13. A digital-to-analog converter 14 of a well known construction is adapted to convert digital data derived from the buffer 13 into analog data. It further includes an output circuit 15 and an oscillator 16.

Operation of the synthesizer arrangement described will be more readily understood by reference to FIG. 3 which is a flow chart of the circuit of FIG. 2.

Respective registers, flip flops and like elements within the above arrangement are first placed into their initial conditions. The data N.sub.1, N.sub.2, N.sub.3 and so on as viewed in FIG. 1 are derived in sequence. Assume now that the value n provided for the comparator 6 is 3.

The data N.sub.0 are first recalled from the memory ROM 1 and loaded into the buffer register 2. When the data N.sub.1 are fetched from the memory 1 and loaded into the buffer register 2, the previous data N.sub.0 is transferred into the buffer register 3. Thereafter, the coincidence detector 4 compares these sampled data values N.sub.0 and N.sub.1 as shown in FIG. 1 if the both are same. In the given example, it compares the contents of the counter 5 and the preselected value n=3 and if C<n increments the contents of the counter 5 by one, allowing the next succeeding data N.sub.2 to be fetched from the memory ROM 1 and further incrementing the contents of the counter 5 in the same manner described. The contents of the counter 5 are incremented by one in this manner until the data N.sub.3 are processed. In other words, the steps n.sub.1 .fwdarw.n.sub.2 .fwdarw.n.sub.3 .fwdarw.n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.6 .fwdarw.n.sub.7 .fwdarw.n.sub.3 .fwdarw.n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.6 .fwdarw.n.sub.7 .fwdarw.n.sub.3 and so on.

The step n.sub.3 is carried out to fetch the data N.sub.4 from the memory 1 and decide through the use of the coincidence detector 4 if the contents of the buffer registers 2 and 3 are both same. When N.sub.4 =N.sub.3 and the contents of the counter 5 are C=n(=3), no increment of the counter 5 takes place. The contents (N.sub.3) of the buffer register 3 are fed via the selector 12 in timed relationship with the sampling frequency Sf into the buffer register 13 whose contents in turn are delivered externally in the form of a synthesized waveform via the digital-to-analog converter 14 and the output circuit 15. The data N.sub.0 is thus outputted in this manner. This operation is achieved by execution of the steps n.sub.3 .fwdarw.n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.6 .fwdarw.n.sub.8 .fwdarw.n.sub.9 (see FIG. 3). During the time that the data N.sub.5 and N.sub.6 are fetched from the memory 1 the waveforms corresponding to the data N.sub.1 and N.sub.2 are developed through the buffer register 13, the digital-to-analog converter 14 and the output circuit 15, similarly.

If the data N.sub.7 are derived from the memory 1 during the step n.sub.3, the data N.sub.6 and N.sub.7 are not equal (as shown in FIG. 1) such that the subtractor 7 carries out subtraction on the buffers 1 and 2 designated 2 and 3 respectively with the results of subtraction being divided by the contents of the counter 5 i.e., (C+1), through the action of the divider 8, that is, (Buff 1-Buff 2)/(C+1). The results of this division are stored in the buffer register 9 for the time being and at the same time the contents of the buffer register 3 are sent to the next succeeding stage buffer register 10. The contents of the buffer register 3 are further fed via the selector 12 into the buffer register 13 and delivered through the circuits 14 and 15 in the same manner as described above, thus executing in succession the steps n.sub.3 .fwdarw.n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.10 .fwdarw.n.sub.11 .fwdarw.n.sub.12 .fwdarw.n.sub.13 .fwdarw.n.sub.14 to output the data N.sub.3. In connection with the data N.sub.4 that are about to be next delivered, the adder 11 executes addition on the contents of the buffer registers 9 and 10 with the result of addition being again loaded into the buffer register 10 and then to the buffer register 13 via the selector 12. This leads to the delivery of the data N.sub.4 through the digital-to-analog converter 14 and the output circuit 15. Accordingly, the waveform corresponding to the data N.sub.4 is outputted at the level denoted by X not at the level denoted by O, thus making waveform adjustment as viewed in FIG. 1. Upon the delivery of the data N.sub.4 the counter 5 is decremented by one and it is decided as to whether the decremented contents of the counter are zero. If not, addition is effected on the contents of the buffer registers 9 and 10 and the data N.sub.5 are delivered via the buffer register 13, the digital-to-analog converter 14 and the output circuit 15. In other words, the data N.sub.5 is not outputted at the level marked by O but at the level marked by X (FIG. 1). After the completion of the delivery of the data up to the data N.sub.6 the counter 5 shows C=0 to cause the data N.sub.8 to be fetched from the memory 1. The steps n.sub.15 .fwdarw.n.sub.16 .fwdarw.n.sub.17 .fwdarw.n.sub.18 .fwdarw.n.sub.15 .fwdarw.n.sub.18 .fwdarw.n.sub.3 are therefore carried out.

The above mentioned operation is executed such that the data N.sub.4 -N.sub.6 are varied and modified from their initial values to the different values as defined by X prior to their delivery.

At the moment when the data N.sub.8 are fetched from the memory 1, the data N.sub.8 and N.sub.7 are respectively stored within the buffer registers 2 and 3. Since the both are different in amplitude and the counter 5 shows C=0, the contents of the buffer register 3 are transferred via the selector 12 into the buffer 13 and externally delivered from the digital-to-analog converter 14 and the output circuit 15. The next step is to fetch the data N.sub.9 from the memory 1. This is accomplished by execution of the steps n.sub.3 .fwdarw.n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.10 .fwdarw.n.sub.8 .fwdarw.n.sub.9 .fwdarw.n.sub.3. During this operation the respective data are delivered as they are. In the case that only two adjacent data as N.sub.9 and N.sub.10 assume the same magnitude, they are deliverd at its intermediate level.

In this manner, accute waveforms are modified so as to reduce noise in accordance with the teachings of the present invention.

FIG. 4 is a waveform diagram for explanation of another preferred embodiment of the present invention wherein not only output values for adjustment but also a predetermined number of output values located before and after the just mentioned output values are modified for the purpose of the present invention. In the case that only one value varies between a first succession of the same data and a second succession of the same data, a predetermined number of output values before and after that transient value suffer from the adjustment process of the present invention. In other words, the waveform is derived at these modified sample values (X) other than the original sample values (O).

FIG. 5 is a schematic block diagram for realizing synthesis of the above illustrated waveform of FIG. 4 and FIG. 6 is a flow chart for explanation of operation of the circuit arrangement shown in FIG. 5.

As noted earlier, the waveform of FIG. 4 shows only a middle part of an overall waveform to be reproduced. Thus, the data N.sub.0 and N.sub.1 have already stored in buffer registers 117 and 102, respectively. By the actions of a memory 101, the buffer register 102 and another buffer 103 the data N.sub.2 are fetched from the memory 101 and a coincidence detector 104 provides a disparity signal and decision circuits 118 and 123 sense if the contents of counters 105 and 120 are zero, respectively. If the two counters assume zero, then the contents of a buffer 117 are shifted toward a buffer register 113. This means that the data N.sub.0 are externally delivered. The data N.sub.0 are delivered through a string of the steps n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.8 .fwdarw.n.sub.10 .fwdarw.n.sub.11 .fwdarw.n.sub.4. Upon the fetching of the data N.sub.3 the coincidence detector 104 provides an equality signal at this time and a comparator 106 decides if the contents C.sub.1 of a counter 105 is equal to the value 2n applied thereto. If C.sub.1 =2n, the count C.sub.1 of the counter 105 is incremented to effect C.sub.1 +1.fwdarw.C.sub.1 and the data is fetched from the memory 101 (ROM). For example, when n=3, the count C.sub.1 of the counter 105 is incremented by a string of the steps n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.6 .fwdarw.n.sub.7 .fwdarw.n.sub.4. After repetition of this operation the data N.sub.9 is fetched from the memory. Provided that the coincidence detector 104 provides an equality signal and the comparator 106 also provides an equality signal, the count C.sub.1 of the counter 105 is added via a 1/2 circuit 119 and a +1 circuit 121 to the count C.sub.2 of the counter 120 by the action of an adder 122 with the result of addition being loaded into a counter CNT 123. A subtractor 107, on the other hand, reduces the contents of the buffer register 103 by that of the buffer register 117, that is, (Buff 2-Buff 3). This result is divided by the contents of the counter (CNT0) 123 through a divider 108, with the result of division being loaded into the buffer register 109. In this instance C.sub.1 =6 and C.sub.2 =0 and thus the count of CNT is 4. Under these circumstances the contents of the buffer 117 are sent to the buffer 113 via the selector 112 and externally delivered after digital-to-analog conversion. This means the delivery of the data N.sub.1. Subsequently to this, the contents of the counter CNT (123) are decremented by one and this result is monitored by a "0" detector 124. If the result is not zero, the adder 111 effects addition on the contents of the buffers 4 and 5, with the result being transferred into the buffer 113 through the selector 112. Simultaneously, the result is again loaded into the buffer 110. This implies that the data N.sub.2 is externally delivered. This sequence of operation is repeated on the data up to N.sub.4 until the counter CNT=0. Accordingly, the steps n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.6 .fwdarw.n.sub.13 .fwdarw.n.sub.14 .fwdarw.n.sub.15 .fwdarw.n.sub.16 .fwdarw.n.sub.17 .fwdarw.n.sub.18 .fwdarw.n.sub.16 are executed. When When CNT=0, arithmetic operations Buff 2.fwdarw.Buff 3 (103.fwdarw.117) and Buff 3.fwdarw.Buff 6 (117.fwdarw.113) take place, thus externally delivering the data N.sub.5. Then, the data N.sub.5 is fetched from the memory 101 and the detector 104 senses if there is equality between the contents of the buffers 102 and 103. If yes the operation Buff 3.fwdarw.Buff 6 is effected. Then if the data N.sub.11 is loaded into the buffer, no equality signal is developed so that the contents C.sub.1 of the counter 105 is divided by 2 by the 1/2 circuit 119 and fed into the counter 120 with the counter 105 being cleared for further readout of the data. This operation is accomplished by a string of the steps n.sub.17 .fwdarw.n.sub.19 .fwdarw.n.sub.20 .fwdarw.n.sub.22 .fwdarw.n.sub.23 .fwdarw.n.sub.24 .fwdarw.n.sub.22 .fwdarw.n.sub.23 .fwdarw.n.sub.24 .fwdarw.. . . n.sub.25 .fwdarw.n.sub.4. The same data thereafter continues to be fetched by the steps n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.6 .fwdarw.n.sub.7 .fwdarw.n.sub.4 until the comparator 106 develops an equality signal. During the step n.sub.4 the data N.sub.18 is fetched to allow the comparator 106 to provide the equality signal. The steps n.sub.13 and n.sub.14 place "7" into the counter CNT 123 and divide the difference (Buff 2-Buff 3) by seven, the result of such division being loaded into the buffer 4. The above described operation externally delivers the data N.sub.7 through N.sub.13 through execution of the steps n.sub.13 .fwdarw.n.sub.14 .fwdarw.n.sub.15 .fwdarw.n.sub.16 .fwdarw.n.sub.17 .fwdarw.n.sub.18 .fwdarw.n.sub.16 and so on. In this way, the waveform as shown by O is modified and changed into that as shown by X for the delivery of outputs, as is clear from FIG. 4.

In the case where the amount of continuous same data is less than that required for the adjustment process, the data is externally outputted as is. For example, the data N.sub.0 is delivered in the embodiment of FIG. without suffering from the adjustment process of the present invention. Only the addition of a comparator 17 of FIG. 7 to the arrangement as shown in FIG. 2 is needed, which comparator compares n'(<n). Referring to the flow chart of FIG. 3, if the value C is smaller than n' during the step n.sub.10, the arithmetic operation C-1.fwdarw.C is executed each time the subtraction Buff 2-Buff 5 is carried out. This is accomplished by modifying a part of the arrangement of FIG. 3 as viewed in FIG. 8.

Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.