Vectorcardiogram Simulator

This application is related to co-pending application entitled "Interconnection System For A Biological Waveform Simulator Device" by Power et al, U.S. Ser. No. 93,086, now U.S. Pat. No. 4,267,576, filed concurrently herewith and having the same assignee as the present invention.

This invention relates to waveform generators and, more particularly, to biological waveform simulator devices for testing the operability of medical electronic equipment.

There is an increasing trend towards using more electronic equipment in the medical profession. Typical of such equipment includes the use of blood pressure monitors, electrocardiogram machines, and vectorcardiogram machines. It is obviously of paramount importance that these devices operate properly at all times. For many years, malfunctions of these devices were detected primarily by observing the operation of the machine on a live patient. The time required to either fix the malfunction or replace the machine is obviously detrimental in emergency situations. Moreover, it was difficult to detect whether the machine, while appearing to perform normally, was actually calibrated properly and generating a correct reading.

To correct many of these problems noted above, simulator devices have been utilized to simulate biological waveforms that can be used to test the operability of blood pressure monitors and electrocardiogram machines. Examples of these devices are more fully disclosed in U.S. Ser. No. 882,357, entitled "Complex Analog Signal Generator", filed Mar. 1, 1978, (now U.S. Pat. No. 4,204,261); and U.S. Ser. No. 938,430, entitled "Electrocardiographic Blood Pressure Waveform Simulator Device", filed Aug. 31, 1978, (now U.S. Pat. No. 4,205,386). These simulators, while having provided extremely satisfactory results, are not capable of testing the operability of a vectorcardiogram machine. Vectorcardiogram machines are somewhat complicated devices in which electrocardiograms are taken along three axes (X, Y, and Z) at right angles to one another, with any two of these ECG's being displayed as a vector on an X-Y oscilloscope. The present invention is directed to fulfilling a long felt need for a reliable, yet relatively inexpensive, means for testing the operability of vectorcardiogram machines before being utilized on a live patient.

This need has been accomplished by way of an electronic waveform simulator device made in accordance with this invention which simulates waveforms for testing the operability of a vectorcardiogram machine. According to the broadest aspect of this invention, generator means are provided for generating waveforms which simulate electrical activity within the human heart along three separate axes.

In one embodiment, the device includes X waveform generator means for generating a waveform generally simulating an X-axis vectorcardiogram waveform. Y waveform generator means are provided for generating a waveform generally simulating a Y-axis vectorcardiogram waveform. Z waveform generator means are also provided for generating a waveform generally simulating a Z-axis vectorcardiogram waveform. Connector means selectively coupled to the X, Y, and Z waveform generator means are operative to supply output signals to a vectorcardiogram machine corresponding to waveforms that would ordinarily be supplied by a plurality of electrodes attached to a patient at various positions. Preferably, the connector means provides output signals which correspond to waveforms that would be generated by a patient in which the electrodes are attached at FRANK electrode positions.

According to the method of this invention, three distinct waveforms are generated by shaping and delaying a single reference waveform generally corresponding to an electrocardiogram waveform. A plurality of connectors are selectively coupled to the waveforms such that they provide output signals to the VCG machine corresponding to waveforms that would ordinarily be supplied by a plurality of electrodes attached to a live patient at various positions.

Preferably, an X waveform is generated by coupling a reference waveform, generally corresponding to an ECG waveform, to an electronic bucket brigade and delaying the output of the bucket brigade for a first time period. The Y waveform is similarly generated but its associated bucket brigade provides a delay time period different from the first time period. The Z waveform is generated by inverting the Y waveform and summing it with a reference ECG waveform. The summed waveform is inverted and coupled to a third bucket brigade which provides a third delay time period.

These and other objects and advantages of the present invention will become apparent upon reading the following specification and by reference to the drawings in which:

FIG. 1 is a view showing FRANK electrode positions on a patient which are used in vectorcardiography;

FIG. 2 is a circuit diagram showing a FRANK attenuation and compensation network;

FIG. 3 is a block diagram of the preferred embodiment of the electrical circuitry of the present invention;

FIGS. 4 (A-B) is a schematic diagram showing the details of the circuitry shown in block diagram form in FIG. 3;

FIG. 5 is a timing chart showing clock signals utilized by the circuitry of FIG. 4;

FIG. 6 is a graph showing X, Y, and Z waveforms generated according to the teachings of the present invention; and

FIG. 7 is a plan view illustrating the simulator device of the present invention in use with a vectorcardiogram machine.

By way of background, FIG. 1 shows typical electrode positions which are utilized in vectorcardiography. The labeled positions in FIG. 1 correspond to known FRANK electrode positions. These electrodes, labeled LA, RA, C, E, M, LL, H, and RL are coupled through a FRANK attenuation and compensation network as shown in FIG. 2 to a vectorcardiogram machine. The outputs X', Y', and Z' contain information relating to the electrical activity within the heart along the designated axes shown in FIG. 1. As is known in the art, the vectorcardiogram machine includes an X-Y oscilloscope which is used to display any two of these ECG's as a vector display or loop. The present invention is directed to simulating waveforms to be carried over the various electrodes to the vectorcardiogram machine for testing same.

FIG. 3 is a block diagram of the electrical circuitry of the present invention. The circuitry 10 includes an input 12 for receiving a simulated ECG (electrocardiographic) waveform. The simulated ECG waveform may be provided by a variety of means. A preferred means is disclosed in the above-identified U.S. Ser. No. 938,430 now U.S. Pat. No. 4,205,386), entitled "Electrocardiographic and Blood Pressure Waveform Simulator Device" which is hereby incorporated by reference. The input waveform provides a reference signal for driving basically all of the waveform generators after being buffered by buffer circuitry 14. The buffered reference waveform passes by way of amplitude and offset conditioning circuitry 16 prior to entering the chain of functional blocks making up the X and Y generators. The Y waveform generator includes an electronic bucket brigade 18 for delaying the reference input signal for a predetermined period of time as defined by the Y clock 20. The delayed signal is coupled to a Y clock noise attenuator 22 which acts to cancel the effect of the clock signals on the generated output. Additional filtering is provided by a low pass filter 24. The Y component signal is amplified by buffer circuitry 26 which includes a resistive network 28 to compensate for the DC offset of the waveform.

Similarly, the X waveform generator includes bucket brigade circuitry 30 which is driven by an X clock 32 such that the bucket brigade delays the waveform for a period which is different than the delay period for the Y waveform. The X waveform generator further includes clock noise attenuator circuitry 33, low pass filter circuitry 34, X signal buffer 36 and associated offset circuitry 38, all of which operate in a similar manner as the corresponding components in the Y waveform generator.

The Z waveform generator, however, includes a summing and inverting amplifier circuit 40 which serves to sum an inverted version of the generated Y waveform with the reference ECG waveform and invert the summed waveform after suitable offset conditioning by way of circuitry 42. Buffer 44 passes the combined signal to a Z bucket brigade 46 which is driven by Z clock 48 at a frequency sufficient to cause a third predetermined delay therein. The remainder of the Z waveform generator is similar to the X and Y generators in that it includes clock noise attenuator circuitry 50 and low pass filter 52, the offsetting and buffering functions being previously performed by circuits 40, 42, and 44 in the Z waveform generator chain.

Bias circuit 49 provides the appropriate voltage levels for driving each of the bucket brigades 18, 30, and 46.

The outputs of the X, Y, and Z generators are coupled to an amplitude adjustment circuit 54 to which output connector leads LL, H, C, RA, LA, M, E, and RL are connected. The outputs of these connector leads provide input signals to a vectorcardiogram machine corresponding to waveforms that would ordinarily be supplied by a plurality of electrodes attached to a patient at various positions. In particular, the outputs of the connectors correspond to examples of signals which would be generated by a patient in which the electrodes are connected in the FRANK electrode position shown in FIG. 1.

The FRANK attenuation and compensation network shown in FIG. 2 will modify the incoming signals somewhat to provide X', Y', and Z' waveforms to the VCG according to this known convention. However, the simulated X, Y, and Z waveforms provided by the respective generators generally correspond to waveforms which are representative of electrical activity within the human heart along the X, Y, and Z axes shown in FIG. 1. Thus, the simulator device of the present invention may be made compatible with other electrode conventions such as axial, cube, and tetrahedron electrode positions with but minor modifications.

Turning now to the details of the circuitry shown in FIG. 4, the components making up the functional blocks of FIG. 3 will be encompassed by dotted lines to aid the reader in ascertaining the correspondence therebetween. A description of the component by component interconnection in the specification will not be undertaken since the precise interconnection details are more than obvious by reference to the drawings. Instead, only the major functional components will be described.

In FIG. 4A, input buffer 14 utilizes an operational amplifier 60 having its noninverting input coupled for receipt of the ECG reference waveform over input 12. Capacitor C4 and resistors R4-R9 cooperate to provide filtering and appropriate configuring of amplifier 60 to provide signal isolation.

Amplitude and offset conditioning circuitry 16 includes amplifier 62 having its inverting input coupled for receipt of the reference ECG waveform which inverts same. Resistors R12 and R13 provide an offset voltage to the noninverting input of amplifier 62. Circuitry 16 conditions the signal to provide a voltage level compatible with the particular bucket brigades 18 and 30 being utilized.

X bucket brigade 30 (FIG. 4B) is an analog delay device which accepts the output from amplifier 62 at its input and delays the generation of basically the same signal at its output for a given time period. The delay time period varies inversely with the frequency of the driving pulses from the X-clock 32 and proportionally with the number of buckets or stages in the brigade. Bucket brigade 30, in this embodiment, utilizes two clock inputs C1 and C2 and generates two output signals over lines labeled 01 and 02. X clock 32 provides two phase clock signals with a 50% duty cycle to inputs C1 and C2 of bucket brigade 30. FIG. 5 shows a timing chart of the two phase signals generated by X clock 32. These signals may be provided by a variety of known two phase clock generator circuits. In the preferred embodiment, X clock 32 uses a binary counter 64 (FIG. 4A) coupled to an externally generated master clock signal 65 of approximately 491.5 kilo-Hertz. Binary counter 64 is typical of counters known in the art and may be such as the one manufactured by National Semiconductor as component No. 4040. As is known in the art, binary counter 64 includes a plurality of output lines which are selectively activated for each incoming clock pulse to provide a coded output signal. By judicious choice of selecting particular ones of the output lines, one can develop a given clock frequency by gating these lines together as by AND gate 66. In such manner, AND gate 66 will provide output pulses at a particular frequency. The output of AND gate 66 is coupled to the input of a divide by two network comprised of cascaded flip flops 68 and 70. The flip flops 68 and 70 are coupled together in a known manner, with the Q and Q outputs of flip flop 70 providing the two phase clock signals to X bucket brigade 30 inputs C1 and C2. The frequency of these signals, in this embodiment, is about 7062 hertz.

The X bucket brigade 30, with driving clock frequencies at this level, provides a signal delay of about 35.7 milliseconds. The X bucket brigade 30 is one half of a dual 512 stage low noise BBD which, in this embodiment, is manufactured by Matsushita Electronics Corporation as component No. MN3010.

The two outputs 01 and 02 of X bucket brigade 30 are summed together at potentiometer R21. A resistive network using resistors R19 and R20 coupled to outputs 01 and 02, respectively, serve to attenuate noise created in bucket brigade 30 by the relatively high frequency clock pulses.

Additional filtering is accomplished by X low pass filter 34 which utilizes operational amplifier 72 configured as a two pole Bessel filter. Filter 34 passes signals having frequencies below 100 hertz and rejects frequencies higher than 100 hertz. Since the frequency components of the reference ECG waveform are generally at frequencies of less than 100 hertz, the waveform of interest will pass through filter 34, with spurious noise being cancelled therefrom.

The output of low pass filter 34 is coupled to the input of X signal buffer 36. Buffer 36 includes an amplifier 74 which amplifies the incoming signal according to the ratio of the feedback resistor R25 and input resistor R24 as is known in the art. Resistor divider circuitry comprised of resistors R26 and R27 coupled to the non-inverting input of amplifier 74 make up offset network 38 and serve to remove DC components of the waveform. Since the signal of interest is coupled to the inverting input of amplifier 74, the thus generated X waveform is re-inverted, i.e., having the same general orientation as the reference ECG input which was originally inverted by circuitry 16.

The Y waveform generator generally corresponds with the X waveform generator, with two notable exceptions. The Y clock 20 utilizes counter 76 whose output lines are selected in such a manner that the clock frequency ultimately generated at the output of flip flop 81 is different than that supplied by X clock 32. In this embodiment, the clock frequency generated by the Y clock 20 is about 6,607 Hertz, thus causing a delay in Y bucket brigade 18 of about 38.7 milliseconds. Another exception is that the Y signal buffer 26 amplifies the signal by a factor greater than that of the X buffer 36. It should also be noted that the output of Y low pass filter 24 includes a feedback line 84 which provides an inverted version of the Y signal to the summing and inverting amplifier 40 of the Z waveform generator.

Referring now to FIG. 4A, the feedback line 84 is coupled to a summing node 82 wherein the inverted version of the Y signal is summed with the ECG reference waveform from input buffer 14. The summed signal is coupled to the inverting input of amplifier 88. Offset circuitry 42 includes resistor divider network made up of resistors R35 and R36. The offset potential generated thereby is coupled to the non-inverting input of amplifier 88. The output of amplifier 88 is thus an inverted composite waveform made up of an inverted version of the Y waveform summed with the reference ECG waveform.

Buffer circuitry 44 utilizes operational amplifier 90 to condition the resulting signal to an appropriate voltage level compatible with the Z bucket brigade 46 (FIG. 4B).

Z bucket brigade 46 is similar to the X bucket brigade 30 and Y bucket brigade 18 but it only includes 128 stages as compared with the 512 stages of the X and Y bucket brigades. In this particular embodiment, Z bucket brigade 46 is component number MN3006 by Matsushita Electronics Corporation. The Z clock 48 includes counter 92 (FIG. 4A) configured such that the clock frequencies to bucket brigade 46 inputs C1 and C2 are at frequencies of about 2234 hertz. At this clock frequency and given this number of stages, bucket brigade 48 provides a delay of about 28.6 milliseconds.

The Z clock noise attenuator circuitry 50 and low pass filter network 52 operate identically with their X and Y counterparts.

FIG. 6 shows representative signals generated by the X, Y and Z waveform generators. The X-waveform shown is that substantially generated at the output of X signal buffer 36. The X waveform is characterized by a shape generally following the contour of the reference ECG input waveform but it is delayed about 35.7 milliseconds therefrom. The Y waveform shown in FIG. 6 is substantially that provided at the output of Y buffer 26. The Y waveform generally corresponds with the X waveform but its amplitude is greater than the X amplitude by a factor of about three and it is delayed therefrom about five milliseconds. The Z waveform is characterized by two successive opposing peaks. The negative or R segment peak is derived from the R segment of the ECG reference waveform and occurs, in this embodiment, approximately seven milliseconds before the X waveform peak or R segment. The positive Z waveform peak is derived from the R segment of the Y waveform which is fed back to the summing and inverting amplifier 40. Since the Y waveform has already been delayed via bucket brigade 18, the positive peak making up the S segment of the Z waveform will be delayed from its R segment, such delay being about 35-40 milliseconds in this embodiment. The amplitude of the Z waveform is about two-thirds that of the X waveform.

The X, Y, and Z signals simulate electrical activity within the human heart along three separate axes. While the specific delays and amplitudes for these waveforms have provided a standard VCG loop for a range of normal adults, they should be considered only as specific examples and not in a limiting sense. Different amplitudes and delays will produce different loops on the VCG which may similarly be used as a calibration reference. However, in order to produce loops which are similar to those made in normal use, the X, Y and Z waveforms must meet certain criteria. The Y waveform should be delayed from the X waveform and the Z waveform should be characterized by two successive opposing major peaks corresponding to the R and S segments, respectively.

Returning now to FIG. 4B, the amplitude adjustment circuitry 54 includes capacitor-resistor networks coupled to the outputs of the X, Y, and Z waveform generators. DC blocking capacitor C13 is disposed between the output of Y signal buffer 26 and two series connected resistors R46 and R47. Likewise, the series connected network of capacitor C14 and resistors R49 and R50 are coupled to the output of X signal buffer 36. The network comprised of capacitor C15 and resistors R53 and R54 are coupled to the output of Z low pass filter 52. The pairs of resistors in each of these networks serve to provide differential outputs for further adjusting the amplitudes of the generated waveforms.

A plurality of connectors are coupled to selected outputs of the amplitude adjustment circuitry 54. The connectors labeled LL, H, C, LA, RA, M, E, and RL provide outputs for the simulator device for connecting with corresponding FRANK lead system electrodes from a vectorcardiogram (VCG) machine. The LL connector includes a lead coupled between resistors R46 and R47. The H lead is connected to the LL lead through a variable resistor device R48. The LA connector includes a lead coupled between resistors R49 and R50. The C lead is connected to the LA lead through resistor R52. The RA lead is coupled to the LA lead through a variable resistor R51. The M lead is coupled between resistors R53 and R54. The E lead is coupled to the M lead through a variable resistor R55, with the RL lead being coupled to ground.

The following table lists the component numbers and values for the referenced components which comprise the electrical circuitry of the particular embodiment just described. This table merely describes typical values and choices for such components and should not be construed in a limiting sense.

FIG. 7 shows one example of an interconnection system for coupling the simulated waveforms to a VCG machine 96 which includes a plurality of FRANK lead system electrodes labeled LL', H', RL', M', E', C', LA', and RA'. A housing 98 includes suitable terminals thereon for making electrical connection to the electrodes. In this embodiment, housing 98 includes slots 100 for receiving electrodes 102, with spring loaded terminals 104 making the electrical connection to electrodes 102. Posts 106 provides alternative connectors for receiving jacks utilized with disposable type electrodes. The interconnection system shown in FIG. 7 is more fully described in U.S. patent application Ser. No. 93,086, now U.S. Pat. No. 4,267,576, entitled "Interconnection System For A Biological Waveform Simulator Device" by Power et al, filed concurrently herewith and having the same assignee as the present invention. This application is hereby incorporated by reference.

In operation, the electrodes of the VCG machine 96 are coupled to corresponding connectors on device 98 which supply simulated vectorcardiographic signals for testing the operability of the VCG machine 96. Therefore, the technician can observe the output of VCG machine 96 and readily determine whether it is operating properly.

It should be understood that while this invention was described in connection with specific examples thereof, no limitation is intended thereby except as defined in the appended claims.