Varying Two Phase Voltages in Dc to Three Phase Converter

The present invention relates to a method of generating a three-phase current from a dc voltage by dc-to-ac conversion, and to an arrangement for carrying out this method.

A three-phase current generated in this manner is preferably used in variable-frequency induction motors, whose advantageous behaviour is described, for example, in "AEG-Mitteilungen 55 (1965) 2", pages 118-123.

The generation of variable-frequency alternating voltages with inverters is described, for example, in "AEG-Mitteilungen 54 (1964) 1/2", pages 89-106. In that publication it is also stated that a virtually sinusoidal current can be achieved in an inductive load, such as an induction motor, by pulse-width modulation of the inverter. To attain this frequently desired sinusoidal current, sinusoidal ac voltages are generated whose sinusoidal difference is effective in the induction motor, and whose maximum amplitude is limited by the voltage of the dc voltage source.

The object of the invention is to provide a method of generating a three-phase current from a dc voltage by dc-to-ac conversion whereby a higher effective ac voltage can be obtained between the ac voltage outputs than is possible by the method referred to above, and an arrangement for performing the method of the invention.

This is achieved in that the method of the invention includes each one-sixth of the period the steps of maintaining a respective one of the three phases at a respective one of the voltages, and varying the voltages of the respective remaining two phases in substantially sinusoidal waveforms with a shift of 60 electrical degrees therebetween.

Further features of the method of the invention and of the arrangement for performing such method will become apparent from the remainder of the disclosure.

An advantage of the invention is that three-phase motors designed for a given rated voltage to be applied to their three terminals are supplied with virtually the full rated voltage without additional transformer means.

Another advantage is that during each sixth of a period of the ac voltage to be generated, only two variable waveforms need to be formed. From this it follows that if pulse-width modulation is used, only two pulse-width modulators are needed; if function values are stored in digital form, only two digital-to-analog converters are required.

A further advantage is that if the function values are stored, only values of one sixth of a period of a sine function need to be stored. The application of the method according to the invention thus leads to a considerable decrease in circuit complexity.

Embodiments of the invention will now be explained in more detail with reference to the accompanying drawings, in which:

FIG. 1 shows the waveforms of the three ac voltage referred to the potentials of the dc voltage source and generated in accordance with the invention;

FIG. 2 shows the waveform of the ac voltage corresponding to the voltage UR of FIG. 1 for a smaller effective value;

FIG. 3 is a schematic circuit diagram showing the essential parts of an inverter for carrying out the method according to the invention, and

FIG. 4 shows exemplary details of the inverter of FIG. 3.

FIG. 1 shows the waveforms of three ac voltages generated in accordance with the invention, which are designated UR, US, UT in accordance with the designations R, S, T commonly used in three-phase networks, and differ in phase from each other by one third of a period. The abscissae are divided into sixth-period sections so that one period is marked from 0 to 6. The maximum value of each of the ac voltages is the voltage Uo, which is equal to the dc voltage to be converted to an ac voltage, and the minimum value is zero and equal to the negative potential 0 of the dc voltage source. Shown by the example of UT, the ac voltages follow the following functions in the period sections indicated on the abscissa:

The ac voltage waveforms of UR and US differ from that of UT only in that they are shifted in time by two sixth-period sections. It can also be seen that in each sixth-period section, the sinusuidal slopes of those two portions of the waveform which do not have the amplitude Uo or 0 differ in phase from each other by 60 degrees.

This fact also permits an auxiliary representation which makes it easier to understand the invention: If the three ac voltages are represented in a vector triangle as is commonly used for three-phase power networks, one corner of the triangle is held at a potential for one sixth of a period, while the two vectors formed by the sides adjacent to these corners differ in phase from each other by 60 degrees. The difference between two ac voltage waveforms of the kind shown is a sinusoidal voltage waveform, as can be proved with the aid of know trigonometric transformations.

If the amplitude of the difference voltages is to be reduced, this can be done by reducing the dc voltage and using ac voltages with waveforms as shown in FIG. 1. However, this has the disadvantage that the dc voltage must be changed. This disadvantage is avoided by a curve as shown in FIG. 2, which refers to the voltage UR by way of example. It follows the waveforms shown in FIG. 1 but has a smaller effective value. To obtain this waveform, only those sixth-period sections need to be changed in amplitude which already have a varying function value within the period section. If all three ac voltages UR, US, UT are generated according to FIG. 2, correspondingly smaller effective sinusoidal difference voltages are again obtained.

FIG. 3 shows an embodiment of an inverter whose controllable elements SR 1, SR 2, SS1, SS2, ST1, and ST2 are switches which are controlled by pulse-width-modulated signals, and each of which is bypassed by one of the diodes D1 to D6. The three ac voltage outputs R, S, T are connected to the terminals O and Uo of the dc voltage source B via one of the switches each. Connected to the ac voltage outputs R, S, T are the delta-connected windings of a three-phase induction motor AM, in which the difference voltages of the ac voltage outputs R, S, T are effective.

The switches SR1 to ST2 are controlled by a control unit C in conjunction with the function values stored in a digital function-value memory FM, which are converted in pulse-width modulators PM1 and PM2 into signals suitable for controlling the switches SR1 to ST2 and are passed through an allocation logic L to the switches.

The pulse-width modulation of the voltages at the ac voltage outputs R, S, T is chosen so that the average values give the voltage waveforms shown in FIG. 1.

As a result of the low-pass action of the motor inductances, a sinusoidal current is then formed in the motor AM which approximately corresponds to the difference voltages of the voltages of FIG. 1. The digital memory FM holds a large number of values of the function sin (.alpha.) in equidistant argument steps in the range of 30 to 90 degrees. During each sixth of a period of the ac voltage, one function value after the other, beginning with values for 30 degrees and ending with values for 90 degrees, is delivered to the pulse-width modulator PM1; reversely, one function value after the other, beginning with values for 90 degrees and ending with values for 30 degrees, is delivered to the pulse-width modulator PM2 in simultaneous or alternate steps. By suitable allocation of the output signals of the pulse-width modulators PM1 and PM2 to the switches SR1 to ST2, the required voltage waveforms are achieved at the outputs R, S, T. This allocation is performed under the control of the control unit C by the allocation circuit L between the pulse-width modulators and the switches.

Since function values for different effective values A are stored in the memory FM, the function values belonging to the effective value are read out by addressing the memory with a signal A.

The control unit C is fed with a clock signal f1.times.n, where f1 corresponds to the required frequency of the ac voltages at the outputs R, S, T, and n is the number of function-value steps or a multiple thereof during a period.

FIG. 4 shows exemplary details of the embodiment of FIG. 3. The digital memory FM, labeled "PROM1", is fed with two addresses A1 and A2 to cause the function values Z1, Z2 to be read from the memory. The address A1 selects the function values belonging to a given effective value A, and the address A2 selects from these function values the value belonging to a given argument. The address A2 is generated by the control unit C, which is composed of an angle decoder PROM2, a counter 1, a flip-flop D-FF, a counter 4, and a NOT element U. The control unit is fed with the frequency signal f1, corresponding to the ac voltages to be generated, multiplied by 96, and with a system clock f2, having a frequency which is a multiple of f1.times.96. These two frequency signals f1.times.96 and f2 are independent and therefore asynchronous, and in the flip-flop D-FF the edges of the frequency signal f1.times.96 are synchronized with the edges of the system clock, whereby the frequency signal f1'.times.96 is obtained. This frequency signal f1'.times.96 is applied to a counter 1, which divides it by 96, so that its count repeats itself periodically with the frequency f1, the count cycle corresponding to 360 degrees, and the counts being delivered as addresses Y1, Y2, Y3 and A3 in the binary code.

Through the factor n=96, the 60-degree sections are specified by the three most significant bits Y1, Y2 and Y3. For addressing the function values within the respective 60-degree section, the least significant bits (bits 4 to 7) obtained with the factor n=96 are applied to the angle decoder PROM2, which assigns two addresses A2 to each address A3 under control of the clock f2, such that for each address A3, the function values Z1=A.times.sin (30.degree. +.alpha.) and Z2=A.times.sin (90.degree. -.alpha.) are read out of the function-value memory FM under control of f2. The system clock f2 also causes the function values Z1 and Z2 to be transferred in the correct sequence to the intermediate memories D-Reg 1 and D-Reg 2; to this end, it is applied to D-Reg 1 via the NOT element U. The intermediate memory D-Reg 1, a counter 2, and a flip-flop FF 1 form a first pulse-width modulator PM1, and D-Reg 2, a counter 3, and a flip-flop FF2 form a second pulse-width modulator PM2. The counters 2 and 3 are programmed by the applied function values Z1 and Z2, respectively, and count the pulses of the system clock f2. The counter 4 of the control unit divides the system clock f2 by the maximum count of the counters 2 and 3. The output signal of the counter 4 starts the counters 2 and 3 and puts the flip-flops FF1 and FF2 in a first defined condition. After reaching the programmed count, the counters 2 and 3 provide a stop signal which puts the flip-flops FF1 and FF2 in a second condition. The time between the start signal and the stop signal is a measure of the pulse width and can be obtained as pulse signals X1 and X2 from the outputs of the flip-flops FF1 and FF2. These pulse signals X1 and X2 are used to control the switches SR1 to ST2 of the inverter via an allocation logic PROM3 and driver stages T1, T2, T3.

The allocation logic PROM3 and the driver stages T1, T2, T3 form the allocation logic L of FIG. 3. The allocation logic PROM3 is controlled by the addresses Y1 to Y3 formed by the counter 1. This address, referred to the period of f1, changes in 60-degree steps.