US 4,350,976 AGrant
Charge-Transfer Coded-Voltage Generator for Use in Analog-Digital Coders and Decoders
Issue Date:1982-09-21
•9 Claims
•2 Drawing Sheets
Abstract
Successive two-trip traversals of charges between gates G.sub.0 and G.sub.2 make it possible to obtain beneath gates G.sub.1 and G.sub.2 quantities of charges equal to Q.sub.R, Q.sub.R /2, Q.sub.R /2.sup.2 . . . Q.sub.R /2.sup.i. A readout device for reading charges and connected to gates G.sub.2 and G.sub.4 generates voltages V.sub.R and V.sub.Ri =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i which are compared with a voltage sample V.sub.x to be coded in order to determine by successive approximations the coefficients a.sub.0 . . . a.sub.n which are equal to 0 or to 1 such that V.sub.x =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.n .multidot.V.sub.R /2.sup.n. Depending on the value of a.sub.i, each quantity of charges Q.sub.R /2.sup.i stored beneath gate G.sub.1 is removed beneath diode D.sub.e or stored beneath gate G.sub.3 and then transferred beneath gate G.sub.4.
Metadata
Assignee
- Thomson-CSF
Inventors
- Roger Benoit-Gonin
- Jean L. Berger
- Jean L. Coutures
Application Information
Application Number:US 2151340
Filing Date:1980-12-10
Priority Date:1979-12-27
Art Unit:236
Classifications
IPC:
H03K 1302
Field of Search:
340364307357347 AD;347 DA;347 M862221 D24
Patent Drawings (2 sheets)
Description
This invention relates to charge-transfer coded-voltage generators which are used in analog-digital coders and decoders.
A well-known practice in the prior art consists in determining by successive approximations the coefficients a.sub.o, a.sub.1 . . . a.sub.i . . . a.sub.n which are equal to 0 or to 1 and make it possible to write an unknown voltage V.sub.x in the form:
where V.sub.R is a reference voltage.
To this end,
V.sub.x is first compared with V.sub.R. If V.sub.x is smaller than V.sub.R, then a.sub.o is accordingly equal to 0 whereas a.sub.o is otherwise equal to 1;
V.sub.X is then compared with V.sub.R1 =a.sub.o V.sub.R +V.sub.R /2. If V.sub.x is smaller than V.sub.R1, then a.sub.1 is in that case equal to 0 but is otherwise equal to 1;
V.sub.x is then compared with V.sub.R2 =a.sub.o V.sub.R +a.sub.1 .multidot.V.sub.R /2+V.sub.R /4.
If V.sub.x is smaller than V.sub.R2, then a.sub.2 is in that case equal to 0 but otherwise equal to 1;
and so on until all the coefficients a.sub.o . . . a.sub.n have been determined.
It can therefore be noted that, in order to determine the coefficients by successive approximations, it is necessary to utilize voltages V.sub.R and
with i=1 . . . n.
The voltages V.sub.R and V.sub.Ri can be generated by networks of resistors or capacitors whose values vary in powers of 2. This is the case, for example, in an article by Messrs. Mc Creary and Gray published in the IEEE Journal of Solid-State Circuits, volume SC 10, No. 6, December 1975, pages 371 to 385.
The aforementioned networks of resistors or capacitors often have the disadvantage of being cumbersome and lacking in accuracy. Moreover, in the case of some of these networks, it sometimes proves impossible during approximation to produce a value of V.sub.Ri directly from V.sub.R(i-1) and it is necessary to resume a new sequence of generation of voltages in order to obtain the correct value of V.sub.Ri. Thus, in order to generate the n values of V.sub.Ri which are necessary for the determination of n coefficients, it may be necessary to carry out n.multidot.(n+1) voltage redistributions.
Moreover, French patent application No. 77,02067 published under U.S. Pat. No. 2,343,369 in the name of I.B.M. disclosed a device which utilizes the method of redistribution of charges; only n charge redistributions are necessary in order to determine the n coefficients.
Said device comprises a generator for producing quantities of charges Q.sub.R /2, Q.sub.R 2.sup.2 . . . Q.sub.R /2.sup.n. Two charge storage regions are provided:
one region in which the quantity of charges Q.sub.x corresponding to the unknown voltage V.sub.x is stored;
the other region which receives Q.sub.R /2.
A comparison is made between Q.sub.x and Q.sub.R /2:
if Q.sub.x >Q.sub.R /2, then a.sub.o =1 and Q.sub.R /2.sup.2 is switched towards the region which contains Q.sub.R /2;
if Q.sub.x <Q.sub.R /2, then a.sub.o =0 and Q.sub.R /2.sup.2 is switched towards the region which contains Q.sub.x ; and so on until a.sub.n is obtained, each quantity of charges Q.sub.R /2.sup.i being switched towards either one region or the other as a function of the value of a.sub.i-1.
The coded-voltage generator in accordance with the present invention also utilizes the method of charge redistribution but its structure is completely different from that of the known device described in the foregoing.
The generator in accordance with the invention has all the advantages of the device described earlier from the point of view of small overall size and speed in particular. Moreover, the generator provides a higher degree of precision than said device.
In said device, the quantities of charges Q.sub.R /2, Q.sub.R /2.sup.2 . . . Q.sub.R /2.sup.n are obtained (as shown in FIGS. 3 to 5) by making use of two storage electrodes separated by a transfer electrode. A quantity of charges Q.sub.R is stored beneath one of the storage electrodes. Redistribution of charges beneath the two storage electrodes followed by separation of the charges by the transfer electrode makes it possible to obtain Q.sub.R /2 beneath each storage electrode. The charges beneath one of the storage electrodes are removed and the next step consists in carrying out a redistribution followed by a separation which makes it possible to obtain Q.sub.R /4, and so on.
Distribution of charges at the time of division by 2 is carried out in a more random manner than in our invention and a lower degree of accuracy is therefore achieved.
The coded-voltage generator in accordance with the invention makes it possible to produce:
either the voltages V.sub.R, V.sub.Ri =a.sub.o V.sub.R +a.sub.1 .multidot.V.sub.R /2+a.sub.2 V.sub.R /2.sup.2 + . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i with i=1 . . . n, in the case in which an unknown voltage V.sub.x is available and in which it is desired to determine by successive approximations, by comparing V.sub.R and V.sub.Ri with V.sub.x, the coefficients a.sub.o . . . a.sub.n which are equal to 0 or to 1 and such that V.sub.x =a.sub.o V.sub.R +a.sub.1 V.sub.R /2+ . . . +a.sub.i .multidot.V.sub.R /2.sup.i + . . . +a.sub.n .multidot.V.sub.R /2.sup.n ;
or the voltage V.sub.x =a.sub.o V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.i .multidot.V.sub.R /2.sup.i . . . +a.sub.n .multidot.V.sub.R /2.sup.n, in the case in which the coefficients a.sub.o . . . a.sub.n are known and in which V.sub.x is not available.
The generator in accordance with the invention is constituted by a charge-transfer device comprising an alternate arrangement of storage gates and transfer gates together with:
a diode D.sub.e placed at one end of the active zone in which transfer and storage of charges takes place, the function of said diode being to inject a reference quantity of charges 2Q.sub.R at the beginning of processing of each sample V.sub.x or of each series a.sub.o . . . a.sub.n as well as to effect removal of surplus charges during the processing operation;
an insulating diffusion which divides into two equal parts the charges originating from a storage gate G.sub.o located near the diode D.sub.e and which divides the active zone after G.sub.o into two parallel channels;
in one channel, a storage gate G.sub.2 beneath which the quantities of charges Q.sub.R, Q.sub.R /2, . . . Q.sub.R /2.sup.i . . . are stored by successive two-trip traversals between G.sub.o, G.sub.2 ;
in the other channel, three storage gates G.sub.1, G.sub.3 and G.sub.4, the quantity of charges Q.sub.R /2.sup.i stored beneath the gate G.sub.1 and originating from the gate G.sub.o being transferred beneath said gate G.sub.o and then removed beneath the diode D.sub.e when a.sub.i is zero in respect of i=0 . . . n and being transferred beneath the gate G.sub.3 when a.sub.i is equal to 1;
when the coefficients a.sub.o . . . a.sub.n are unknown, a charge-reading device connected to gates G.sub.2 and G.sub.4 and adapted to generate the reference voltage V.sub.R at the time of transfer of the quantity of charges Q.sub.R beneath the gate G.sub.2, thus permitting determination of a.sub.o by comparison of the voltage V.sub.R with the voltage V.sub.x, then to generate V.sub.R1 =a.sub.o V.sub.R +V.sub.R /2 at the time of transfer of the quantity Q.sub.R /2 beneath the gate G.sub.2 and, in the event that a.sub.o =1, at the time of transfer of Q.sub.R originating from gate G.sub.3 to the gate G.sub.4, thus permitting determination of a.sub.1 by comparison of the voltage V.sub.R1 with the voltage V.sub.x, and so on until generation of V.sub.Rn and determination of a.sub.n, or,
when the coefficients a.sub.o . . . a.sub.n are known, a charge-reading device connected to the gate G.sub.4 for generating the voltage V.sub.x by transfer of charges from gate G.sub.3 to gate G.sub.4 when the n coefficients of V.sub.x have been processed.
Moreoever, in a preferred embodiment of the generator in accordance with the invention, in the case in which the voltage V.sub.x is available and in which the coefficients a.sub.o . . . a.sub.n are unknown, it is possible to dispense with any need for an external source of reference voltage by converting the voltage V.sub.x to be coded to a quantity of charges Q.sub.x by means of a charge injection device which is identical with the device employed for generating 2Q.sub.R. Reading of the voltage Q.sub.x is then carried out so as to obtain a voltage V.sub.Lx by means of a device which is identical with the device employed for reading the charges beneath the gates G.sub.2 and G.sub.4. The advantage of conversion followed by reading of Q.sub.x lies in comparison of the signals V.sub.Lx and V.sub.Ri having the same direct-current component and the same scale of amplitude.
The advantage offered by the generator in accordance with the invention lies in the fact that it can be employed in analog-digital coders or decoders as described in an article by Messrs. Gray and Hodges entitled "All MOS analogic-digital conversion techniques" and published in "IEEE Transactions on circuits and systems," volume CAS-25, No. 7, July 78, pages 482 to 489.
These and other features of the invention will be more apparent to those skilled in the art upon consideration of the following description and accompanying drawings, wherein:
FIG. 1 is a top view of the charge-transfer device constituting the generator in accordance with the invention and the circuit diagram of the device consisting of MOS transistors, capacitors and resistors which is associated to the charge-transfer device;
FIG. 2a is a sectional view of the charge-injection device of the generator in accordance with the invention and the surface potentials beneath said device at a given instant;
FIG. 2b shows the progressive variation in surface potential .phi..sub.S as a function of the voltage V.sub.G applied to two gates T.sub.o and G.sub.E of the injection device;
FIG. 3 is a diagram showing the diffused regions within the substrate beneath one of the gates G.sub.o of the charge-transfer device which constitutes the generator;
FIG. 4 is a diagram showing the arrangement of the generator in accordance with the invention when the voltage V.sub.x to be coded is converted to charges which are read before making a comparison with the voltages V.sub.Ri.
In the different figures, the same references designate the same elements but the dimensions and proportions of the different elements have not been observed for the sake of enhanced clarity.
FIG. 1 shows a top view of the charge-transfer device which constitutes the generator in accordance with the invention and the circuit diagram of the device which is constituted by MOS transistors, capacitors and resistors and which is associated to the charge-transfer device.
Said charge-transfer device is preferentially of the type known as a charge-coupled device (CCD).
Charge transfer can be carried out either at the surface or in volume.
The active region of the semiconductor substrate in which transfer and storage of charges take place is located within the dashed outline 1. Outside the region defined by said outline, overdoping of the substrate has the effect of raising the inversion threshold and thus prevents any storage of charges.
At one end of the active zone, namely the end corresponding to the left-hand side of the figure, provision is made for a diode D.sub.e which serves to introduce a reference charge 2Q.sub.R beneath a storage gate G.sub.e by means of a transfer gate T.sub.o. The diode D.sub.e and the gates T.sub.o and G.sub.e constitute the device for injecting the reference charge 2Q.sub.R within the generator.
The diode D.sub.e is also employed for removal of surplus charges during operation of the generator.
The gate G.sub.e is followed by a transfer gate T.sub.1 and by a storage gate G.sub.o.
Beneath the gate G.sub.o, an insulating diffusion extends to one-half of the width of the active charge-transfer region in order to effect a pre-division of the charge stored beneath the gate G.sub.o into two equal quantities of charges. This insulating diffusion divides the active region downstream of the gate G.sub.o into two parallel channels which usually have the same width. Thus two quantities of charges equal to one-half of the charge stored beneath the gate G.sub.o will be transferred beneath the storage gates G.sub.1 and G.sub.2 which are located in each channel downstream of the gate G.sub.o and separated from this latter by the transfer gates T.sub.2 and T.sub.3. This division of a quantity of charges by a diffused region is already known in the prior art.
One of the channels therefore terminates in the storage gate G.sub.2 whilst the other channel is provided downstream of the storage gate G.sub.1 with two storage gates G.sub.3 and G.sub.4 and three transfer gates, namely the transfer gate T.sub.4 between the storage gates G.sub.1 and G.sub.3, the transfer gate T.sub.5 between the storage gates G.sub.3 and G.sub.4, and the transfer gate T.sub.6 between the storage gate G.sub.4 and a collecting diode D.sub.c. The collecting diode D.sub.c which terminates the channel is connected to a direct-current voltage V.sub.DD and permits removal of the charges at the end of processing of a sample V.sub.x or of a series a.sub.o . . . a.sub.n.
Depending on whether V.sub.x or coefficients a.sub.o . . . a.sub.n are available, the gates G.sub.2 and G.sub.4 or the gate G.sub.4 alone are connected at a point P to a charge-reading device which serves to carry out nondestructive readout of the charges stored beneath the gates G.sub.2 and G.sub.4 or beneath the gate G.sub.4 alone.
Said reading device can be a direct-current charge-reading device of a type already known in the prior art such as, for example, the device described in French patent application No. 77 13857 published under U.S. Pat. No. 2,389,899 in the name of Thomson-CSF.
The potential of the point P is maintained constant at the time of arrival of the charges by means of an MOS transistor Q.sub.2 which is connected between the point P and a point A. The transistor Q.sub.2 controlled by a periodic clock signal .phi..sub.2 then becomes biased in the saturating mode. The current which passes through the transistor Q.sub.2 at the time of inflow of charges is integrated within a capacitor C.sub.A connected between the point A and ground.
The voltage at the point A is read by an MOS transistor or TMOS Q.sub.5 mounted as an emitter-follower, the gate of which is connected to the point A and one of the electrodes of which is connected to a voltage V.sub.DD whilst the other electrode delivers the read voltage to the terminals of a resistor R.sub.S. The TMOS Q.sub.5 can be replaced for reading the voltage at the point A by an operational amplifier having a gain of 1.
Between the point A and a point B, there is also connected a TMOS Q.sub.3, the gate of which is connected to B. A capacitor C.sub.B is connected between the point B and the clock signal .phi..sub.2. Finally, a TMOS Q.sub.4 is connected between the point B and the voltage V.sub.DD, the gate of the transistor Q.sub.4 being also connected to V.sub.DD.
Finally, depending on whether the voltage V.sub.x or the coefficients a.sub.o . . . a.sub.n are available, a TMOS transistor Q.sub.1 is connected between the gates G.sub.2 and G.sub.4 and ground or between the gate G.sub.2 alone and ground. The TMOS transistor Q.sub.1 is controlled by a periodic clock signal .phi..sub.1 and causes the gates to which said transistor is connected to be reset to zero when it is triggered into conduction.
We shall now study the operation of the generator shown in FIG. 1, in which the point P of the reading device and the TMOS transistor Q.sub.1 are connected to the gates G.sub.2 and G.sub.4. In the example under consideration, it is therefore assumed that samples V.sub.x are available and that it is desired to determine the coefficients a.sub.o . . . a.sub.n by generating the voltages V.sub.R and V.sub.Ri.
Five sequences can be distinguished in this operation:
Sequence t.sub.o : a charge 2Q.sub.R is introduced beneath the gate G.sub.e in a known manner and in accordance with the so-called "fill and spill" method. To this end, the diode D.sub.e is successively brought to a low level which permits transfer of charges from the diode D.sub.e beneath the gates T.sub.o and G.sub.e, then to a high level which makes it possible to store a given quantity of charge 2Q.sub.R beneath the gate G.sub.e.
The gates T.sub.o and G.sub.e receive the same voltage V.sub.GE as shown in FIG. 2a which is a sectional view of the device for injection of charges, so as the surface potentials when the charge 2Q.sub.R is stored beneath the gate G.sub.e.
The reference quantity of charges 2Q.sub.R has first-order stability or, in other words, is independent of the variations in voltage V.sub.GE applied to gates T.sub.o and G.sub.e if the surface potential curves as a function of the voltage of this pair of gates are parallel. To this end, the threshold voltages beneath the gates T.sub.o and G.sub.e are adjusted by means of an implantation 5 beneath the gate T.sub.o so as to ensure that the barrier height .DELTA.Q.sub.S has first-order independence with respect to V.sub.GE. FIG. 2b shows the curves obtained in respect of the gates T.sub.o and G.sub.e.
The other transfer electrodes of the generator (gates T.sub.1 . . . T.sub.6) can be formed on an overthickness of oxide as shown in FIG. 2a in the case of the gate T.sub.1. As in the case of the gate T.sub.o, said transfer electrodes or gates may be formed by implantation or in any other known manner.
Sequence t.sub.1 : the charge 2Q.sub.R is transferred beneath the gate G.sub.o. The clock signal .phi..sub.2 is at the high level V.sub..phi., with the result that the point B which was initially pre-loaded by transistor Q.sub.4 at V.sub.DD -V.sub.T changes to V.sub.B =V.sub.DD -V.sub.T +V.sub..phi. and the point A changes to V.sub.B -V.sub.T, where V.sub.T is the threshold voltage which is common to the TMOS transistors Q.sub.2, Q.sub.3 and Q.sub.4. The point P and the gates G.sub.2 and G.sub.4 are thus pre-loaded at V.sub..phi. -V.sub.T and the TMOS transistor Q.sub.2 is biased in the saturating mode since V.sub.AO =V.sub.B -V.sub.T >V.sub..phi. -V.sub.T.
Sequence t.sub.2 : the charge 2Q.sub.R which is present beneath the gate G.sub.o is transferred to the gates G.sub.1 and G.sub.2 by resetting the gate G.sub.o to zero since the gates T.sub.2 and T.sub.3 are at intermediate fixed potentials. The charges are therefore transferred over the potential barriers induced beneath T.sub.2 and T.sub.3, thereby eliminating the parasites which could arise from zero-resetting of the transfer gates T.sub.2 and T.sub.3 on the read gates G.sub.1 and G.sub.2.
The charge Q.sub.R is therefore available beneath the gate G.sub.1 and the charge Q.sub.R is available beneath the gate G.sub.2 on account of the charge distribution produced by the insulating diffusion.
During the same time interval, the gates T.sub.4 and G.sub.3 are reset to zero and the gate T.sub.5 is reset at an intermediate fixed potential, which corresponds to transfer of any subsequent charge from the gate G.sub.3 to the gate G.sub.4.
During the first sequence t.sub.2, there are no charges to be transferred from gate G.sub.3 to gate G.sub.4 and the arrival of Q.sub.R beneath gate G.sub.2 alone causes current to flow through the transistor Q.sub.2 which maintains the potential at the point P at V.sub..phi. -V.sub.T whereas the potential at A changes from V.sub.AO to V.sub.A =V.sub.AO -Q.sub.R /C.sub.A =V.sub.AO -V.sub.R.
By means of the TMOS transistor Q.sub.5 mounted as an emitter-follower, a voltage V.sub.S proportional to V.sub.R =Q.sub.R /C.sub.A is therefore available. The voltage V.sub.R is then compared in known manner with the sample V.sub.x to be coded and the value of a.sub.o is deduced therefrom:
Sequence t.sub.3 : depending on the value of a.sub.o, the charge transfers are different:
if a.sub.o =0, the charge Q.sub.R is transferred from the gate G.sub.1 beneath the gate G.sub.o and then beneath the gate G.sub.e and is finally removed by the diode D.sub.e ;
if a.sub.o =1, the charge Q.sub.R is transferred from gate G.sub.1 beneath gate G.sub.3. The charge a.sub.o Q.sub.R is therefore stored beneath gate G.sub.3 ;
Sequence t.sub.4 : the transition of the clock signal .phi..sub.1 to the high level whilst the clock signal .phi..sub.2 shifts to the low level triggers the TMOS transistor Q.sub.1 into conduction, initiates resetting of the gate G.sub.2 to zero and therefore the transfer of Q.sub.R from gate G.sub.2 to gate G.sub.o and resetting of gate G.sub.4 to zero, and consequently the transfer of any subsequent charge from gate G.sub.4 to gate G.sub.3.
The different sequences are then resumed from the sequence t.sub.1 but the sequence t.sub.o does not take place since the charge Q.sub.R is available beneath gate G.sub.o.
We thus have successively:
sequence t.sub.1 : pre-loading of points A and P;
sequence t.sub.2 :
transfer of Q.sub.R /2 beneath gate G.sub.2 and of Q.sub.R /2 beneath gate G.sub.1 ;
transfer of a.sub.o Q.sub.R from gate G.sub.3 to gate G.sub.4 ;
reading of a.sub.o Q.sub.R +Q.sub.R /2;
comparison of V.sub.R 1=(a.sub.o .multidot.Q.sub.R +Q.sub.R /2).multidot.C.sub.A with V.sub.x and determination of a.sub.1.
sequence t.sub.3 :
if a.sub.1 =0, removal of Q.sub.R /2 from gate G.sub.1 to gates G.sub.2, G.sub.e and diode D.sub.e ;
if a.sub.1 =1, transfer of Q.sub.R /2 from gate G.sub.1 beneath gate G.sub.3.
sequence t.sub.4 :
transfer of Q.sub.R /2 from gate G.sub.2 to gate G.sub.o ;
transfer of a.sub.o Q.sub.R from gate G.sub.4 to gate G.sub.3. The charge a.sub.o Q.sub.R +a.sub.1 Q.sub.R /2 is accordingly present beneath gate G.sub.3.
The different sequences are then resumed from t.sub.1 until determination of a.sub.n. For the determination of each coefficient a.sub.i, it is therefore necessary to have a pre-load sequence t.sub.1 and three successive transfer sequences t.sub.2, t.sub.3, t.sub.4, a certain number of which therefore involve a plurality of simultaneous transfers.
For the determination of n coefficients, it is therefore necessary to have 4 n successive sequences, whereupon the generator is initialized for coding the following sample V.sub.x. There then takes place a removal of Q.sub.R /2.sup.n from gate G.sub.2 to gates G.sub.o and G.sub.e and diode D.sub.e and for removal of the charges stored beneath gate G.sub.4 to the diode D.sub.c.
The surface area of the gates G.sub.1 and G.sub.2 is preferably equal to one-half of the area of gate G.sub.o. Gates G.sub.3 and G.sub.4 preferably have a surface area equal to that of gate G.sub.o. It is worthy of note that, when all the coefficients are equal to 1, the quantity of charges to be stored beneath gates G.sub.3 and G.sub.4 is close to 2Q.sub.R since it is equal to Q.sub.Rn =2Q.sub.R (1-1/2.sup.n).
During the sequence t.sub.4, the charge Q.sub.R /2.sup.i is transferred from gate G.sub.2 to gate G.sub.o. Before said charge can again be transferred beneath the gates G.sub.1 and G.sub.2 in order to divide said charge by 2, it is essential to ensure that the charge has had time to be distributed beneath gate G.sub.o in a uniform manner. In actual fact, in order to obtain sufficient accuracy of charge distribution, the gate G.sub.o employed in practice is of relatively substantial width at right angles to the direction of charge transfer, said width being of the order of 300 .mu.m, for example. The time of homogeneous distribution of a charge beneath an electrode of this width is of relatively long duration. In order to reduce this distribution time to an appreciable extent, a diffused region of the type opposite to that of the semiconductor substrate 1 is provided over the entire width of the electrode G.sub.o.
In FIG. 3, the reference numeral 2 designates the diffused region beneath the electrode G.sub.o which establishes high conduction from one end of the electrode to the other, thus facilitating transfer of charges and uniform distribution of these latter over the entire surface of said electrode G.sub.o.
In order to dispense with the need for any external supply of reference voltage, the voltage V.sub.x to be coded can be converted to a quantity of charges Q.sub.x by means of an injection device which is identical with the device employed for generating 2Q.sub.R.
This device is illustrated in FIG. 4 and comprises a diode D.sub.e ' followed by a transfer gate T.sub.o ' which is connected to V.sub.Ge and by a storage gate G.sub.e ' which is connected to V.sub.x.
Reading of Q.sub.x is then carried out on a storage gate G.sub.o ' which is adjacent to the injection device by means of a readout device which is identical with the device employed for reading the charges beneath the gates G.sub.2 and G.sub.4. There is thus obtained a voltage V.sub.A '=V.sub.AO -Q.sub.x /C.sub.A to be compared with the voltage V.sub.Ai =V.sub.AO -Q.sub.Ri /C.sub.A.
The advantage of conversion and then reading of Q.sub.x lies in the fact that the signals V.sub.A ' and V.sub.Ai which are obtained are wholly comparable in regard to their direct-current component and their scale of amplitude.
Generation of Q.sub.x must be performed for determination of each coefficient a.sub.i. Injection beneath the gate G.sub.e ' takes place during the sequence t.sub.1 ; transfer and readout beneath the gate G.sub.o ' take place during the sequence t.sub.2 ; removal beneath a diode D.sub.c ' connected to V.sub.DD and separated from the gate G.sub.o ' by a transfer gate T.sub.2 ' takes place during the sequence t.sub.3. Provision must therefore be made for a voltage V.sub.x which is sampled and maintained.
The surface area of the storage gate G.sub.e ' is preferably chosen so as to be identical with the area of the storage gate G.sub.e. The maximum charge 2Q.sub.R which can be processed by the generator is accordingly introduced beneath the gate G.sub.e ' when V.sub.x is equal to V.sub.GE.
In order to obtain a high degree of accuracy in respect of the minimum charge which can be injected beneath the gate G.sub.e ' and subsequently read, a constant voltage V.sub.o is superimposed on the voltage V.sub.x.
The voltage swing in the gate G.sub.e ' accordingly takes place within the range of V.sub.o to V.sub.o +V.sub.GE. The quantities of charges beneath the gate G.sub.e ' therefore vary between Q.sub.o and Q.sub.o +2Q.sub.R.
In order that a comparison between V.sub.A, and V.sub.Ai may always be made, a quantity of charges Q.sub.o is added to the charges which arrive beneath gates G.sub.2 and G.sub.4. To this end, an additional storage gate G.sub.o " is connected to the point P as shown diagrammatically in FIG. 4. Accordingly, a quantity of charges Q.sub.o is injected and then transferred beneath the gate G.sub.o " by means of a device which is identical with the device employed for generating and transferring Q.sub.o +Q.sub.x. The quantities of charges Q.sub.o +Q.sub.x and Q.sub.o +Q.sub.Ri are read by readout devices 3 and a comparator 4 makes a comparison between the signals
and
The devices for injection of 2Q.sub.R, Q.sub.x +Q.sub.o and Q.sub.o must be sufficiently close together on the semiconductor substrate to prevent variations in technological parameters from one device to the next in regard to threshold voltage, oxide thickness and so on. Then these precautions have been taken, it is possible to avoid the use of an external reference-voltage supply.
Finally, when the voltage V.sub.x to be coded is negative, the comparison between V.sub.x and the voltages V.sub.R, V.sub.Ri takes place after the voltage V.sub.x or the voltages V.sub.R, V.sub.Ri have been reversed in sign by a differential stage.
We shall now study the operation of the generator in accordance with the invention when the point P of the readout device is connected only to the gate G.sub.4 and when the TMOS transistor Q.sub.1 is connected only to the gate G.sub.2. This is therefore a case in which the coefficients a.sub.o . . . a.sub.n are known and in which it is desired to generate V.sub.x. A single charge readout is necessary in this case and is carried out by transfer from gate G.sub.3 to gate G.sub.4 whereas the quantity of charges a.sub.o Q.sub.R +a.sub.1 Q.sub.R /2+ . . . +a.sub.n Q.sub.R /2.sup.n has been stored beneath gate G.sub.3.
Consideration will be given hereinafter to the differences observed during the sequences t.sub.1 to t.sub.4 described earlier while noting that the sequence t.sub.o remains unchanged.
Sequence t.sub.1 : this is the sequence involving pre-loading of points A and P in order to permit reading of the charges. In this case, a single readout operation is performed when all the coefficients a.sub.o . . . a.sub.n have been processed. In contrast to the events which occurred in the previous instance, the sequence t.sub.1 takes place only once for processing a series a.sub.o . . . a.sub.n as is the case with the sequence t.sub.o. The period of the clock signal .phi..sub.2 must therefore be modified;
Sequence t.sub.2 : the transfer of Q.sub.R and then Q.sub.R /2, Q.sub.R /2.sup.2 . . . beneath gates G.sub.1 and G.sub.2 still takes place but is no longer followed each time by a transfer from gate G.sub.3 to gate G.sub.4, reading of charges beneath gates G.sub.2 and G.sub.4 and comparison of the readout voltage V.sub.Ri with V.sub.x in order to determine a.sub.i. Transfer from gate G.sub.3 to gate G.sub.4 and reading beneath gate G.sub.4 take place only once when all the values of the coefficients a.sub.i have been processed;
Sequence t.sub.3 : this sequence remains unmodified and removal of charges from gate G.sub.3 to diode D.sub.e or transfer from gate G.sub.3 to gate G.sub.4 still takes place, depending on the value of a.sub.i. The charge a.sub.o Q.sub.R +a.sub.1 Q.sub.R /2+ . . . +a.sub.i .multidot.Q.sub.R /2.sup.i is therefore present beneath gate G.sub.3 ;
Sequence t.sub.4 : the gate G.sub.2 alone is reset to zero by the TMOS transistor Q.sub.1.
It is readily apparent that the entire generator in accordance with the invention may be integrated on one and the same semiconductor substrate.
Claims
What is claimed is:
1. A charge-transfer coded-voltage generator for generating the voltages .multidot.V.sub.R /2.sup.2 + . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i, where V.sub.R is a reference voltage and where i=1 . . . n and in which said voltages make it possible by comparison with a voltage V.sub.x to determine by successive approximations the coefficients a.sub.o . . . a.sub.n which are equal to 0 or to 1 and such that V.sub.x =a.sub.o V.sub.R +a.sub.1 .multidot.V.sub.R /2+a.sub.2 .multidot.V.sub.R /2.sup.2 . . . +a.sub.i V.sub.R /2.sup.i + . . . +a.sub.n .multidot.V.sub.R /2.sup.n or alternatively for generating the voltage V.sub.x =a.sub.o V.sub.R +a.sub.1 .multidot.V.sub.R /2+a.sub.2 .multidot.V.sub.R /2.sup.2 + . . . +a.sub.i .multidot.V.sub.R /2.sup.i + . . . +a.sub.n .multidot.V.sub.R /2.sup.n in the event that the coefficients a.sub.o . . . a.sub.n are known, wherein said generator is constituted by a charge-transfer device comprising an alternate arrangement of storage gates and transfer gates together with: a diode D.sub.e placed at one end of the active region in which transfer and storage of charges take place, the function of said diode being to inject a reference quantity of charges 2Q.sub.R at the beginning of processing of each sample V.sub.x or of each series a.sub.o . . . a.sub.n as well as to effect removal of surplus charges during the processing operation; an insulating diffusion which divides into two equal parts the charges originating from a storage gate G.sub.o located near the diode D.sub.e and which divides the active region into two parallel channels downstream of the gate G.sub.o ; in one channel, a storage gate G.sub.2 beneath which the quantities of charges Q.sub.R, Q.sub.R /2 . . . Q.sub.R /2.sup.i . . . are stored by successive two-trip traversals between gates G.sub.o and G.sub.2 ; in the other channel, three storage gates G.sub.1, G.sub.3 and G.sub.4, the quantity of charges Q.sub.R /2.sup.i stored beneath gate G.sub.1 and originating from gate G.sub.o being transferred beneath said gate G.sub.o and then removed beneath the diode D.sub.e when a.sub.i is zero in respect of i=0 . . . n and being transferred beneath gate G.sub.3 when a.sub.i is equal to 1; when the coefficients a.sub.o . . . a.sub.n are unknown, a charge-reading device connected to gates G.sub.2 and G.sub.4 and adapted to generate the reference voltage V.sub.R at the time of transfer of the quantity of charges Q.sub.R beneath gate G.sub.2, thus permitting determination of a.sub.o by comparison of the voltage V.sub.R with the voltage V.sub.x, then to generate V.sub.R1 =a.sub.o V.sub.R +V.sub.R /2 at the time of transfer of the quantity Q.sub.R /2 beneath gate G.sub.2 and, if a.sub.o =1, at the time of any subsequent transfer of Q.sub.R from gate G.sub.3 to gate G.sub.4, thus permitting determination of a.sub.1 by comparison of the voltage V.sub.R1 with the voltage V.sub.x, and so on until generation of V.sub.Rn and determination of a.sub.n or, when the coefficients a.sub.o . . . a.sub.n are known, a charge-reading device connected to the gate G.sub.4 for generating the voltage V.sub.x by transfer of charges from gate G.sub.3 to gate G.sub.4 when the n coefficients of V.sub.x have been processed.
2. A generator according to claim 1, wherein the surface area of the gates G.sub.1 and G.sub.2 is one-half of the area of gates G.sub.o, G.sub.3 and G.sub.4.
3. A generator according to claim 1 wherein the two parallel channels have the same width.
4. A generator according to claim 1, wherein the diode D.sub.e is followed by a pair of gates consisting of a transfer electrode T.sub.o and a storage electrode G.sub.e to which the same voltage (V.sub.GE) is applied, the implantation beneath the transfer electrode T.sub.o being adapted to ensure that the curves of surface potential as a function of the voltage of said pair of gates are parallel and the diode D.sub.e being successively brought to a low level which permits transfer of charges from the diode D.sub.e beneath the gates T.sub.o and G.sub.e then to a high level which permits storage of the quantity of charges 2Q.sub.R beneath gate G.sub.e.
5. A generator according to claim 1, wherein a diode (D.sub.c) is provided in one of the channels downstream of the storage gate G.sub.4 and permits removal of charges stored beneath gate G.sub.4 on completion of the processing operation.
6. A generator according to claim 1, wherein the width of the storage gate G.sub.o at right angles to the direction of charge transfer is of sufficient value to permit division of charges stored beneath the gate G.sub.o into two equal parts with a high degree of accuracy and a diffused region of opposite type with respect to the substrate is provided over the entire width of the gate G.sub.o in order to reduce the time of distribution of charges beneath said gate G.sub.o.
7. A generator according to claim 1, in which the voltage V.sub.x is available and the coefficients a.sub.o . . . a.sub.n are unknown, wherein said generator comprises an injection diode D.sub.e ' which is identical with the diode D.sub.e and followed by a pair of gates consisting of a transfer electrode T.sub.o ' and of a storage electrode G.sub.e ' which is identical with the pair T.sub.o -G.sub.e, the diode D.sub.e ' being successively brought to a low level and to a high level, the gate T.sub.o ' being brought to the potential V.sub.GE and the potential V.sub.x being applied to the gate G.sub.e ', the charges injected beneath gate G.sub.e ' being read-out by a device which is identical with the device connected to gates G.sub.2 and G.sub.4, the result of said readout being compared with the readout performed beneath gates G.sub.2 and G.sub.4 for determination of the coefficients a.sub.o . . . a.sub.n.
8. A generator according to claim 7, wherein the voltage V.sub.x applied to gate G.sub.e ' varies between V.sub.o and V.sub.o +V.sub.Ge and the quantity of charges injected beneath gate G.sub.e ' varies between Q.sub.o and Q.sub.o +2Q.sub.R, a quantity of charges equal to Q.sub.o being added to the charges which arrive beneath the gates G.sub.2 and G.sub.4 by means of a storage gate G.sub.o " which is connected to the point P and beneath which a quantity of charges Q.sub.o is injected by means of an injection device, said device being identical with the device which generates the quantities of charges Q.sub.o +Q.sub.x and 2Q.sub.R.
9. A generator according to claim 7 wherein, the voltage V.sub.x being negative, said voltage V.sub.x or the voltages V.sub.R, V.sub.Ri are reversed in sign by a differential stage before making a comparison between the voltages V.sub.x and V.sub.R, V.sub.Ri.