Circuit for Correcting Data Reading Clock Pulses

1. Field of the Invention

This invention relates to a circuit for correcting data reading clock pulses, and more particularly to an improved circuit for correcting data reading clock pulses which is capable of eliminating mis-reading of data due to timing error of the data reading clock pulses.

2. Description of the Prior Art

In general, reading clock pulses are required to read n-bits of data within a period of time T and the timing of the pulses must be synchronized with an external signal. To this end, a synchronizing signal is generally required. Where no special synchronizing signal is provided for the data reading clock pulses, a start bit is formed, as dummy data, in the data to be read, so as to act as the desired synchronizing signal.

In the former case where a synchronizing signal per se is used, however, it is quite difficult to have the reading clock pulses coincide with the synchronizing signal when mass-produced digital circuits etc. are employed. This has been a problem to be solved. On the other hand, the latter case where a start bit is used has the disadvantage that an additional bit needs to be inserted in a limited time space and a time space for one data bit is reduced.

It is therefore an object of the present invention to provide a circuit for correcting data reading clock pulses which is capable of obviating the aforesaid disadvantages.

It is a more specific object of the present invention to provide a circuit for correcting data reading clock pulses which is capable of eliminating mis-reading of data without using a special synchronizing signal, a start bit, etc. and by automatically selecting optimum clock pulses from roughly synchronized n-phase clock pulse groups.

A circuit for correlating data reading clock pulses, including a clock pulse generator for generating a plurality of groups of clock pulses different in phases, a switch for selecting and outputting one or more groups of clock pulses from the plurality of groups of clock pulses, a device for reading data in response to one or more groups of clock pulses selected by the switch, a detector for detecting mis-reading of the data and outputting a detection signal, and a switch control responsive to the detection signal to control the switch so as to continue selection of another group or groups of clock pulses until correct data reading is accomplished.

FIG. 1 is a block diagram of one form of a circuit for correcting data reading clock pulses in accordance with the present invention;

FIG. 2 is a block diagram of one specific form of a principal portion of the circuit illustrated in FIG. 1;

FIG. 3 shows IC.sub.1 and IC.sub.2 of FIG. 2;

FIG. 4 shows one of the switch circuits S.sub.1 -S.sub.8 of FIG. 3; and

FIG. 5 shows IC.sub.3 of FIG. 2.

Referring now to the accompanying drawings, there is illustrated one preferred mode of the invention. In FIG. 1, numeral 1 designates a data reading device such as a known tape reader. Numeral 2 is a detector for detecting misreading of data, 3 is a switch control circuit, SW.sub.1 to SW.sub.n are switches and 4 is a clock pulse generator for generating clock pulses of groups .phi..sub.1 to .phi..sub.n of n different phases each generally synchronized with a desired external signal. A time of one data bit is divided into n parts to form the clock pulse groups .phi..sub.1 to .phi..sub.n of n phases. Out of these clock pulse groups .phi..sub.1 to .phi..sub.n, a given number of clock pulse groups or groups are selected by corresponding switches SW.sub.1 to SW.sub.n closed by the switch control circuit 3. In the illustrated embodiment, one clock pulse group is selected and the selected clock pulse .phi.out is outputted to the data reading device 1.

If there is an error in data reading by the device 1 effected in response to the clock pulse .phi.out, the detector detects the error and the switch control circuit 3 is actuated by the detection signal so that the switch in a closed position is opened and another switch is closed to select another clock pulse group. Thus, the switch control circuit 3 automatically goes on scanning of the switches, closing the switches sequentially, in response to the detection signals of mis-reading of the data, until a clock pulse .phi.out desired for accurate data reading is obtained. The detector 2 may be a known detector which is adapted to detect an error through an output of a parity check or continuous-transmission check of the read-out data.

FIG. 2 illustrates one example of an arrangement of the switches SW and the switch control circuit 3 employing IC circuits. In the FIG., IC.sub.1 and IC.sub.2 are analog switch circuits and have functions equivalent to those of the switches SW.sub.1 to SW.sub.n. In the illustrated arrangement, the circuit IC.sub.1 receives input clock pulses .phi..sub.2 to .phi..sub.7 and selectively outputs one of the clock pulses .phi..sub.2 to .phi..sub.5 to an output .PHI..sub.8 and outputs one of the clock pulses .phi..sub.3 to .phi..sub.6 to an output .PHI..sub.1. The circuit IC.sub.2 receives inputs .phi..sub.4 to .phi..sub.7 and outputs one of the clock pulses .phi..sub.4 to .phi..sub.7 to an output .PHI..sub.2.

IC.sub.3 is a counter having a function of the switch control circuit 3 as mentioned above. An input terminal I.sub.2 of the counter IC.sub.3 receives a detection output (for example "0" for mis-reading and "1" for correct reading) from the detector 2, while an input terminal I.sub.1 receives a clock pulse .phi..sub.8. I.sub.3 is a reset terminal. O.sub.1 and O.sub.2 are output terminals and connected to control terminals C.sub.1 and C.sub.2 of the analog switch circuit, respectively. Numerals indicated around the respective IC circuit IC.sub.1 to IC.sub.3 designate terminal numbers of IC chips of the respective circuits.

When mis-reading occurs, the detection output "0" is applied to the input terminal I.sub.2 of the counter IC.sub.3 and the counter IC.sub.3 starts to count the clock pulses .phi..sub.8 in response to the detection output. If the mis-reading remains uncorrected, for example, after eight clock pulses have been counted, i.e., the data reading device has failed to correctly read the data eight times, level conditions of the output terminals 01 and 02 are changed and, in response thereto, each of the analog switch circuits changes respective input clock pulse to a different one, namely, an input clock pulse which lags or leads by one phase. Thus, scanning of input clock pulses is repeated until the mis-reading of the data is eliminated.

FIG. 3 illustrates specific formation of the analog switch circuits IC.sub.1 and IC.sub.2 . In the figure, AND.sub.1 and AND.sub.2 are AND circuits, INV.sub.1 to INV.sub.11 are inverters, NAND.sub.1 to NAND.sub.4 are NAND circuits, LLC is a logic level converter circuit, and S.sub.1 to S.sub.8 are switch circuits each of which is formed, for example, of MOS transistors M.sub.1 to M.sub.7. The switch circuit of FIG. 4 is a standard switching circuit which operates in the conventional manner. One of four groups of clock pulses OX to 3X different in phases applied to terminals 12, 14, 15 and 11 respectively is selected to be outputted through a COMMON terminal 13, depending on conditions of signals C.sub.1 and C.sub.2 applied to terminals 9 and 10, i.e., (0,0), (0,1), (1,0) or (1,1). Similarly, one of four groups of clock pulses 0Y to 3Y different in phases, applied to terminals 1, 5, 2 and 4 respectively is selected to be outputted through a COMMON terminal depending on the conditions of the signals C.sub.1 and C.sub.2.

FIG. 5 illustrates one specific form of one of two synchronous binary counters (four digits) constituting the counter IC.sub.3. In the figure, INV.sub.12 to INV.sub.23 are inverters, NOR.sub.1 is a NOR circuit, NAND.sub.5 and NAND.sub.6 are NAND circuits and FF.sub.1 to FF.sub.4 are flip-flop circuits. One of the binary counters counts occurrences of mis-reading of the data, and the other is responsive thereto to output a clock selecting signal through the output terminals O.sub.1 and O.sub.2 of the counter IC.sub.3.

Where various data is superposed on a video signal as in a toll TV broadcast, in general, a horizontal synchronizing signal is utilized as a synchronizing signal for the data, too. However, circuits for separating the horizontal synchronizing signal are usually mass-produced ones and have significant variances therebetween, so that it is quite difficult for all the circuits to generate data clock pulses at desired timing. In such a case, the circuit of the present invention can also be employed with advantages to achieve desired timing.

Further in accordance with the present invention, there is no need to provide a start bit or stop bit within a limited time space so that a time per one bit data can be utilized effectively.