Signal Comparison Circuit

This invention relates to means for generating and maintaining a reference signal at a predetermined fraction between the high and low levels of a single being sensed.

In the design of high speed memories it is desirable to limit the voltage swing between the high voltage level (e.g. V.sub.H) indicative of a logic "1" and the low voltage level (e.g. V.sub.L) indicative of a logic "0" in order to decrease the time it takes for a "1" or a "0" to be produced and/or sensed. Where the voltage difference (.DELTA.V) between V.sub.H and V.sub.L is relatively small it is desirable, for example, to generate a reference voltage midway between V.sub.H and V.sub.L and to compare the signal to be sensed with the reference voltage.

Applicants' invention resides in part in the recognition that a problem exists where the source impedance of the circuit generating the signal to be sensed is different than the source impedance of the reference voltage generating circuit and where the sensing circuit loads (i.e. draws current from) the signal and reference generators. The loading by the sensing circuit alters and shifts the signal levels and the reference level by different amounts. For example, where the sense circuit draws equal currents through the reference and signal generators and where the source impedance of the reference is less than that of the signal generator, the reference signal of the sense amplifier will be offset (e.g. shifted upwards relative to the signal) towards one of the two signal levels, decreasing the margin between one of the signal levels and the reference signal. The system's ability to distinguish the high and low signal levels relative to the reference level is thereby degraded.

Applicants further recognized that, in general, a problem exists where the voltage drop (I.sub.L2 R.sub.1) across the source impedance of a signal generator plus the voltage drop (I.sub.L2 R.sub.2) across the impedance means coupling the signal generator to the sense circuit due to the sense circuit load current (I.sub.L2) through them is not equal to the voltage drop (I.sub.L1 R.sub.3) across the source impedance of a reference generator plus the voltage drop (I.sub.L1 R.sub.4) across the coupling means coupling the reference generator to the sense circuit due to the sense circuit load current (I.sub.L1) through them. When the inequality exists, any change in I.sub.L1 and I.sub.L2 even where the changes in I.sub.L1 and I.sub.L2 are equal (or proportional) results in unequal changes in the reference voltage and the signal voltage applied to the sense circuit.

Applicants' invention also resides in the means for generating a reference signal and maintaining the reference signal at the input to the sense circuit at a fraction between the two levels, (high and low), of a signal to be sensed as will be discussed in detail below.

Circuits embodying the invention include a signal generator (e.g. a memory cell) having a source impedance R.sub.1 and an output at which signals are produced having either one of a high value (V.sub.1H) or a low value (V.sub.1L). The signal generator output is coupled via the "ON" impedance R.sub.2 of a first coupling means to a first input of a sense circuit. A reference generator (e.g. a reference cell) having a source impedance R.sub.3 has an output at which is produced a reference signal (V.sub.2) having a value intermediate V.sub.1H and V.sub.1L. The reference generator is coupled via the "ON" impedance R.sub.4 of a second coupling means to a second input of the sense circuit. The sense circuit is of the type which has direct current conduction paths between its first and second inputs and a point of reference potential. Consequently, the sense circuit causes:

1. A first current (I.sub.L1) to flow through R.sub.3 and R.sub.4 causing the reference signal (V.sub.2) at the second (e.g. reference) input of the sense circuit to be offset by an error term equal to I.sub.L1 (R.sub.3 +R.sub.4); and

2. A second current (I.sub.L2) to flow through R.sub.1 and R.sub.2 causing the signals (V.sub.1H or V.sub.1L) at the first (e.g. signal) input to be offset by an error term equal to I.sub.L2 (R.sub.1 +R.sub.2).

In circuits embodying the invention the error terms are cancelled by making I.sub.L1 (R.sub.3 +R.sub.4)=I.sub.L2 (R.sub.1 +R.sub.2). This results in:

where K=I.sub.L2 /I.sub.L1.

For the values of R.sub.1, R.sub.2, R.sub.3 and R.sub.4 satisfying equation 1 above, V.sub.R may be set at any arbitrary point between V.sub.SL and V.sub.SH and its position relative to V.sub.SH and V.sub.SL will be maintained even though the loading of the sense circuit may change (i.e. the "load" currents (I.sub.L1 and I.sub.L2) may increase or decrease) so long as K remains constant.

In the accompanying drawing like reference characters denote like components, and

FIG. 1 is a schematic diagram of a circuit embodying the invention;

FIG. 2 is a schematic diagram of a simplified equivalent circuit of FIG. 1;

FIG. 3 is a drawing of the I.sub.DS versus V.sub.DS of a typical IGFET;

FIG. 4 is a diagram of voltage levels associated with certain nodes of the circuit of FIG. 1 under different conditions;

FIG. 5 is a schematic diagram of a bipolar sense circuit which may be used in a circuit embodying the invention; and

FIG. 6 is a simplified equivalent diagram of a circuit embodying the invention using a sense circuit of the type shown in FIG. 5.

The circuit of FIG. 1 includes a Read Only Memory (ROM) array 10, a "dummy" (reference) cell 12, and a sense amplifier 14 for comparing a signal output from array 10 with a reference signal generated by cell 12.

The structure and operation of blocks 10 and 12 will first be described for the condition when the blocks 10 and 12 are decoupled (transmission gates PR1 and PD2 are OFF) from the sense circuit 14 which is defined herein as the "no load" condition.

The ROM array 10 (only two columns and two words of which are shown) is comprised of 2 bit line (column) conductors (C.sub.1, C.sub.2) and row (Word) conductors (W.sub.1, W.sub.2) disposed in an orthogonal direction to the bit line conductors. Each intersection of a row conductor and a bit line conductor defines a bit location. There is a single data storage (memory cell) IGFET, Ni-j, of N conductivity type at each bit location. The gate electrode of each IGFET in a word is connected to the word conductor for that word and the source electrodes of all the N-IGFETs are connected to ground. Each IGFET at a bit location either has: (a) its drain connected to its associated bit line conductor in which event that bit location (e.g. N1-1, N2-2) is arbitrarily defined as storing a logic "0"; or (b) its drain is disconnected from its associated bit line conductor in which event that bit location (e.g. N1-2, N2-1) is arbitrarily defined as storing a logic "1".

The conduction path of a P-type load IGFET (PL1,PL2) is connected between each column (bit line) conductor and V.sub.DD which is typically 5 volts. The gate electrodes of the load IGFETs are connected to ground potential so that the load IGFETs are always conducting and the column conductors are normally at, or very close to, V.sub.DD. (IGFET PL1 as well as IGFETs PR1, PD1, and PD2 are drawn with a resistive symbol in their conduction paths to indicate that, when ON, they are operated as resistive elements).

The contents of the cells of ROM 10 associated with a selected word line W.sub.1 are read by applying a potential of V.sub.DD volts to that word line. This turns on all the memory cell IGFETs whose gates are connected to that word line. A memory cell IGFET (e.g. N2-1) whose drain is not connected to a bit line conductor does not conduct a current and its corresponding bit line conductor (e.g. C.sub.2) under "no load" condition remains at V.sub.DD (logic "1") due to its turned-on load IGFET (e.g. PL2). A memory cell IGFET (e.g. N1-1) whose drain is connected to a bit line conductor conducts a saturation current (I) and the potential (e.g. V.sub.1) of that bit line (e.g. C.sub.1) under "no load" condition drops to [V.sub.DD -IZ.sub.PL ], corresponding to logic "0"; where Z.sub.PL is the impedance of the load device (e.g. PL1) connected to that column.

The swing between the logic "1" level (V.sub.H) and the logic "0" level (V.sub.L) is intentionally made small by making the impedances (Z.sub.Nij) of the conduction paths of the N-type IGFETs, all of which are approximately equal to each other, much larger than the impedances (Z.sub.PL) of the load IGFETs (PLi), all of which are approximately equal to each other. To make the memory as dense as possible, the memory cell transistors (Ni-j) are made as small as possible. It is important to conserve area because the ROM may have, in some cases, 64,000 (or more) memory cell transistors and it is desired that they all fit on the same chip. The impedance (Z) of an IGFET is a function of its physical size, which can be relatively well controlled. Z=f(L/W) where L is the channel length and W is the channel width. Hence, the ratio of the sizes (and impedances) of the IGFETs (P and N) to each other is well defined.

The "dummy" or reference cell 12, which includes IGFET PD1 and ND1, functions to generate a reference voltage (V.sub.2) intermediate the V.sub.1H and V.sub.1L voltage levels of the ROM cells. The conduction path of PD1 is connected between V.sub.DD and a node 2 and the conduction path of ND1 is connected between node 2 and ground. The gate electrode of PD1 is returned to ground potential while a read-control pulse (RC) is applied to the gate electrode of ND1. PD1, which is of the same conductivity type as the load devices PLi, is designed to have an impedance Z.sub.PD1 equal to one-half the impedance of Z.sub.PL. In practice, PD1 may be formed by connecting, in parallel, the conduction paths of two transistors similar to the PLi transistors. PD1 is then effectively twice the size of the PLi transistors and its Z.sub.PD1 is equal to Z.sub.PL /2. IGFET ND1 is of the same conductivity type and size as the memory cell N-type IGFETs of the ROM. Making ND1 the same size as the memory cell transistors ensures tracking over temperature, voltage, and fabrication processing. As an aside, it would be difficult to make ND1 smaller than the Ni-j transistors since as a practical matter, the latter are already made about as small as can be managed with an acceptable yield. A read-control (RC) pulse having an amplitude of V.sub.DD volts is applied to the gate electrode of N.sub.D1 during a read cycle. This is the same amplitude turn-on signal (W.sub.i =V.sub.DD) that is applied to the gate electrodes of the memory cell transistors. Hence, ND1, when turned on, conducts a saturation current (I) which is approximately equal to the current (I) conducted by a turned-on memory cell transistor. Therefore, the voltage drop across PD1 due to the current I under "no load" condition, is approximately one-half (1/2) that across PLi (since Z.sub.PD1 =1/2Z.sub.PL) when a current I flows through PLi.

In general, under "no load" condition, the signal voltage (e.g. V.sub.1) produced on any of the bit line conductors will be equal to one of: (a) V.sub.DD volts, or (b) [V.sub.DD -.DELTA.V] volts; where .DELTA.V is equal to (I).multidot.(Z.sub.PL), and where I is the saturation current through a memory cell N-type IGFET or ND1. The reference voltage (V.sub.2) at node 2, under "no load" condition, is equal to [V.sub.DD -.DELTA.V/2] volts, since I.sub.ND1 =I.sub.Nij and Z.sub.PD1 =Z.sub.PDi /2.

The information generated on a bit line conductor (C.sub.1, C.sub.2) is selectively coupled via its associated transmission gate transistor (PR1, PR2) to a data line (DL) which is connected to node 5 which is a signal input of sense circuit 14. The reference cell output (V.sub.2) is coupled via a transmission gate transistor PD2 to a node 3 which defines another input terminal of circuit 14. With the turn on of PD2 and any of the PRi transistors, the memory cells signals on Ci and the reference signal V.sub.2 are respectively "loaded". In more detail, with PD2 on, a load current (I.sub.L1) flows between nodes 2 and 3, which current flows from V.sub.DD via PD1 and PD2 into node 3. Similarly, with the turn-on of any of the PRi transistors, a load current (I.sub.L2) flows from V.sub.DD via PLi and PRi into node 5.

Thus, to read data out of memory 10, a word line (Wi) is energized (V.sub.DD is applied to it) and a gating transistor (PRi) is turned on coupling a selected column (bit line) conductor to the data line and hence to node 5. Concurrently, RC goes positive turning on ND1 and establishing a reference signal, and RC goes negative turning on PD2 which couples the reference signal to node 3.

The sense amplifier 14 includes a bias generating stage 20 comprised of transistors P20 and N20, a signal sensing stage 22 comprised of transistors P22 and N22, and a buffer stage 24 comprised of transistors P24 and N24.

The conduction paths of transistors P20 and N20 are connected in series between node 3 and ground. The gates and drains of P20 and N20 and the gates of P22 and N22, are connected in common to node 4. The conduction paths of P22 and N22 are connected in series between node 5 and ground and the drains of P22 and N22, defining the output node 6 of stage 22, are connected to the gate electrodes of P24 and N24. The sources of P24 and N24 are connected to V.sub.DD and ground, respectively, and their drains are connected in common to the sense amplifier output node 7.

In the circuit of FIG. 1, P20 and N20 are designed to have approximately equal impedances for equal values of turn on bias. By connecting the gates and drains of P20 and N20 in common, P20 and N20 function as a self-biased inverter whose quiescent point (V.sub.4 at node 4) is set approximately at the mid point of the operating potential applied across the inverter. The operating potential across inverter 20 is the difference between the potential (V.sub.3) applied to the source of P20 and the potential (0 volts) applied to the source of N20. Hence, V.sub.4 which is directly applied to the gates of P22 and N22 functions as the bias voltage to stage 22 placing it in its high gain region. P22 and N22 are also designed to have approximately equal impedances (i.e. Z.sub.P22 =Z.sub.N22) for equal values of turn-on bias. P22 and N22 then form a complementary inverter whose "flip-point" voltage (V.sub.FP) is equal to 1/2 the operating potential (V.sub.P =V.sub.5) applied across the inverter stage 22.

V.sub.P across stage 22 is the difference between the potential (V.sub.5) applied to the source of P22 and the potential (0 volts) applied to the source of N22. V.sub.FP of inverter 22 for the condition of Z.sub.P22 =Z.sub.N22, is equal to V.sub.5 /2.

Sense amplifier 14 compares the signal applied to input node 5 (which may be V.sub.SH or V.sub.SL) with V.sub.R at input node 3 and produces at the output of stage 22 a signal indicative of whether the signal at node 5 is more positive than, equal to, or less positive than V.sub.R. The detailed explanation of the operation of the sense amplifier is set forth in our copending application entitled SMALL SIGNAL MEMORY SYSTEM, assigned to the assignee of this application bearing Ser. No. 106,882 and issued as U.S. Pat. No. 4,270,190 and is incorporated herein by reference.

In the discussion to follow, it is assumed that inverter 20 conducts a current (I.sub.L) between node 3 and ground and that inverter 22 conducts a current (KI.sub.L) between node 5 and ground; where K is a constant which is a function of the ratio of the impedances of the transistors in stage 22 to the impedances of the transistors in stage 20. Assuming all the transistor channels to have the same length, K may be expressed as follows: K=W.sub.P22 /W.sub.P20 =W.sub.N22 /W.sub.N20 where W.sub.P20, W.sub.P22, W.sub.N20 and W.sub.N22 are, respectively, the channel widths of transistors P20, P22, N20 and N22.

For the condition Z.sub.P20 =Z.sub.N20 and Z.sub.P22 =Z.sub.N22, inverters 20 and 22 are biased near their midpoint. Hence, for the particular condition W.sub.P20 =W.sub.P22 and W.sub.N20 =W.sub.N22, the load current (I.sub.L) flowing between node 3 and ground is approximately equal to that flowing between node 5 and ground (K is equal to 1).

The load currents into nodes 3 and 5 cause a shift in the signal at nodes 1, 2, 3 and 5, which is best explained by reference to FIG. 2 which is a simplified equivalent circuit diagram of portions of the circuit of FIG. 1.

Transistors Ni-j and transistor ND1 may be represented by current sources 21 and 23. Transistors Ni-j and transistor ND1 are operated in the current saturation region. When any one of the memory transistors Ni-j is turned-on, or when transistor ND1 is turned-on, a potential of V.sub.DD volts is applied to its gate while its source remains grounded. Therefore, its gate-to-source potential (V.sub.GS) is constant. Also, the impedances of ND1 and of the memory transistors are significantly greater than the impedances of the load IGFETs connected in their drain circuits. Consequently, when these transistors are turned-on and connected in circuit, most of the voltage drop (between V.sub.DD and ground) occurs across their drain-to-source paths rather than the drain-to-source path of the load transistors. Each one of the memory transistors, when connected in circuit and ND1, when turned-on, then functions as a relatively constant current generator, whose pertinent characteristics may be noted by reference to FIG. 3 which shows a typical drain-to-source current (I.sub.DS) versus drain-to-source voltage (V.sub.DS) curve of an IGFET for constant values of V.sub.GS. For V.sub.DS greater than V.sub.GS -V.sub.T, where V.sub.T may be assumed to be in the range of 1 volt, the I.sub.DS versus V.sub.DS response curve is very flat, for constant values of V.sub.GS. Hence, the current (I.sub.DS) through the transistor remains essentially constant, even though the V.sub.DS across the transistor may be decreased until V.sub.DS =V.sub.GS -V.sub.T or increased to V.sub.DD.

Transistors Ni-j and/or ND1 should be represented by an ideal current generator in parallel with an output impedance which is a measure of the flatness of the response curve. However, the output impedance is in the order of meghoms (10.sup.6 ohms) which is much larger than the ohmic values of the load impedance. Hence, the output impedance may be ignored in this discussion. Thus, in FIG. 2 resistor R.sub.1 represents the ohmic value of a load transistor (e.g. PL1). Resistor R.sub.2 represents the ohmic value of a turned-on column transmission gate transistor (PRi) plus all the conductor impedances. Resistor R.sub.3 represents the ohmic value of the "reference" load transistor PD1, which in the circuit of FIG. 1, is equal to R.sub.1 /2. Resistor R.sub.4 represents the ohmic value of the compensation and coupling transmission gate transistor PD2. I.sub.L1 represents the d.c. current drawn by inverter stage 20, while I.sub.L2 =KI.sub.L1 represents the d.c. current drawn by inverter stage 22.

An examination of FIGS. 1 and 2 indicates that when transmission gates PD2 and PRi are turned on, currents I.sub.L1 and I.sub.L2 flow into nodes 3 and 5, respectively. These currents cause an additional voltage drop across resistors R.sub.3 and R.sub.1. Thus, the values of V.sub.1 and V.sub.2 prior to the turn-on of the transmission gates (defined as the "unloaded" condition) are not the same as their values after the turn-on of the transmission gates. Furthermore, V.sub.1H, V.sub.1L and V.sub.2 shift down to the voltages V.sub.SH, V.sub.SL, and V.sub.R, respectively, due to the "load" currents I.sub.L2 and I.sub.L1, respectively.

The expression for the high level (V.sub.SH) and low level (V.sub.SL) signals voltages applied to node 5 of the sense amplifier may be expressed as follows:

The expression for the voltage V.sub.R, applied to node 3 of the sense amplifier may be expressed as follows:

Comparing equations 2a, 2b and 3 it may be observed that each equation includes a "pure signal" term and an "error" term.

The "pure signal" terms in equations 2a, 2b and 3 are, respectively: V.sub.DD ; [V.sub.DD -IR.sub.1 ]; and [V.sub.DD -IR.sub.3 ]. The error term in equation 2a is equal to [I.sub.L2 .multidot.(R.sub.1 +R.sub.2)] which is equal to the error term in equation 2b. The error term in the "reference" equation 3 is equal to [I.sub.L1 .multidot.(R.sub.3 +R.sub.4)]. Applicants recognized that making the error term I.sub.L2 (R.sub.1 +R.sub.2) in equations 2a and 2b equal to the error term I.sub.L1 (R.sub.3 +R.sub.4) in equation 3 prevents the reference signal applied to node 3 of the sense circuit from being shifted by a different amount than the memory signals applied to node 5. These error terms are made equal by maintaining the relationship shown in equation 1 (which is repeated below) among R.sub.1, R.sub.2, R.sub.3 and R.sub.4.

where K is the ratio of I.sub.L2 to I.sub.LI.

The significance of satisfying equation 1 is that V.sub.R remains at a fixed fraction between V.sub.SH and V.sub.SL for any change in I.sub.L1 and I.sub.L2, so long as K is constant.

For the condition of FIG. 1 where V.sub.R is desired to be set midway between V.sub.SH and V.sub.SL, and where equal currents (I) flow in transistor Ni-j and ND1, R.sub.3 is made equal to R.sub.1 /2.

Further in FIG. 1 since I.sub.L1 is equal to I.sub.L2, R.sub.4 is made equal to R.sub.2 +R.sub.1 /2, such that R.sub.3 +R.sub.4 =R.sub.1 +R.sub.2. Thus, for the circuit of FIG. 1, V.sub.R is set midway between V.sub.SH and V.sub.SL and will remain in that position so long as K=I.sub.L2 /I.sub.L1 =1.

By way of example, a circuit embodying the invention was built in which: (a) the current (I) drawn by the Ni-j transistors and ND1 was 400 microamperes (400.times.10.sup.-6 amperes); (b) R.sub.1 --the impedance (Z.sub.PL) of the PLi transistors--was approximately 1 Kohm; (c) R3--the impedance of PD1--was 500 ohms; (d) V.sub.DD was equal to 5 volts; (e) the d.c. current drawn by inverters 20 and 22 were each equal to 120 microamperes, i.e. K was equal to 1; (f) R.sub.2 --the "ON" impedance of PRi--was 1 Kohm; and (g) R.sub.4 --the "ON" impedance of PD2--was 1.5 Kohms (equal to R.sub.2 +1/2R.sub.1).

The shifting of the reference and signal voltages due to the current drawn by the sense circuit is tabulated in TABLE 1 below and is illustrated graphically in FIG. 4 for the following three conditions:

A. The "NO LOAD" condition which occurs when transmission gates PRi and PD1 are "OFF". The status of the signal generator and reference generator when decoupled from the sense amplifier is set forth at line A of TABLE 1 and is depicted in FIG. 4A.

B. The "loaded uncompensated" condition is set forth at line B of TABLE I and is depicted in FIG. 4B. The "load" condition occurs when PD1 and a PRi transistors are turned on and the signal and reference generators are coupled to the sense amplifier. The circuit is "uncompensated" in that the impedances of the transmission gates were made equal (R.sub.2 =R.sub.4) and R.sub.3 .noteq.R.sub.1.

C. The "loaded compensated" condition is set forth at line C of TABLE 1 and is depicted in FIG. 4C. The loaded condition consists of coupling the signal and reference generators to the sense amplifier. The compensated condition consisted of making the sum of R.sub.3 and R.sub.4 equal to the sum of R.sub.1 and R.sub.2, (since I.sub.L1 was equal to I.sub.L2, K was equal to 1).

It is evident from TABLE I and FIG. 4 that for the uncompensated condition V.sub.SH -V.sub.R =0.140 volts; whereas V.sub.R -V.sub.SL =0.260 volt. Thus, the margin for one condition would be almost twice that for the other condition.

For the compensated condition, there is equal margin between V.sub.R and the V.sub.SH and V.sub.SL conditions. Of additional significance is that the position of V.sub.R between V.sub.SH and V.sub.SL is independent of changes in V.sub.DD and, is independent of changes in the load currents drawn by the sense circuit so long as I.sub.L1 =I.sub.L2.

For the input to the sense circuit being equivalent to current sources there is no attenuation of the difference between V.sub.1H and V.sub.1L generated when the circuit is unloaded. The signals (V.sub.SH and V.sub.SL) and the reference V.sub.R are only shifted down with respect to V.sub.1H and V.sub.1L.

In some circuit V.sub.R may be desirably set at some point other than midway between V.sub.SH and V.sub.SL. For these conditions the equations derived above may be modified as follows:

where: .DELTA.V=V.sub.SH -V.sub.SL ; and C, which is a fraction less than 1, determines the point between V.sub.SH and V.sub.SL at which V.sub.R is set. To set V.sub.R at V.sub.SL +C.DELTA.V, the value of R.sub.3 may be defined as follows:

while the relationship between R.sub.1, R.sub.2, R.sub.3 and R.sub.4 is still as described in equation 1 above.

It has thus been shown that V.sub.R may be set to any arbitrary point between V.sub.SH and V.sub.SL and that the signal and reference generator circuits may be compensated to ensure that V.sub.R, V.sub.SH and V.sub.SL are all shifted by the same amount, so long as the ratio K=I.sub.L2 /I.sub.L1 does not change.

In the circuit of FIG. 1 it was assumed that the currents (I) in transistors Ni-j and ND1 were equal. However, it should be evident that where desired the current (I.sub.A) through Ni-j could be different than the current (I.sub.B) through ND1.

The "signal terms" in equation 2a, 2b, and 3 would then be V.sub.DD ; V.sub.DD -I.sub.A R.sub.1 ; and V.sub.DD -I.sub.B R.sub.3. But, so long as I.sub.A R.sub.1 is greater than I.sub.B R.sub.3, V.sub.R will be positioned between V.sub.SH and V.sub.SL, and, so long as the requirements of equation 1 are satisfied V.sub.R will maintain its position between V.sub.SH and V.sub.SL.

The signal and reference circuits may also be compensated for the condition where their outputs are coupled to a circuit of the type shown in FIG. 5, whose equivalent input impedance is resistive (and not an equivalent current source). FIG. 5 shows a differential stage 14' comprised of two bipolar transistors (Q1, Q2) connected at their bases to nodes 3 and 5, respectively. The equivalent circuit of the memory, the reference, and the sense circuit may then be represented as shown in FIG. 6.

R.sub.5 represents the input impedance looking into the base of Q1 and R.sub.6 represents the input impedance looking into the base of Q2.

Analysis of the circuit of FIG. 6 is as follows: ##EQU1##

To set V.sub.R midway between V.sub.SH and V.sub.SL ##EQU2##

This may be satisfied when V.sub.2 =[V.sub.DD +V.sub.L ]/2 and ##EQU3## solving for R.sub.4 indicates that: ##EQU4##

The sum of R.sub.3 and R.sub.4 which is equal to the total impedance looking back from node 3 into the reference circuit to AC ground may be expressed as:

where, R.sub.5 and R.sub.6 represent the impedances looking into input nodes 3 and 5, respectively, of sense amplifier 14'. Therefore, R.sub.5 /R.sub.6 corresponds to the term K described above. For V.sub.3 and V.sub.5 approximately equal, the ratio of R.sub.5 and R.sub.6 is essentially equal to the K=1 condition discussed above.