Divisional Reading Device for Sine Signals

1. Field of the Invention

This invention relates to a device for use with an apparatus such as a position encoder, a laser interferometer or the like in which a detector outputs two sine signals out of phase with each other in accordance with a position change (generally, the signals from said detector are not pure sine signals but are quasi-sine signals, whereas herein signals including such quasi-sine signals are referred (to as sine signals) to indicate the amount and direction of displacement. The device forms the ratio of the sine signals to enable greater resolution and accuracy in the determination of displacement.

2. Description of the Prior Art

A device for dividing and for reading out the signals from a position encoder is known in which two sine signals, out of phase with each other by 90.degree., obtained from a detector are applied to a resistor array to thereby form sine signals of various phases, and all the zero crossing points of these signals are counted.

However, such conventional divisional reading device has required a great number of divisions and thus a large number of zero detecting circuits, and this has led to a disadvantage that the circuit construction thereof becomes complex.

The conventional device has also suffered from the disadvantage that the accuracy of division is poor due to the amplitude fluctuations or the like of the two sine signals.

A further disadvantage of the conventional device is that the accuracy of division is poor due to the so-called phase fluctuation of the two sine signals which is the deviation of the phase difference therebetween from 90.degree. resulting from temperature changes or the like.

It is a first object of the present invention to provide a divisional reading device which is simple in circuit construction.

It is a second object of the present invention to provide a device which can effect divisional reading having high accuracy and free of the influence of amplitude fluctuations of signals, by a simple construction.

It is a third object of the present invention to provide a device which can effect divisional reading having high accuracy without being affected by phase fluctuations of signals, by a simple construction.

The invention will become fully apparent from the following detailed description of some embodiments thereof taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing a first embodiment of the device according to the present invention.

FIG. 2 is a waveform diagram for illustrating the manner in which a sine signal is divided by the device of the present invention.

FIGS. 3A-3I are the waveform diagrams for illustrating a certain reading error occurring in the circuit of FIG. 1.

FIG. 4 is a block diagram showing a second embodiment of the present invention in which a reading error correcting circuit is added to the circuit of FIG. 1.

FIG. 5 is a block diagram showing the details of the blocks 30 and 80 of FIG. 4.

FIG. 6 is a block diagram showing a third embodiment of the device according to the present invention which can effect divisional reading accurately even when sine signals out of phase with each other by 90.degree. create amplitude fluctuations.

FIGS. 7A-7F illustrate the waveforms appearing in various portions of the block diagram of FIG. 6.

FIG. 8 is a block diagram showing a fourth embodiment of the device according to the present invention which can effect divisional reading accurately even when two sine signals create phase fluctuations in addition to amplitude fluctuations.

FIGS. 9A-9J illustrate the waveforms appearing in various portions of the block diagram of FIG. 8.

FIG. 10 illustrates the principles on which phase error is eliminated in the block diagram of FIG. 8.

FIGS. 11A and 11B are graphs showing tangent curves used to illustrate a modification of the FIG. 8 embodiment.

In the following embodiments, to proceed with the discussion concretely, description will be made of an example in which the divisional reading device of the present invention as applied to a linear encoder for measuring displacement. The linear encoder is usually designed to provide two sine voltages 90.degree. out of phase with each other at the output of a detector to enable the direction of movement to be determined.

In FIG. 1, zero detecting circuits 2 and 4 receive as inputs two sine voltages e.sub.0 and e.sub.90 obtained from the aforementioned detector (e.sub.90 is a sine voltage which is advanced by 90.degree. in phase with respect to e.sub.0) and waveform-shape such voltages into rectangular voltages with 0 volts as the standard. A gate circuit 6 forms a pulse at the rising and falling edges of the rectangular voltage corresponding to the voltage e.sub.0 and discriminates the direction of movement of a main scale of the encoder from the relation between the two rectangular voltages corresponding to the voltages e.sub.0 and e.sub.90. That is, when the main scale moves in the positive direction, the gate circuit 6 outputs pulses to a terminal connected to the up input (a) of an up-down counter 8 and, when the main scale moves in the reverse direction, the gate circuit 6 outputs pulses to a terminal connected to the down input (b) of the up-down counter 8. Accordingly, the number of pulses counted by the counter 8 corresponds to the displacement of the main scale from its initial position. Assuming that the design is such that one half period of the voltage corresponds to l.mu. (displacement unit) on the main scale, it will be seen from the count content n of the counter 8 that the displacement of the main scale is n.mu.. Such a construction is well-known as the counting circuit of the conventional linear encoder.

In accordance with the invention, the sine voltages e.sub.0 and e.sub.90 are converted into digital signals e.sub.D0 and e.sub.D90 by A-D converters 10 and 12, respectively, and their ratio e.sub.D0 /e.sub.D90 is formed and output by a division circuit 14. An operational circuit 16 performs the operation tan -1 (e.sub.D0 /e.sub.D90). A conversion circuit 18 outputs a signal corresponding to the value range of tan -1 (e.sub.D0 /e.sub.D90) in accordance with a preset rounding width depending on the number of ports, i.e., intervals, into which the one-half period (180.degree. ) of the sine voltage is divided. For example, where the one-half period (180.degree.) is divided into ten equal parts as shown in FIG. 2, the rounding width becomes 18.degree.. Accordingly, the conversion circuit 18 outputs a digital signal between corresponding to a particular 0-9 18.degree. interval i.e., it outputs 0 when tan.sup.-1 (e.sub.D0 /e.sub.D90) is 0.degree.-18.degree., it outputs 1 when tan.sup.-1 (e.sub.D0 /e.sub.D90) is 18.degree.-36.degree., it outputs 2 when tan.sup.-1 e.sub.D0 /e.sub.D90) is 36.degree.-54.degree., . . .. If the one-half period corresponds to 1.mu., the order of the output signal of the conversion circuit 18 corresponds to 0.1.mu., i.e., tenths of a displacement unit. An addition circuit 20 adds the output of the converting circuit 18 to the count content of the counter 8 and provides the sum as the drive signal for a displayer 22. Accordingly, if the output of the conversion circuit 18 is m(0.ltoreq.m.ltoreq.9), (n+0.1 m).mu. will be displayed on the displayer 22. Thus, the reading accuracy is enhanced by tenths of a unit.

The operational circuit 16 and conversion circuit 18 may be replaced by a ROM (Read Only Memory) 25, as is indicated by broken lines in FIG. 1. That is, if the design is such that the ratio e.sub.D0 /e.sub.D90 and the values 0-9 corresponding to said ratio are stored in mutually corresponding relationship in ROM 25, s shown in Table I (hereinafter), and the value from the division circuit 14 (ratio e.sub.D0 /e.sub.D90) is used as the address designation data of the ROM 25, a divided value may be obtained without actually effecting an operation. Further, the design may of course be such that the ratio of the voltages e.sub.0 and e.sub.90 is obtained by an analog device, and the ratio is A-D-converted so that e.sub.D0 /e.sub.D90 is obtained as the A-D-converted value.

In the above-described circuit construction, the circuits 2 and 4 for detecting the zero crossing points of the sine voltages e.sub.0 and e.sub.90 and the A-D converters 10 and 12 used for the divisional reading operate independently of each other. Therefore, if the amount of drift differs from one circuit to another, an error in the reading would occur at certain positions. The following is the description of means for overcoming such a disadvantage.

FIG. 3A shows the sine voltage e.sub.90 and FIG. 3B shows the sine voltage e.sub.0. FIG. 3C shows the rectangular voltage output of zero detecting circuit 4 produced by crossing points of the sine voltage e.sub.90, and FIG. 3D shows the rectangular voltage output of zero detecting circuit 2 produced by the zero crossing points of the sine voltage e.sub.0 FIGS. 3E and 3F shown pulses produced at the rising and falling edges of the voltage waveform of FIGS. 3C and 3D, respectively. FIG. 3G shows an assumed count value of the counter 8 of FIG. 1. FIGS. 3H and 3I illustrate the case where the one-half period of FIG. 3B is divided into ten parts, FIG. 3H showing an example of the value in a case where the reference position (the position changed from 9-0) is deviated leftwardly with respect to FIG. 3G, and FIG. 3I showing an example of the value in a case where the reference position (the position changed from 9-0) is deviated rightwardly with respect to FIG. 3G. That is, where the reading of the divided least significant bit (LSB) obtained from the sine voltages e.sub.0 and e.sub.90 is as shown in FIG. 3H, the entire reading is 9999 at position A, 9990 at position B and 0000 at position C. The reading 9990 at position B is a meaningless value. Also, where the reading of the divided least significant bit obtained from the sine voltages e.sub.0 and e.sub.90 is as shown in FIG. 3I, the entire reading is 9998 at position A, 9999 at position B and 0009 at position C. The reading 0009 at position C is a meaningless value. Accordingly, unless, with one of the readings of FIG. 3G and FIG. 3H (or FIG. 3I) as the reference, the value of the other is corrected, the meaning of the digital display would be lost.

FIGS. 4 and 5 show an example in which the reading of FIG. 3G is corrected with that of FIG. 3H, namely, the values of the least significant unit, as the reference. The differences between the FIG. 4 circuit and the FIG. 1 circuit are that the function of the counter has been changed, as later described, and that a gate circuit 30 has been added. In other respects, the FIG. 4 circuit is similar to the FIG. 1 circuit and, therefore, the identical portions need not be described. The blocks 30 and 80 of FIG. 4 will be described in detail with reference to FIG. 5.

In FIG. 5, a gate 50 within the block 30 outputs an H (high level) signal at the upper output terminal when the output of the conversion circuit 18 is 0-4, and outputs an H signal at the lower output terminal when the output of the conversion circuit 18 is 5-9 A gate 51 is an exclusive logic sum gate which outputs an H signal only when the signal levels from the zero detecting circuits 2 and 4 differ from each other. A gate 52 receives as inputs the signals produced at the upper output terminal of the gate 50 and the output terminal of the gate 51, and outputs an H signal when its two input signals are H. A one shot circuit 54 outputs a pulse when the output of the gate 52 becomes H, which increases the count content of a preset counter 82 by one. On the other hand, a gate 53 receives as inputs the signals produced at the lower output terminal of the gate 50 and the output terminal of the gate 51, and outputs H signal when an H signal is produced at the lower output terminal of the gate 50 and when an (low level) signal is produced at the output terminal of the gate 51. A one shot circuit 55 outputs a pulse when the output of the gate 53 becomes H, which decreases the count content of the preset counter 82 by one. A counter 80 has counters 81a, 81b and 81c corresponding to the respective units(bits), and the pulses from the gate circuit 6 of FIG. 1 are successively counted by this counter 80. These counters 81a-81c correspond to the counter 8 of FIG. 1. The contents of these counters 81a, 81b and 81c are applied to the preset counter 82 in a parallel fashion. With such a construction, assume a case where, for example, at the position B of FIG. 3, the output of the conversion circuit 18 is 0 as shown in FIG. 3H. At this time, the counter 81a is counting 9, the counter 81b is counting 9 and the counter 81c is counting 9. Since the outputs of the zero detecting circuits 2 and 4 are L and H, respectively, the gate 51 outputs an H signal. On the other hand, since the output of the conversion circuit 18 is 0, the output to the upper terminal of the gate 50 becomes H and the output of the gate 52 becomes H. Accordingly, the preset counter 82 counts up and its count content becomes 000. Thus, in this case, the count value becomes 9999 at the position A of FIGS. 3, 0000 at the position B of FIG. 3 and also 0000 at the position C of FIG. 3, and the count value continues. Now assume a case where, for example, at the position C of FIG. 3, the output of the conversion circuit 18 is 9 as shown in FIG. 3I. At this time, the counter 81a is counting 0, the counter 81b is counting 0 and the counter 81c is counting 0. Since the outputs of the zero detecting circuits 2 and 4 are H and H, respectively, the gate 51 outputs an L signal. On the other hand, since the output of the conversion circuit 18 is 9, the output to the lower terminal of the gate 50 becomes H and the output of the gate 53 becomes H. Accordingly, the preset counter 82 counts down by one and its count content becomes 999. Thus, in this case, the count value becomes 9998 at the position A of FIG. 3, 9999 at the position B of FIG. 3 and also 9999 at the position C of FIG. 3, and the count value continues.

In this manner, a certain discontinuous value produced at the LSB position due to the error inherent in each circuit can be corrected in the state of reading.

The above-described embodiment is convenient in a case where the two sine signals e.sub.0 and e.sub.90 obtained from the detector have no amplitude fluctuations. However, in a measuring device, for example, an encoder, it is usually the case that the two signals e.sub.0 and e.sub.90 obtained have amplitude fluctuations due to irregularities in lattice spacing, cut lines of lattice, etc. Therefore, another embodiment designed to enable divisional reading to be accurately effected even if there are amplitude fluctuations in the two signals e.sub.0 and e.sub.90 will now be described with reference to the drawings. In this embodiment, elements identical to those in FIG. 1 are given similar reference numerals and need not be described.

In FIG. 6, the sine voltages e.sub.0 and e.sub.90 are applied to a selector 70 and also to peak detectors 60 and 62, respectively. The peak detector 60 generates a pulse at the peak position of the sine voltage e.sub.0 as shown in FIG. 7B, and the peak detector 62 generates a pulse at the peak position of the sine voltage e.sub.90 as shown in FIG. 7C. An OR gate 64 receives as inputs the pulses from the peak detectors 60 and 62 and alternately outputs the two input pulses as shown in FIG. 7D. Sample and hold circuits 66 and 68 are designed to hold the values of the sine voltages e.sub.0 and e.sub.90, respectively, synchronized with the pulse outputs of the OR gate 64, and the outputs thereof are such as shown in FIGS. 7E and 7F, respectively. The positive and negative maximum values of the sine voltage e.sub.0 and E.sub.OP and E.sub.ON, respectively, and the positive and negative maximum values of the sine voltage e.sub.90 and E.sub.90P and E.sub.90N, respectively.

The selector 70 applies successively to an A-D converter 72 the signals applied to its four terminals in accordance with the control signal from a control circuit 71. The control circuit 71 receives as inputs the pulses from OR gate 64 and prepares the control signal for the selector 70 following a predetermined procedure, in accordance with said pulses, and controls the selector 70. The A-D converter 72 A-D-converts the voltages e.sub.0, e.sub.90, E.sub.OP, E.sub.ON, E.sub.90P and E.sub.90N to digital signals e.sub.D0, E.sub.D90, E.sub.DOP, E.sub.DON, E.sub.D90P, and E.sub.D90N corresponding to the magnitudes of the respective signals. These digital signals are successively applied to a regularization circuit 74. The regularization circuit 74 discriminates between the types of the applied digital signals by the control signal from the control circuit 71, regularizes the digital signals e.sub.D0 and e.sub.D90 by the operations of the following equations (1) and (2), and successively outputs regularized signals e'.sub.D0 and e'.sub.D90. ##EQU1## The signals e'.sub.D0 and e'.sub.D90 obtained by regularizing the digital signals e.sub.D0 and e.sub.D90 as described above are free of the influences of amplitude fluctuations of the sine voltages, drift of the circuit, etc. However, generally, the drift of the circuit can be corrected to some degree by the circuit itself and, therefore, in that case, equations (1) and (2) may be simplified into the following equations (1)' and (2)', respectively: ##EQU2##

The signals e'.sub.D0 and e'.sub.D90 obtained by the regularization circuit 74 are successively applied to a division circuit 14', where e'.sub.D0/e'.sub.D90 is calculated. The output e'.sub.D0 /E'.sub.D90 of the division circuit 14' is applied to an operational circuit 16, where it is subjected to the operation tan.sup.-1 (e'.sub.D0 /e'.sub.D90) and the result is output. A conversion circuit 18 outputs a signal corresponding to tan.sup.-1 (e'.sub.D0 /e'.sub.D90) in accordance with the preset rounding width depending on the number of parts into which the one-half period (180.degree.) of the sine voltage is divided. The operational circuit 16 and the conversion circuit 18 may be the same as those shown in FIG. 1.

Also, four memory circuits may be provided in the regularization circuit 74 and a circuit for detecting the frequencies of the voltages e.sub.0 and e.sub.90 may be provided in the control circuit 71, and the design may be made such that the control circuit 71 causes the average values of E.sub.DOP, E.sub.DON, E.sub.D90P and E.sub.D90N to be separately stored in said four memory circuits when the frequencies of the voltages e.sub.0 and e.sub.90 are high, and such that the regularization circuit 74 is controlled so as to effect regularization only when the frequencies of the voltages e.sub.0 and e.sub.90 have become small or when these voltages have become DC voltages (in the case of an encoder, the condition in which the main scale is stopped). Of course, the block M may be replaced by a computer.

As described with respect to the foregoing embodiment, in a linear encoder, there can usually be obtained sine voltages 90.degree. out of phase with each other as the outputs of the detector for the purpose of direction discrimination. However, there may occur also a case where the mutual phase is deviated from 90.degree. due to temperature fluctuations or the like and becomes (90+.phi.).degree. (.vertline..phi..vertline.<90). The following embodiment is a device which can effect accurate divisional reading even in such a case.

In FIG. 8, zero detecting circuits 2 and 4 are for receiving as inputs two sine voltages e'.sub.0 and e'.sub.90 obtained from said detectors (as shown in FIG. 9A, where e'.sub.90 is a sine voltage advanced in phase by (90+.phi.).degree. with respect to e'.sub.0) and for waveform-shaping these sine voltages into rectangular voltages (shown in FIGS. 9B and 9C) with O volts as the standard. A gate circuit 6 forms a pulse at the rising and falling edges of the rectangular voltage (shown in FIG. 9C) corresponding to the voltage e'.sub.0, determines the direction of movement of the main scale of the encoder from the relation between the two rectangular voltages corresponding to the voltages e'.sub.0 and e'.sub.90, outputs a pulse at a terminal connected to the up input (a) of an up-down counter 8 when the movement of the main scale is in the positive direction, and outputs a pulse at a terminal connected to the down input (b) of the up-down counter when the movement of the main scale is in the reverse direction. Accordingly, the number of pulses counted by the counter 8 corresponds to the displacement of the main scale from its initial position. Also, assuming that design is made such that one-half period 180.degree. of the voltage e'.sub.0 corresponds to 1.mu. on the main scale, it will be seen from the count content n of the counter 8 that the displacement of the main scale is n.mu.. Such a construction has already been described with reference to FIG. 1.

On the other hand, sine voltages e'.sub.0 and e'.sub.90 are applied to A-D converters 100 and 101, respectively, and also to peak detectors 60 and 62, respectively. The peak detector 60 generates a pulse at the peak position of the sine voltage e'.sub.0 as shown in FIG. 9E, and the peak detector 62 generates a pulse at the peak position of the sine voltage e'.sub.90 as shown in FIG. 9D. An OR gate 64 receives as inputs the pulses from the peak detectors 60 and 62 and alternately outputs the two input pulses as shown in FIG. 9F. Sample and hold circuits 66 and 68 hold the values of the sine voltages e'.sub.0 and e'.sub.90, respectively, synchronized with the pulses from the OR gate 64 and therefore, the outputs thereof are such as shown in FIGS. 9J and 9I, which correspond generally to FIGS. 7E and 7F. However, the positive and negative maximum values of the sine voltage e'.sub.0 and E.sub.OP and E.sub.ON, respectively, and the positive and negative maximum values of the sine voltages e'.sub.90 are E.sub.90P and E.sub.90N, respectively. A selector 70' successively applies to an A-D converter 72' the signals from the sample and hold circuits 66 and 68 applied to its two input terminals, in accordance with the control signals from a control circuit 71'. The control circuit 71' receives as inputs the pulses from the OR gate 64, prepares the control signal for the selector 70' following a predetermined procedure, in response to said pulse, and controls the selector 70'. An A-D converter 72' A-D-converts the voltages E.sub.OP, E.sub.ON, E.sub.90P and E.sub.90N successively supplied from the selector 70' to digital signals E.sub.DOP, E.sub.DON, E.sub.D90P and E.sub.D90N corresponding to the magnitudes of the respective signals.

A-D converters 100 and 101 A-D-convert the voltages e'.sub.0 and e'.sub.90 to digital signals e.sub.D0 and e.sub.D90 corresponding to the magnitudes of the respective signals.

These digital signals e.sub.D0, e.sub.D90, E.sub.DOP, E.sub.DON, E.sub.D90P and E.sub.D90N are applied to a regularization circuit 74'. The regularization circuit 74' discriminates between the types of the applied digital signals E.sub.DOP, E.sub.DON, E.sub.D90P and E.sub.D90N by the control signal from the control circuit 71', regularizes the digital signals e.sub.D0 and e.sub.D90 by the operations of the following equations (1) and (2), and successively outputs regularized signals e'.sub.D0 and e'.sub.90. ##EQU3## The signals e'.sub.D0 and e'.sub.D90 obtained by regularizing the digital signals e.sub.D0 and e.sub.D90 as described above are free of influences such as amplitude fluctuations in the size of voltages, drift of circuit, etc. As already described in connection FIG. 6, the drift of the circuit can be corrected to some degree by the circuit itself and therefore, equations (1) and (2) may be simplified to the following equations (1)' and (2)': ##EQU4## The signals e'.sub.D0 and e'.sub.D90 obtained by the regularization circuit 74' are applied to a division circuit 14', where e'.sub.D0/e'.sub.D90 is calculated. The otput e'.sub.D0 /e'.sub.D90 of the division circuit 14' is applied to an operational circuit 19.

Where there is no phase fluctuation, if tan.sup.-1 (e.sub.D0 /e'.sub.90) is calculated from the output e'.sub.D0 /e'.sub.D90 of the division circuit 14', the angle .theta. of the signal e.sub.0 will be obtained. If this .theta. is made to correspond to the amount of movement as shown in FIG. 2, division can be effected substantially without any restriction, but this is based on the premise that the phase difference between the signals e'.sub.D0 and e'.sub.D90 is exactly 90.degree. and, if the phase difference is deviated by .phi. from 90.degree., said .phi. will also include an error resulting therefrom. The above-described construction is substantially similar to that of FIG. 6, and may be made identical to the latter. Description will now be made of the portion for eliminating the influence of the above-described phase error.

Reference characters 102-112 designate an example of the circuit for obtaining the phase error .phi. between two signals. The AND circuit 102 outputs the AND signal of the rectangular voltage of zero detecting circuit 2 (FIG. 9C) and the output pulse of the peak detector circuit 60 (FIG. 9E). The AND circuit 103 outputs the AND signal of the rectangular voltage of zero detecting circuit (FIG. 9B) and the output pulse of the peak detector circuit 62 (FIG. 9D). The AND circuit 104 outputs the AND signal of the inverted voltage of the rectangular voltage of the zero detecting circuit 4 (FIG. 9B) and the output pulse of the peak detector circuit 62 (FIG. 9D). The AND circuit 105 outputs the AND signal of the inverted voltage of the rectangular voltage of the zero detecting circuit 2 (FIG. 9C) and the output pulse of the peak detector circuit 60 (FIG. 9E). The selection circuit 106 receives as inputs the output signals of the sample and hold circuits 66 and 68 (FIGS. 9J and 9I), and outputs the output signal of the sample and hold circuit 68 when the AND signal of the AND circuit 102 has been produced, and outputs the output signal of the sample and hold circuit 66 when the AND signal of the AND circuit 103 has been produced. The selection circuit 107 receives as inputs the output signals of the sample and hold circuits 66 and 68 (FIGS. 9J and 9I), and outputs the output signal of the sample and hold circuit 66 when the AND signal of the AND circuit 104 has been produced, and outputs the output signal of the sample and hold circuit 68 when the AND signal of the AND circuit 105 has been produced. Accordingly, the output signal of the selection circuit 106 is the positive error amount .DELTA.i+1, .DELTA.i+2, . . . ; .DELTA.j+1, .DELTA.j=2, . . . of FIGS. 9I and 9J, and the output signal of the selection circuit 107 is the negative error amount .DELTA.i-1, .DELTA.i-2, . . . ; .DELTA.j-1, .DELTA.j-2, . . . of FIGS. 9I and 9J. The above-described error amount .DELTA.i+1, . . . , .DELTA.i-1, . . . .DELTA.j+1, . . . , .DELTA.j-1, . . . , as shown in FIG. 10, corresponds to the deviation .phi. of the phase difference between sine voltages e.sub.0 and e.sub.90 from 90.degree.. That is, in FIG. 10, for example, deviation .phi..sub.1 is obtained as .phi..sub.1 =sin.sup.-1 (.DELTA.j+1) and at this time, the phase difference between the sine voltages e.sub.0 and e.sub.90 is 90+.phi..sub.1.

The OR circuit 108 applies the OR signal of the output signals of the AND circuits 102 and 103 (FIG. 9G) to the averaging circuit 109. The averaging circuit 109 successively adds the output signals of the selection circuit 106 and divides the sum by the number of the OR signals from the OR circuit 108 to obtain an average of the same. Accordingly, the output signal of the averaging circuit 109 is the average signal .DELTA.ij+ of the positive error amounts .DELTA.i+1, . . . ; .DELTA.j+1, .DELTA.j+2, . . . . The OR circuit 110 applies the OR signal of the output signals of the AND circuits 104 and 105 (FIG. 9H) to the averaging circuit 111. The averaging circuit 111 successively adds the output signals of the selection circuit 107 and divides the sum by the number of the OR signals from the OR circuit 110 to obtain an average of the same. Accordingly, the output signal of the averaging circuit 111 is the average signal .DELTA.ij- of the negative error amounts .DELTA.i-1, .DELTA.i- 2, . . . ; .DELTA.j-1, .DELTA.j-2, . . . . The converting circuit 112 receives as inputs the output signals .DELTA.ij+ and .DELTA.ij- of the averaging circuits 109 and 111 and supplies a digital signal corresponding to ##EQU5## That is, the output of the converting circuit 112 is the average value of the phase errors. An operational circuit 19 receives as inputs this digital signal ##EQU6## and the output signal e'.sub.D0 /e'.sub.D90 of the previously described division circuit 14', and effects the following operation; ##EQU7## where n.ident.e'.sub.D0 /e'.sub.D90 ##EQU8##

The meaning of formula (3) is as follows. In FIG. 10, if e.sub.0 =sin0, e.sub.90 =sin(.theta.+.phi.'). Here, if it is assumed that m=e.sub.0 /e.sub.90, then ##EQU9## and from this equation, .theta. is derived as shown by formula (3). In formula (3), m of equation (4) is substituted for by n and the analog value .phi.' is substituted for by the digital value .phi.. The difference between formula (3) and equation (4) is that formula (3) uses a regularized digital signal as the ratio of the amplitudes between two sine waves and formula (3) uses a digital signal with the phase difference between the two sine wave as .phi., but formula (3) and equation (4) show the same content. In this manner, it is possible to obtain .theta. which does not contain the error resulting from the influence of the phase error .phi..

The conversion circuit 18 outputs a signal corresponding to formula (3), which is the output signal of the operational circuit 19, that has been converted in accordance with a preset rounding width depending on the number of ports into which one-half period (180.degree.) of the sine voltage is divided. An addition circuit 20 adds the output of the conversion circuit 18 to the count content of the counter 8 and the sum thereof provides the driving signal for a displayer 22. Accordingly, if the output of the conversion circuit 18 is m(0.ltoreq.m.ltoreq.9), then (n+0.1 m).mu. will be displayed by the display circuit. Thus, the reading accuracy has been enhanced by tenths of a unit.

It will be apparent that e'.sub.D90 /e'.sub.D0 may be used as n of formula (3). As shown in FIG. 11, it is merely the difference between dividing one-half period corresponding to tan.theta. (0.ltoreq..theta..ltoreq.180) (FIG. 11A) and dividing one-half period corresponding to (1/tan.theta.)(0.ltoreq..theta..ltoreq.18) (FIG. 11B).

Also, the above-described conversion circuit 18 may be designed such that, as already described, the ratio ##EQU10## and values 0-9 corresponding to said ratio are stored in mutually corresponding relationship in a ROM and the ratio from the operational circuit is used as the address designation data of ROM.

Also, four memory circuits may be provided in the regularization circuit 74' and a circuit for detecting the frequencies of the voltages e.sub.0 and e.sub.90 may be provided in the control circuit 71'. The design may be made such that the control circuit 71' causes the average values of E.sub.DOP, E.sub.DON, E.sub.D90P and E.sub.D90N to be separately stored in said four memory circuits when the frequencies of the voltages e.sub.0 and e.sub.90 are high, and such that the regularization circuit 74' is controlled so as to effect regularization only when the frequencies of the voltages e.sub.0 and e.sub.90 have become small or when these voltages have become DC voltages (in the case of an encoder, the condition in which the main scale is stopped). Of course, the block M may be replaced by a computer.

Further, in the foregoing description, an example in which the amplitude fluctuation and the phase fluctuation are eliminated at the same time in the circuit has been shown. The causes of the two fluctuations differ from each other and therefore, if the amplitude fluctuation is suppressed to some extent by constructing the encoder with accurate lattice spacing and without irregularities of cut lines, it will only be required in terms of the circuit to eliminate the phase fluctuation.

The foregoing description has been made by taking a linear encoder as an example, but the phase fluctuations resulting from temperature changes are conspicuous in rotary encoders. Also therefore, the present invention will be particularly effective if used with rotary encoders.

Also, in the above-described example, the counter 8 is designed to count the pulses generated at the rising and falling edges of the rectangular voltages (FIG. 9C) and these pulses are generated for each 180.degree. and therefore, during that time, tan.theta. (or 1/tan.theta.) corresponds to .theta.(0.ltoreq..theta..ltoreq.180) in one to one relationship and no error occurs during the division. But in a case where the counter 8 is designed to count only the pulse generated at the rising edge of the rectangular voltage (FIG. 9C), tan.theta. (or 1/tan.theta.) is such that .theta. corresponding to the same tan.theta. exists in 0-180.degree. and 180.degree.-360.degree.. That is, for example, in the case of FIG. 11A, there are 90.degree. and 270.degree. as .theta. exhibiting tan.theta.=+.infin.. During the division, these must be distinguished and, for example, when .theta. is 0.degree.-180.degree., the sine voltage e.sub.0 is positive and when .theta. is 180.degree.-360.degree., the sine voltage e.sub.0 is negative and therefore, if it is arranged that the sign of e.sub.90 can be applied to the operational circuit, the operational circuit can discriminate between the two due to the difference in sign.