Smooth Pulse Sequence Generator

This invention relates to a smooth pulse sequence generator that is capable of dividing a uniform pulse sequence by virtually any proper, predetermined rational fraction.

The necessity increasingly arises in digital systems to generate a signal having a pulse rate which is related to a reference signal pulse rate by some (unusual) proper rational fraction, while still maintaining synchronism with the reference signal. In many instances, it is a requirement that the pulses of the generated signal be as uniformly spaced as possible within the constraint of synchronism. Sequences of such pulses are called "smooth" in contrast with uniform pulse sequences in which each pulse is separated from its predecessor by a fixed interval. The smooth pulse sequences possess a number of interesting properties in their structure. These properties are discussed in an article entitled "Smooth Pulse Sequences," by A. J. Lincoln et al. in Proceedings of the Third Annual Princeton Conference on Information Sciences and Systems, 1969, pp. 350-354.

A technique commonly employed to form synchronous pulse rate muliples uses a rate multiplier and involves detecting 0 to 1 transitions of stages of a binary counter chain. The rate multiplier technique, although often capable of forming relatively smooth sequences, does not form a true smooth sequence, as is noted in the above-cited article by A. J. Lincoln et al.

More recently, smooth pulse sequences have been generated by employing a complex digital divider arrangement including a plurality of routing circuits coupled in tandem, as disclosed in U.S. Pat. No. 4,034,302, issued to C. J. May Jr., on July 5, 1977. Although the May arrangement generates adequate smooth sequences, it is made up of a plurality of gate circuits which necessarily restrict the circuit to the generation of one fixed sequence. Additionally, this prior smooth pulse sequence generator is somewhat difficult to test and requires substantial energy as compared to modern circuit components. Thus, although this prior smooth pulse sequence generator may be adequate for some applications, it is undesirable for others.

These and other problems are overcome in a smooth pulse sequence generator, in accordance with an aspect of the invention, by storing signal samples defining desired smooth pulse sequence transitions (0 to 1 and 1 to 0) relative to predetermined pulse transitions of a reference signal having a uniform pulse sequence to be divided and by reading out the stored samples in accordance with a prescribed relationship dependent on the reference signal pulse rate.

More specifically, the pulse transition occurrences of the desired smooth pulse sequence are quantized by the period of the reference signal with a quantizer characteristic including rounding to generate a least jittered version of the desired smooth pulse sequence. That is to say, the smooth sequence pulse transitions are restricted to occur at predetermined reference sequence pulse transitions and are rounded to either the previous or subsequent one of the predetermined reference pulse transitions in accordance with prescribed criteria so that the resulting smooth pulse sequence periods are within a predetermined maximum error related to the period of the reference sequence.

One embodiment of the invention includes an address generator and a read only memory (ROM). Signal samples are stored in the ROM defining the smooth sequence pulse transitions relative to the predetermined pulse transitions of the reference signal having the uniform pulse sequence to be divided. The address generator is driven by the reference signal and, in turn, generates a sequence of address signals which, when applied to the ROM, cause the desired smooth pulse sequence to be read out. The smooth pulse sequence is then filtered and shaped to obtain an output signal having a desired, precise uniform pulse sequence which is in synchronism with the reference signal.

The invention will be more fully understood from the following detailed description of an illustrative embodiment thereof taken in connection with the appended figures, in which:

FIG. 1 shows in simplified block diagram form a fractional synthesizer including a smooth pulse sequence generator incorporating the invention;

FIG. 2 graphically illustrates a sequence of waveforms useful in describing the operation of the embodiment shown in FIG. 1;

FIG. 3 is a flow chart illustrating the steps in obtaining the desired pulse transition positions; and

FIG. 4 is a flow chart illustrating the steps taken to generate the smooth pulse sequence samples to be stored in ROM memory locations of FIG. 1.

The fractional synthesizer embodiment of the invention is intended to generate a desired uniform pulse sequence SOUT which is a rational fraction M/N of and is in synchronism with a reference uniform sequence SIN, namely,

where M is the numerator and N is the denominator of the fraction.

For purposes of description, let us assume that the smooth pulse sequence generator embodiment of the invention receives uniform pulse sequence SIN of 16.384 Mbs, produces smooth pulse sequence SSM and, in turn, generates uniform pulse sequence SOUT of 6.176 Mbs. Note that the fraction 6.176.times.10.sup.6 /16.384.times.10.sup.6 can be reduced to the prime fraction M/N=193/512. Therefore, the desired smooth pulse sequence is periodic, producing M=193 output pulses for each N=512 input pulses. The numbers used for purposes of illustration are not entirely arbitrary or fortuitous, e.g., the numerator (193) of the prime fraction is the same as the number of bits per frame of the T1 Carrier (see "The T1 Carrier System" by D. F. Hoth, Bell Laboratories Record, November 1962, pages 358-363). However, as will be evident hereinafter, the principles of the present invention are of general applicability and a smooth pulse sequence generator can be designed in accordance with the invention to divide any given uniform pulse sequence by virtually any predetermined rational fraction.

FIG. 1 illustrates in simplified block diagram form a fractional synthesizer including one embodiment of a smooth pulse sequence generator incorporating the invention.

Accordingly, shown in FIG. 1 is address generator 10 to which reference signal SIN is supplied via terminal 11 and to which signal SYNC is supplied via terminal 12. Reference signal SIN is also supplied to an input of latch circuit 14. Address generator 10 is a digital counter having a predetermined number of stages for generating a sequence of digital address signals corresponding to the number of memory locations employed in read only memory (ROM) 15. As explained hereinafter, ROM 15 has at least N memory locations, in this example, 512. Consequently, counter 10 generates a corresponding sequence of N addresses, i.e., 0 to N-1, in this example, 0 to 511. Thus, address generator 10 essentially divides reference signal SIN by N. The address signals are supplied in well known fashion to ROM 15. Signal SYNC is employed to synchronize address generator 10 to other system waveforms and may not be necessary in certain applications.

ROM 15 may be any of a number of memory units now commercially available. As indicated hereinafter, ROM 15 has at least N one bit memory locations. Signal bits stored in ROM 15 define pulse transitions in desired smooth pulse sequence SSM. Generation of the pulse transition positions to obtain a least jittered smooth pulse sequence is described below. ROM 15 responds to the supplied address signals to output the signal samples, i.e., logical 1 or 0, stored in the memory locations in sequence as driven by reference sequence SIN. The output bits from ROM 15 are supplied to latch 14.

Latch 14 is employed to compensate for delays experienced in address generator 10 and ROM 15. To this end, the pulse transitions outputted from latch 14 are synchronized to correspond to transitions of SIN in a manner which will be apparent to those skilled in the art. The output of latch 14 and also ROM 15 is at least jittered version of desired smooth sequence SSM and is supplied to bandpass filter 16.

Bandpass filter 16 is employed to extract the desired uniform sequence component, i.e., 6.176 Mbs, from smooth sequence SSM. To this end, a two-pole monolithic crystal filter is used, with a 6 KHz, 3 dB passband centered at 6.176 MHz. An output of filter 16 is supplied to pulse shaper 17 to generate the desired uniform sequence SOUT having, in this example, a 6.176 Mbs regular pulse train with 50 percent duty cycle.

The 6.176 MBs pulse train is readily divided by 4 to obtain the well known 1.544 Mbs T-Carrier pulse rate.

Uniform pulse sequence SIN of 16.384 Mbs is illustrated in FIG. 2 having period t. Signal SYNC is also shown, and in this example is the 8 KHz T-Carrier SYNC signal. SOUT is a desired uniform pulse sequence which is M/N of SIN, or, in this example, 6.176 Mbs and has a period of T. To obtain the desired uniform pulse sequence having period T, desired pulse transitions (0 to 1 and 1 to 0) should occur as shown. However, since the division of SIN is a prime fraction, pulse transitions are only allowed to occur, in this example, at positive going, i.e., 0 to 1, pulse transitions of SIN. Consequently, the desired pulse transitions must be rounded to the allowed transitions pulse resulting in smooth sequence SSM having a maximum error .+-.t/2. Accordingly, appropriately logical signals are stored in memory locations of ROM 15 as shown to realize the desired least jittered smooth pulse sequence SSM. It should be noted that the allowed transition need not be restricted to the positive transitions of SIN and any other desirable arrangement may be used, as will be apparent to those skilled in the art.

To realize a particular fractional synthesis operation, factors to be considered are size of ROM 15, number of pulse transitions to be synthesized and the phase relationship with other signals employed. For a fraction M/N, the size of ROM 15 is at least N.times.1 memory locations. Minimizing M/N to a prime fraction minimizes the size of ROM 15.

The procedure for generating the digital signals to be stored in ROM 15 includes:

Computing the desired pulse transition occurrences (FIG. 2) for a desired uniform pulse sequence in interval Nt.

Computing the allowed pulse transition occurrences (FIG. 2) by rounding the desired pulse transition occurrences so that the maximum error from each of the desired pulse transition occurrences is limited to .+-.t/2. This results in an array of ROM 15 memory locations having stored signals representing 0-to-1 and 1-to-0 transitions.

Assigning the computed logical signals to ROM 15 memory locations in a predetermined address sequence beginning with ROM 15 memory location address 0 through address N-1.

FIG. 3 shows a flow chart of the process for determining the desired pulse transition occurrences.

After initialization, the first desired pulse transition is computed via

where m is the desired transition number,

and beginning at

Each TR(m) is a non-integer number representative of a corresponding transition occurrence of the desired uniform pulse sequence normalized to period t of uniform pulse sequence SIN being divided.

The pulse transitions of smooth pulse sequence SSM (FIG. 2) are computed by rounding with 50% probability the desired pulse transition occurrences. That is, if the desired pulse transition occurs at a position in relation to the allowed pulse transitions which is less than t/2 the rounding is to the preceding allowed pulse transition and if the desired pulse transition occurs at a position equal to or greater than t/2, the rounding is to the next subsequent allowed pulse transition. Consequently, the addresses of memory locations of the pulse transition occurrences are represented by an array of integers

where {} indicates rounding.

FIG. 4 is a flow chart of a process for generating the bit pattern stored in memory locations of ROM 15 to obtain desired smooth pulse sequence SSM. Memory locations are represented by n, namely

and the corresponding memory location content is represented by R(n), namely,

Then, starting at a convenient transition n=A(m)=0, R(O)=b is chosen either to be a logical 0 if a 1-to-0 pulse transition is to occur or to be a logical 1 if a 0-to-1 pulse transition is to occur. ROM 15 address n is advanced and the memory signal content remains the same until the next transition in smooth pulse sequence SSM being generated is reached. That is to say, the memory locations of ROM 15 between pulse transitions of smooth pulse sequence SSM have bits stored therein the same as the previous transition.