Synchronous Demodulator for Multi-Phase PSK Signal

The present invention relates to a PSK (phase shift keying) demodulator, and more particularly to a PSK demodulator having a simplified carrier wave reproducing circuit.

A conventional, demodulator of this kind has a carrier wave reproducing circuit for reproducing a carrier wave from an N-phase (N=2.sup.n, n being a positive integer) PSK-modulated carrier wave, and an N-phase PSK-demodulating circuit for providing demodulated signals by detecting the PSK-modulated carrier wave with this reproduced carrier wave. Such a PSK demodulating circuit generally includes as its components n phase detectors and n level decision circuits together with (n-1) phase shifters. A first example of conventional carrier wave reproducing circuits (see Reference 1, William C. Lindsey et al., Telecommunication Systems Engineering, 1973, Prentice-Hall, pp. 55-81) comprises an N-fold frequency multiplier for frequency-multiplying by N an N-phase PSK carrier wave to generate an unmodulated carrier wave having a frequency N times as high as the carrier wave frequency, a phase synchronizing circuit or a PLL (phase locked loop) circuit for providing an unmodulated wave phase-synchronized with this unmodulated carrier wave, and a 1/N frequency divider for dividing the phase-synchronized wave by N to generate the carrier wave. A similar circuit is disclosed in the U.S. Pat. No. 3,835,404. Such wave reproducing circuit requires circuits operable in a frequency band of Nxfc higher than the carrier wave frequency band fc of the N-phase PSK carrier wave. Therefore the circuits have to meet increasingly severe requirements with an increase in number of phases, resulting in a greater cost and sometimes in the unavailability of elements operable in the required high frequency band. These disadvantages may be obviated by converting the N-phase PSK carrier wave into a lower frequency band by means of a suitable local oscillator and then supplying the converted carrier wave to the aforementioned first carrier wave reproducing circuit to enable this circuit to operate in the carrier wave band. This circuit composition, however, requires a separate local oscillator, in particular one with a small frequency drift, i.e., a highly stable local oscillator, to minimize the stationary phase error in the PLL circuit (including a voltage-controlled oscillator, a phase comparator and a low pass filter), inviting an increase in cost.

A second example of conventional carrier wave reproducing circuits (see Reference 2, U.S. Pat. No. 4,110,706) consists of an N-phase PSK modulating circuit involving n phase detectors which inversely modulates an N-phase PSK carrier wave with a demodulating signal and (n-1) phase shifters, a phase-synchronizing circuit (or a PLL circuit) for generating a carrier wave phase-synchronized with the output of this modulating circuit, and a delay circuit for adjusting the delay time on each path. This carrier wave reproducing circuit, wherein the delay achieved by the delay circuit varies with the ambient temperature and other factors as stated in the reference, is incapable of proper phase synchronization. Therefore, the PSK demodulating circuit is unable to demodulate correct signals from the PSK-modulated carrier wave. There is another disadvantage that the structure of the PSK-modulating circuit enlarges with an increase in number of phases. The carrier wave reproducing circuit of the Costas loop has a similar shortcoming.

The objective of the present invention therefore is to provide a simple-structured and highly stable PSK demodulator cleared of the above-stated disadvantages.

In accordance with this invention, there is provided a PSK demodulator comprising a first means for reproducing a carrier wave from an N-phase (N=2.sup.n, n being a natural number) PSK-modulated carrier wave and an N-phase PSK demodulating means for reproducing n strings of demodulated signals from the PSK-modulated carrier wave in response to the PSK-modulated carrier wave and the reproduced carrier wave, wherein the first means consists of a second means for generating the carrier wave phase-synchronized with an unmodulated carrier wave; a third means for dividing the frequency of the reproduced carrier wave by two to generate a frequency-divided carrier wave, and a fourth means for generating the unmodulated carrier wave in response to the PSK-modulated carrier wave and the frequency-divided carrier wave, wherein the fourth means consists of n fifth means connected in series, and wherein each of the fifth means consists of a sixth means for frequency-mixing the PSK carrier wave or the output wave of the fifth means of the preceding stage with the frequency-divided carrier wave, and a seventh means for frequency-multiplying the output of the sixth means and supplying the frequency-multiplied wave to the input of the fifth means of the following stage or that of the second means.

Further features and advantages of the invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram illustrating a two-phase PSK demodulator in accordance with this invention;

FIG. 2 is a block diagram illustrating a four-phase PSK demodulator in accordance with this invention; and

FIG. 3 is a block diagram illustrating an N-phase PSK demodulator in accordance with this invention.

In FIG. 1, a two-phase PSK demodulator of the present invention is composed of a two-phase PSK demodulating circuit 1 and a carrier wave reproducing circuit 2. The demodulating circuit 1 further comprises a phase detector 11 and a level decision circuit 12, and the carrier wave reproducing circuit 2 consists of a frequency converter section 3, a PLL circuit 4 and a 1/2 frequency divider 5. The frequency converter section 3 is made up of a mixer (MIX) 31, a band pass or low pass filter (LPF) 32, a frequency doubler 33 and a band pass filter (BPF) 34. The PLL circuit 4 is made up of a phase comparator (PC) 41, a low pass filter (LPF) 42 and a voltage-controlled oscillator (VCO) 43. A two-phase PSK-modulated carrier wave fed to a terminal 100 is supplied to the demodulating circuit 1 and carrier wave reproducing circuit 2. The PSK carrier wave is detected by the phase detector 11 with a carrier wave from the carrier wave reproducing circuit 2. This detected signal is identified by the level decision circuit 12 to supply a demodulated binary signal to a terminal 101.

The operation of the carrier wave reproducing circuit 2 will be described hereunder, with the carrier frequency of the two-phase PSK-modulated carrier wave S.sub.i of the carrier wave reproducing circuit 2 being represented by w.sub.i and the output frequency of the VCO 43 by W.sub.o. The output of the VCO 43 is frequency-divided by the frequency divider 5 to have a frequency of W.sub.o /2. The MIX 31, in response to the output of the frequency divider 5, converts the frequency of a demodulated signal S.sub.i into frequencies w.sub.i .+-.w.sub.o /2. The LPF 32 filters the signal having a frequency of w.sub.i -w.sub.o /2 and then supplies it to the frequency doubler 33 to provide an unmodulated carrier wave having a frequency of 2w.sub.i -w.sub.o. The output of this freqency doubler 33 is fed to one of the input terminals of the PC 41 by way of the BPF 34, and to the other input terminal is fed the output of the VCO 43. This PC 41 compares the phases of these inputs, and gives a beat signal of a frequency (2w.sub.i -w.sub.o)-w.sub.o =2(w.sub.i -w.sub.o)=2w.sub.e. That is to say, the phase difference w.sub.e between the input PSK carrier wave and the output of the VCO 43 emerges doubled in the output of the PC 41. Since this PLL circuit 4 is exactly identical in structure with any conventional PLL circuit except that the detection sensitivity in the PC 41 is doubled, its synchronization process is exactly the same as in any conventional PLL circuit. When this PLL circuit 4 is brought to synchronism, 2w.sub.e becomes equal to 0 and consequently w.sub.o equal to w.sub.i, with the result that the PLL circuit 4 provides the carrier wave identical to that of the input PSK carrier wave. In this way, the PLL circuit 4 can operate at the same frequency as that of the PSK carrier wave.

Referring to FIG. 2, a four-phase PSK demodulator of the present invention consists of a four-phase PSK demodulating circuit 6 and a carrier wave reproducing circuit 7. The demodulating circuit 6 further is composed of phase detectors 61 and 62, a .pi./2 phase shifter 63 and level decision circuits 64 and 65; and the carrier wave reproducing circuit 7, of the PLL circuit 4, the frequency divider 5 and frequency converter sections 71 and 72. Each of the frequency converter sections 71 and 72 has exactly same structure as the frequency converter section 3 shown in FIG. 1. A four-phase PSK modulated carrier wave fed to a terminal 200 is supplied to the four-phase PSK demodulating circuit 6 and the carrier wave reproducing circuit 7. The phase detectors 62 and 61 detect the PSK-modulated carrier wave with the carrier wave from the reproducing circuit 7 and that phase-shifted by .pi./2 by the phase shifter 63, respectively. These detected signals are identified by the level decision circuits 64 and 65, and two strings of demodulated binary signals are supplied to terminals 201 and 202, respectively.

In the carrier wave reproducing circuit 7, the carrier frequency of the input four-phase PSK-modulated carrier wave S.sub.i being represented by w.sub.i and the output frequency of the PLL circuit 4 by w.sub.o, the output of the mixer (which corresponds to the MIX 31 in FIG. 1) included in the frequency converter section 71 is a four-phase PSK-modulated carrier wave having a frequency of w.sub.i -w.sub.o /2, while the output of the frequency doubler (which corresponds to the frequency doubler 33 in FIG. 1) in the frequency converter section 71 is a two-phase PSK-modulated carrier wave having a frequency of 2w.sub.i -w.sub.o. The outputs of the mixer and frequency multiplying circuit in the other frequency converter section 72 are a two-phase PSK wave having a frequency of 2w.sub.i -3/2 w.sub.o and an unmodulated carrier wave having a frequency of 4w.sub.i -3w.sub.o, respectively. Therefore, the output of the phase comparator in the PLL circuit 4 is a beat signal of a frequency 4w.sub.i -3w.sub.o -w.sub.o =4(w.sub.i -w.sub.o)=4w.sub.e and, as in the circuit of FIG. 1, the PLL circuit 4 achieves proper synchronization to make w.sub.i equal to w.sub.o. As is obvious from the foregoing description, this circuit operates in or below the carrier wave frequency band.

In FIG. 3, an N-phase (N=2.sup.n) PSK demodulator of this invention comprises a N-phase PSK demodulating circuit 8 of known structure and a carrier wave reproducing circuit 9. The carrier wave reproducing circuit 9 consists of a PLL circuit 4, a 1/2 frequency divider 5 and n frequency converter sections 91 through 93 connected in series, and each of the frequency converter sections 91 through 93 has the same structure as the frequency converter section 3 shown in FIG. 1. In the demodulating circuit 8 is demodulated an N-phase PSK-modulated carrier wave applied to a terminal 300 with a carrier wave from the carrier wave reproducing circuit 9, and n strings of demodulated binary signals are supplied to terminals 301, 302 and 303. This carrier wave reproducing circuit 9 operates in the same manner as the aforementioned reproducing circuits 2 and 7, and the output signal of the frequency converter section 91 of its first stage is a 2.sup.(n-1) -phase PSK carrier wave having a frequency of 2w.sub.i -w.sub.o. The output of the frequency converter section 92 of its second stage is a 2.sup.(n-2) -phase PSK carrier carrier wave having a frequency of 4w.sub.i -3w.sub.o. Similarly, the output of the frequency converter section 93 of its nth stage is an unmodulated carrier wave having a frequency of Nw.sub.i -(N-1)w.sub.o. Accordingly, the output of the phase comparator in the PLL circuit 4 is a beat signal of a frequency N(w.sub.i -w.sub.o)=Nw.sub.e and, as in the foregoing description, the PLL circuit 4 achieves proper synchronization to make w.sub.i equal to w.sub.o.

As is obvious from the description hitherto made, the carrier wave reproducing circuit in the demodulating circuit of the present invention has the following advantages:

(1) Irrespective of the number of phases N, the whole circuit operates in or below the carrier wave frequency band. Therefore, unlike in the first conventional carrier wave reproducing circuit referred to above, no increase in number of phases could make the circuit composition any more difficult.

(2) No separate oscillator is needed as a source of local oscillation for frequency conversion. This circuit, moreover, is immune from the stationary phase error in the PLL circuit, attributable to the frequency drift of the local oscillator.

(3) Since the absence of a delay circuit, unlike in the second conventional carrier wave reproducing circuit referred to above, prevents synchronization with a wrong phase, correct signals can be demodulated from the input PSK carrier wave.

(4) Because the sensitivity of the phase comparator rises with an increase in number of phases, the stationary phase error attributable to the frequency drift of the VCO of the carrier frequency drift of the input PSK wave control can be suppressed.