Silicon Rich Refractory Silicides as Gate Metal

This invention relates to semiconductor integrated circuits.

Semiconductor integrated circuits, as well as the design, manufacture, and operation of such circuits, are well known in the art. Common to such circuits is an epitaxially grown single crystal film in which various regions of different conductivity type are interconnected by multiple layers of patterned electrically conducting material.

A variety of electrically conducting material is available for implementing the layers. Gold, copper, aluminum, Polycrystalline Silicon (or "polysilicon"), and various metal alloys, for example, are all suitable to some extent. On the other hand, each has its drawbacks as is well known in the art.

In large scale integration (LSI)-metal-oxide-semiconductor (MOS)-field effect transistor (FET) technology, polysilicon has become the standard material for the conducting layer closest to the epitaxial film. Typically, the polysilicon layer is a first layer separated from a second electrically conducting overlay by an insulating layer typically of silicon dioxide.

Polysilicon exhibits relatively high resistivity and the lengths of polysilicon paths are limited as a consequence. For example, various functional areas in an integrated circuit chip cannot be interconnected together directly by polysilicon. Rather, the connections from each area are brought out to aluminum bus bars formed from the second overlay. Similarly, LSI high speed circuits require high conductivity input-output lines. The requirement results in the exclusion of polysilicon as a material for such use. Aluminum power lines are needed and this often requires aluminum bonding pads within the chip. The additional aluminum areas, are, essentially, wasted space and parallel aluminum conductors yield problems.

Copending application Ser. No. 974,378 for Levinstein, Murarka, and Sinha, filed Dec. 29, 1978 discloses the high conductivities of silicides used with a thin layer of polysilicon. The method for fabrication described therein involved depositing a layer of Ti or Ta on a polysilicon layer. The resulting structure was then sintered at about 900 degrees C. to form TiSi.sub.2 or TaSi.sub.2. The excess silicon from the polysilicon layer allowed a later oxidation to SiO.sub.2.

In order to improve resolution of patterns in layers of material on chips with increasingly higher packing densities, and therefore, increasingly narrower apertures, it is advantageous to reduce the thickness of the layers as well. One route to this goal would be the elimination of the high-resistance polysilicon layer completely. However, in the above-mentioned application of Levinstein, Murarka and Sinha, it is stated that the polysilicon layer is necessary as a source of silicon for the reduction of the metal to silicide and for the subsequent oxidation to form SiO.sub.2. It is also stated that in the absence of the polysilicon, the silicide forming layer will react with the underlying gate oxide to form an undesirable oxide overlay which cannot be etched. A problem thus exists as to the realization of increasingly thinner layers in which patterns are formed for realizing increasingly higher packing density devices.

The solution to the above problem was found through studies of the silicides used on a polysilicon layer as a gate metal. It was found that silicon-rich silicide, formed by sintering a cosputtered alloy with silicon to metal (Ti or Ta) atomic ratio of three in the as-deposited film, is stable even on the gate oxide and in oxidizing mediums. In addition, the resistivity and stress of Si-Ti alloys is a minimum for Si/Ti ratio nominally equal to three. Such a silicon-rich silicide can be used even without the polysilicon layer and leads to a stable, low resistivity gate.

Thus, the invention comprises a semiconductor integrated circuit including a single crystal semiconductor layer coated by an SiO.sub.2 layer and including a lamellate overlay comprising first and second electrically conducting layers separated by an electrically insulating layer. The structure is characterized in that the overlay includes a layer of silicon-rich silicide deposited directly on the gate oxide without a layer of polysilicon as a buffer between the gate oxide and the silicide layer. The excess silicon, present as interstitials within the lattice of the silicide, replaces the polysilicon layer as a source of silicon for oxidation to SiO.sub.2.

FIG. 1 is a projection view of a semiconductor integrated circuit chip assembly;

FIGS. 2 and 3 are cross sectional views of portions of the chip shown in FIG. 1; and

FIG. 4 is a block diagram of a process for making the chip of FIG. 1.

FIG. 1 shows a projection view of a semiconductor chip assembly. The assembly includes a substrate 11. The substrate comprises layers 12 and 13 sandwiching a sunburst pattern 15 of electrical conductors therebetween. Layer 12 includes a centrally disposed square aperture 16 which exposes the inner ends of the conductors of the sunburst pattern.

A semiconductor integrated circuit chip 20 is mounted on the portion of layer 13 exposed by aperture 16. Typically, chip 20 includes electrical lands 22 at its periphery for external connection to the exposed inner ends of the electrical conductors of the sunburst.

An integrated circuit chip has multiple functional areas defined therein. These areas are interconnected with one another and to lands 22 by conductors defined by patterned layers of electrically conducting material formed on the surfaces of chip 20. These layers are electrically insulated from one another and from the epitaxial layer of the chip typically by silicon dioxide layers.

Of course, contact between portions of the conducting layers and various regions of opposite conductivity in the epitaxial layer require through connections. The term "through connection" herein refers to an electrically conducting path from one layer of conducting material to another as to the epitaxial layer through other layers separating the layers from one another. When through connections are made, electrical continuity is achieved between the areas of the chip and the externally exposed ends of the conductors of the sunburst pattern. The design permits external connection even with a closure member (not shown) over opening 16 secured in place.

Freeform area 30 of FIG. 1 is a representative area of chip 20 and it is to this area that we now turn our attention. FIGS. 2 and 3 show area 30 partially in cross section to expose the plurality of layers from which the chip is constituted. The bottom layer 40 as shown, illustratively, comprises silicon on which an electrically insulating layer 41 of silicon dioxide is formed typically by growing the layer by heating in an oxidizing atmosphere. This step is represented by the top block in FIG. 4. Layer 40 comprises an epitaxially grown layer 10-20 microns thick. In accordance with this invention, the layer 41 is 1000 Angstroms or thinner.

The next layer 42 comprises a silicon-rich silicide, typically of titanium or tantalum. In, for example, the case of titanium, silicon-rich titanium silicide is cosputtered on the gate oxide film. The cosputtering step is indicated by the second block in FIG. 4. The nominal silicon to titanium ratio, controlled by independently controlling the deposition rates of Si and Ti from two independent targets, is Si/Ti=3. Typically, a 2500 Angstrom silicide film is deposited. The alloy is then sintered in hydrogen at 900 degrees C. for 30 minutes as indicated by the third block in FIG. 4.

The silicide film that results has a sheet resistance of less than 1.OMEGA./[ ]. The compound formed can be thought of as TiSi.sub.2+x. Experiments in which silicon and titanium were cosputtered in different ratios show that for Si/Ti greater than two, TiSi.sub.2 is the only compound formed. It is thought that the excess silicon is present in the TiSi.sub.2 lattice as interstitials. For a film with an as desposited Si/Ti ratio of 3, Rutherford backscattering composition for the sintered alloy is TiSi.sub.2.5. This would means four excess silicon atoms per unit cell of TiSi.sub.2. The fact that this composition shows the lowest stress and resistivity indicates a range of solid solubility of Si in TiSi.sub.2. The compressive stress due to the excess silicon reduces the tensile stress produced by the volume change during silicide formation. With alloys cosputtered on oxide, for Si/Ti<2, no silicide is formed, and resistivity is high. For Si/Ti>3, the silicon concentration is higher than that required for TiSi.sub.2.5, and resistivity increases with increasing silicon concentration.

A layer of self-passivating thermal oxide is formed over the TiSi.sub.2+x layer by heating in an oxidizing atmosphere as indicated by the fourth block in FIG. 4. A field oxide of phosphorous-doped SiO.sub.2 is then deposited and patterned by plasma etching as indicated by the fifth and sixth block of FIG. 4. Following patterning of this SiO.sub.2 layer 43, a layer 44 of Al, 0.5 percent Cu, from 7000 Angstroms-1, micron thick is deposited by sputtering. The aluminum layer is etched in a plasma of CCl.sub.4, BCl.sub.3 and He. The aluminum deposition and etching steps are represented by the last two blocks in FIG. 4.

The following is a specific example of an IGFET fabricated with the above-described silicon-rich silicide system.

The starting material is a substrate of single crystal Si, having a (100) orientation and doped with boron to a resistivity of 7 ohm cm. The Si-substrate is thermally oxidized at 1000 degrees C. for 30 minutes in a dry oxygen ambient to grow an oxide 350 Angstroms thick. Over this oxide, a thin film of Si.sub.3 N.sub.4 is deposited by chemical vapor deposition from a mixture of silane and ammonia at 680 degrees C. A layer of photoresist is defined into a pattern using standard photolithographic techniques so as to leave the resist over active device areas of the wafer. The Si.sub.3 Ni.sub.4 is etched from the nonactive "field" areas thus defined, using an rf-glow discharge in a mixture of CF.sub.4 and O.sub.2. The etched areas are implanted with boron ions accelerated to a voltage of 30 kV and up to a total dose of 1.5.times.10.sup.13 ions/cm.sup.2. This step leads to the formation of a heavily p-doped channel stop with a high threshold voltage in the nonactive field areas. The resist is then stripped in an oxygen plasma and the exposed areas of thin oxide in the field region are etched in a solution of buffered HF down to bare Si. With the active areas masked by the Si.sub.3 N.sub.4 film, the wafer is subjected to a mixture of 10 percent O.sub.2 +90 percent N.sub.2 at 1100 degrees C. for 20 minutes to drive in the implanted B ions and then to a steam ambient at 1000 degrees C. for 430 minutes to form a field oxide, 10,000 Angstroms thick. The masked areas are cleaned by successively etching in buffered HF, hot H.sub.3 PO.sub.4 (180 degrees C.) and buffered HF down to Si in the active gate area. Gate oxide of less than 1000 Angstroms is grown at 1000 degrees C. in a mixture of O.sub.2 +3 percent HCl for 42 minutes. The oxide is annealed, in situ, for one-half hour in Ar also at 1000 degrees C. to provide optimum electrical characteristics of the Si/SiO.sub.2 interface. In order to adjust the threshold voltage of the MOSFETs, the Si in the gate areas is implanted with B at 3 Kev to a dose of 5.times.10.sup.11 cm.sup.-2.

A layer of silicon-rich titanium silicide, 2500 Angstroms thick, is deposited by cosputtering on the gate oxide with a silicon to titanium atomic ratio of three. The alloy is then sintered in hydrogen at 900 degrees C. for 30 minutes. The sheet resistance of the resulting silicide film is less than 1 ohm per square cm.

A desired pattern of a masking layer consisting of photoresist is formed over the TiSi.sub.2+x by using standard lithographic techniques. The silicide layer is etched in a plasma of CF.sub.4 +8 percent O.sub.2 at a pressure of 150 millitorr and at a power of 200 watts and at a temperature greater than 70 degrees C. The resist is removed and the wafer is cleaned.

Source and drain areas of the MOSFETs are formed by ion-implanting arsenic at 30 Kv and a dose of 7.times.10.sup.15 cm.sup.-2 through the thin oxide layers. The previously defined areas of TiSi.sub.2+x and thick oxide in the field region act as a mask against arsenic implantation. A thin layer of oxide is grown over the silicide areas in steam at 1000 degrees C. for 10 minutes. The top of the wafer is coated with photoresist and SiO.sub.2 is etched off the back of the wafer in a buffered HF solution.

A 1.mu. thick layer of phosphorous doped SiO.sub.2 (7 percent P-glass) is deposited using a reaction of SiH.sub.4, O.sub.2 and PH.sub.3 at 480 degrees C. This oxide is flowed at 1100 degrees C. for 15 minutes in nitrogen to achieve a smooth topology. The wafers are gettered at 1000 degrees C. in PBr.sub.3 for 30 minutes to help remove unwanted heavy metal impurities from the active surface regions of the wafer to the back of the wafer. Windows (apertures) are opened in the P-glass down to diffused Si in the source and drain areas and to the TiSi.sub.2+x gate. The wafers are annealed at 700 degrees C. in H.sub.2 for 30 minutes to reduce slow-trapping instability in the gate oxide.

A top metallization layer of Al, 0.5 percent Cu, 7000 Angstroms thick, is deposited using a sputter gun. Using standard techniques, the metal is patterned and etched to form contacts, interconnections, and bonding pads. The top of the wafer is coated with photoresist and then the phosphorous-doped Si-layer, which formed on the back of the wafer during gettering, is removed by plasma etching in CF.sub.4 +8 percent O.sub.2 at 50 watts for 20 minutes. Subsequently, the resist is stripped in an O.sub.2 plasma at 100 watts for 10 minutes. The wafers are annealed in H.sub.2 at 450 degrees C. for one-half hour to assure ohmic contacts and to anneal out surface states in the gate oxide. A passivation layer of 1.mu. thick Si-N is deposited by plasma enhanced chemical vapor deposition from a mixture of SiH.sub.4, NH.sub.3 and Ar at 300 degrees C. Bonding pad areas are opened by etching Si-N in a CF.sub.4 /O.sub.2 plasma.

The back of the wafer is cleaned and a film of Ti followed by Au is deposited by sequential evaporation. The devices are tested, separated into chips and packaged by bonding the back of the chip to a metallized mini ceramic with an Au, Si eutectic alloy, and by bonding Au-wires to the Al bonding pads and to metallized interconnections on the package leading to dual-in-line pins. The hermetic packaging is completed by soldering a closure member (not shown in FIGS.) in a dry N.sub.2 ambient.