US 4,336,601 AGrant

Rewritable Programmable Logic Array

Issue Date:1982-06-22

•4 Claims

•13 Drawing Sheets

Abstract

A Rewritable Programmable Logic Array (R-PLA) which can alter dynamically logic functions during processing by loading a word pattern of bit personalities to realize the specific logic functions into memory cells of Current Mode Logic (CML) is constructed by splitting a conventional Random Access Memory (RAM) of CML into two parts (SEARCH and READ parts). Each cell structure of the new R-PLA is identified with that of the conventional RAM, differing from a complicated cell structure of a flip-flop and AND gate proposed in the past. SEARCH and READ parts of the new R-PLA can operate AND functions without using special AND gates in each cell in the READ mode and can enter WRITE data from a word direction in the WRITE mode. Each part of the R-PLA comprises a two-channel selector to select READ inputs or WRITE inputs, a CML memory array and sense-drive circuits. The selector and the sense-drive circuits are controlled by means of READ/WRITE control circuits. The logic-in-memory for the AND functions on the array can be conducted by using one of multi-emitters of a transistor in each CML memory cell and an emitter of a reference transistor in each of the sense-drive circuits in the READ mode of the new R-PLA. The new READ/WRITE control circuits let a word pattern of the bit personalities load into the CML memory cells in the word direction.

Metadata

Inventor

Mamoru Tanaka

Application Information

Application Number:US 0550094

Filing Date:1979-07-05

Priority Date:1978-07-04

Art Unit:237

Classifications

IPC:

H03K 1920G11C 1500

Field of Search:

364307340328200 MS File;900 MS File;716207166 R92

Patent Drawings (13 sheets)

Description

Background of the Invention

This invention relates to a programmable logic array which can be used as a memory circuit for performing a combinational circuit or a sequential circuit and particularly to a rewritable programmable logic array which can be applied to various circuits as an associative memory or functional memory.

In the light of rapid development of LSI semiconductor memories, design engineers have been prompted to apply similar technology also to the design of general purpose logic networks capable of performing both combinational and sequential logic functions. Though the use of memory devices as Random Access Memory (RAM) or Read Only Memory (ROM) to implement logic, it is pointed out that as the number of input variables n grows larger the memories are inefficient in providing 2.sup.n word lines to implement n variable function regardless of the complexity of the function [see reference 1 cited in the appendix].

A programmable logic Array (PLA), which generally consists of a SEARCH array performing AND function and a READ array performing OR function, has been recognized as a memory device to realize combinational and sequential logic networks [see reference 1-3 cited in the appendix].

A brief description of a drawing of a prior art device is shown as follows.

FIG. 1 shows a diagram of a general Programmable Logic Array (PLA).

FIG. 2 is a 2-bit adder used as an example circuit of PLA representation.

FIG. 3 depicts a PLA representation of the 2-bit adder in FIG. 2.

FIG. 4 represents a read-only type of a bipolar PLA and FIG. 5 shows a diagram of a read/write type of prior art PLA with the complexity of the cell construction.

As shown in FIG. 1, a Programmable Logic Array (PLA) is based on the so-called naked PLA which consists of a SEARCH array and a READ array. When p-bit decoders are used as the bit partitioning networks in a general symmetric PLA, the number of the partitioned bit lines, N, and the number of cells, S.sub.p, are given respectively as follows:

Here, n,m and l are the number of input lines, output lines and word lines respectively in the PLA.

As the circuit example for the PLA representation, the 2-bit adder shown in FIG. 2 is used in this invention. The 2-bit adder accepts four input variables X.sub.0, X.sub.1, X.sub.2 and X.sub.3, and generates outputs F.sub.0, F.sub.1 and C.sub.out, which are the zero-order and first-order sums and a carry respectively. The three Boolean equations for F.sub.0, F.sub.1 and C.sub.out may be written as

where the symbols .multidot., V, .crclbar. and .sup.- represent the operations of AND, OR, EXCLUSIVE-OR and INVERT respectively.

The PLA representation of the 2-bit adder is shown in FIG. 3. Two 2-bit decoders are used as the bit partitioning networks.

Let B.sub.i (i=0,1, . . . ,7), W.sub.j (j=0,1,2,3) and Z.sub.k (k=0,1,2) be Boolean variables for bit lines b.sub.i, word lines w.sub.j and output bit lines z.sub.k respectively, W.sub.j and Z.sub.k are given by ##EQU1##

Compared with the RAM or the ROM, the PLA is expected to be more efficient in its silicon area requirements, though the cell number of the PLA varies drastically as a function of the partitioning for the input decorders [see reference 1 cited in the appendix].

Historically, a read-only type of PLA, which generates specific Boolean output functions by open-circuiting or short-circuiting some cells at intersections of bit lines and word lines on the array, has been widely used in the market as a Field-PLA or a Mask-PLA.

But, for a read/write type of PLA, the ideal memory cell to perform the `bit personality` to realize specific logic functions [see reference 1 cited in the appendix] and to be rewritable easily is not yet available, though the concepts are already proposed as a functional memory [see reference 2 cited in the appendix] with writable storage cells capable of holding a binary 1, a binary 0 and a DON'T CARE, or a PLA [see reference 1 cited in the appendix] with use of small memory cell and NAND gate at each intersection of bit lines and word lines. The latter PLA is shown in FIG. 5. But, such a PLA is inefficient in the complexity of the cell constructions And interconnections. Also, I proposed in Japanese patent application No. 53-78411 filed on June, 1978 that a rewritable PLA can be constructed by using simplified Current Mode Logic (CML) memory cells. But, the disadvantage of the rewritable PLA is in that in the SEARCH part bit personalities to realize specific logic functions can not be written from the work direction.

Summary of the Invention

An object of this invention is to provide a rewritable PLA of CML type in which bit personalities to specific logic functions can be written and changed word by word.

The Rewritable PLA (R-PLA) is mainly consisted of a SEARCH part performing NOR function and a READ part performing NOR function. The two parts have the same configurations. That is, the SEARCH (READ) part consists of a two-channel selector with a READ input and a WRITE input, a memory array with bistable Current Mode logic (CML) memory cells at all intersections of bit (word) lines and pairs of sense-drive word(bit)lines, and a set of sense-drive circuits with a DRIVE input and READ output. The READ output lines of the SEARCH part are connected to the READ input lines of the READ part. The input bit partitioning networks [see reference 1 cited in the appendix] are connected to the READ input lines of the SEARCH part. READ/WRITE control circuits and a WRITE address decoder are added in the R-PLA.

For the R-PLA, bit personalities (contents of the CML memory cells) to realize specific logic functions are easily loadable and dynamically changed word by word during processing. The R-PLA is densed pachaged by means of the simplicity of the cell constructions and the regularity of interconnections. The R-PLA is constructed by splitting the conventinal Random Access Memory (RAM) using CML memory cells into two parts. Therefore, each cell structure of the new R-PLA is identified with that of the conventinal RAM. Because of the identification, the comparison for the number of cells between the new R-PLA and the RAM becomes possible according to historical discussions of the PLA and the memory in [see reference 1 cited in the appendix].

The R-PLA will be applicable as a maskable associative memory or a functional memory to several digital systems, especially to a computer with a dynamic microprogramming [see reference 4 cited in the appendix].

Brief Description of the Drawings

FIG. 6 shows a block diagram of the Rewritable PLA (R-PLA) disclosed in this invention;

FIG. 7 shows a detail diagram of the R-PLA disclosed in this invention;

FIG. 8 shows a representation for the READ mode of the R-PLA disclosed in this invention;

FIG. 9 shows a timing chart for the WRITE mode of the R-PLA disclosed in this invention;

FIG. 10 shows a representation for the WRITE mode of the R-PLA disclosed in this invention;

FIG. 11 shows a section of the SEARCH part of the R-PLA disclosed in this invention;

FIG. 12 shows an operating voltage level relations of the R-PLA disclosed in this invention;

FIG. 13 shows a maskable associative memory realized by using the R-PLA disclosed in this invention.

Detail Description of the Invention

Now in detail are discussed the architecture and READ/WRITE operations of the Rewritable Programmable Logic Array (R-PLA) of CML type in which bit personalities to realize specific logic functions can be changed from the word direction.

First, the architecture and logical operations of the R-PLA are discussed.

As shown in the block diagram of FIG. 6, a general R-PLA disclosed in this invention is based on the connection of a SEARCH part 1 performing NOR operation and a READ part 2 performing NOR function. Each of the parts 1(2) consists of a two-channel selector 13(23) with READ/WRITE inputs 130(230),131(231) and inverted output 10(20), an AND array 14(24) comprised of CML memory cells, and a set of sense-drive circuits 16(26) with the DRIVE input 161(261) and READ output 12(22). The READ output lines 12 of the SEARCH part 1 are connected to the READ input lines 230 of the READ part 2. The bit partitioning networks 3 to receive n input signal lines 30 as well as to output N partitioned bit lines 130 and the output circuit 4 with m output lines 41 are connected to the READ input lines 130 of the SEARCH part 1 and the READ output lines 22 of the READ part 2 respectively. There exist l column words, each of which consists of a pair of sense-drive word lines 15 on the SEARCH array 14 and a word lines 20 on the READ array 24. The R-PLA also has a WRITE address decoder 6 to address one of the column words in the WRITE mode and has READ/WRITE control circuits containing a set of EXCLUSIVE-OR circuits 7 etc.

FIG. 7 shows the detail diagram of the R-PLA for n=4, N=8, l=4 and m=3, in which there exist the SEARCH part 1, the READ part 2, two 2-bit input decoders 3, a WRITE address decoder 6, READ/WRITE control circuits containing a set of EXCLUSIVE-OR circuits 7 etc. and an output circuit 4.

Bit (word) lines 10 (20) on the SEARCH (READ) array 14 (24) run in the row (column) direction from the inverted outputs of the two-channel selectors 13 (23) which select the WRITE input signals in the WRITE mode or the READ input signals in the READ mode. Pairs of sense-drive word (bit) lines 15 (25) on the SEARCH (READ) array 14 (24) run to column (row) direction and connect at the terminals to the sense-drive circuits 16 (26). Each of the sense-drive circuits 16 (26) may receive a write pulse signal (WPS) from AND gate A.sub.s and a DRIVE input signal (DI) at the DRIVE gate (DG) in the WRITE mode, or generate a READ output signal 12 (22) from the reference circuit (RC) in the READ mode.

In the R-PLA shown in the FIG. 7, when the WRITE ENABLE control signals designated by WE1 and WE2 are logical 0's, the R-PLA is in the READ mode. In the READ mode of the R-PLA, the two-channel selectors 13 (23) are controlled to select the READ input signals 130 (230) by means of the logical 0 at the select control lines SL1 and SL2, and all sense-drive circuits 16 (26) are controlled to generate the results of AND-functions performed on the arrays to the READ output lines 12 (22) by means of the logical 0's at the write pulse signal lines WPS1 and WPS2.

The READ operation of the SEARCH (READ) part 1 (2) of the R-PLA is performed such that, when there exists one logical 0 at least in the contents of the CML memory cells 11 (21) on the each pair of sense-drive word (bit) lines 15 (25) and on a plurality of bit (word) lines 10 (20) activated to logical 0's according to the logical 1's of the READ input signals 130 (230) of the two-channel selectors, 13 (23), the logical 0 is generated at the corresponding READ output line 12 (22) of the sense-drive circuit 16 (26).

In order to illustrate the READ operation of the R-PLA, the 2-bit adder shown in the FIG. 2 is used. When the 2-bit adder is already realized by the R-PLA of FIG. 7, the simplified representation for the READ mode of the R-PLA is shown in FIG. 8. Two bit partitioning networks receive the input signals x.sub.0 x.sub.1 =01 and x.sub.2 x.sub.3 =11 and output the partitioned bit signals {0,0,1,0} and {0,0,0,1} respectively. As the selectors 13 of the SEARCH part 1 are controlled to select signals of the READ input lines 130 connected to the partitioned bit lines by means of the logical 0 at the line SL1, the inverted output signals 10 of the two selectors 13 are {1,1,0,1} and {1,1,1,0} respectively. In the SEARCH array 14, bit personalities (i.e., contents of the CML memory cells) are already set as shown in FIG. 8. The bit lines b.sub.i (i=0,1, . . . , 7) entering from the inverted outputs 10 of the selectors 13 are `connected` by means of AND-cells with the content 0's to pairs of sense-drive word lines sw.sub.j (j=0,1,2,3) at intersections indicated by 0 symbols corresponding to .multidot. symbols in FIG. 3. The sense-drive circuits 16 of the SEARCH part 1 are controlled to generate the results of the AND-functions performed on the SEARCH array 14 by means of the logical 0 at the line WPS1.

Let B.sub.i (i=0,1, . . . , 7) and W.sub.j (j=0,1,2,3) be Boolean variables for bit lines b.sub.i (i=0,1, . . . , 7) and READ output lines SRO.sub.j (j=0,1,2,3) of the SEARCH part 1 respectively, W.sub.j are given by equations (6). For {B.sub.0,B.sub.1,B.sub.2,B.sub.3 }={1,1,0,1} and {B.sub.4,B.sub.5,B.sub.6,B.sub.7 }={1,1,1,0}, {W.sub.0,W.sub.1,W.sub.2,W.sub.3 } are given by {0,0,1,1}.

Note that when there exists at least one logical 0 in the contents of the CML memory cells 11 on a pair of sense-drive lines, sw.sub.j, and on two bit lines b.sub.2 and b.sub.7 activated to logical 0's, logical 0 is generated at the READ output lines 12 as SRO.sub.0 and SRO.sub.1.

As the two-channel selector 23 of the READ part 2 is controlled to select signals of the READ input lines 230 connected to the READ output lines SRO.sub.j (j=0,1,2,3) of the SEARCH part 1 by means of the logical 0 at the line SL2, the inverted output signals 20 of the selector 23 of the READ part 2 are {1,1,0,0}. In the READ array 24 bit personalities are already set shown in FIG. 8. The word lines w.sub.j (j=0,1,2,3) entering from the inverted outputs 20 of the selector 23 are `connected` by means of AND-cells with the content 0's to a pair of sense-drive bit lines, sb.sub.k (k=0, 1,2) at intersections indicated by 0 symbols corresponding to x symbols in FIG. 3. The sense-drive circuits 26 of the READ part 2 are controlled to generate the results of AND-functions performed on the array 24 to the READ output lines RRO.sub.k (k=0,1,2) by means of the logical 0 at the line WPS2.

Let W.sub.j (j=0,1,2,3) and Z.sub.k (k=0,1,2) be Boolean variables for word line w.sub.j (j=0,1,2,3) and READ output lines RRO.sub.k (k=0,1,2) respectively, Z (k=0,1,2) are given by

Equations (8) are identified with equations (7). For {W.sub.0,W.sub.1,W.sub.2,W.sub.3 }={1,1,0,0}, {Z.sub.0,Z.sub.1,Z.sub.2 } are given by {1,0,0}.

Note that when there exists at least one logical 0 in the contents of the CML memory cells 21 on a pair of sense-drive bit lines, sb.sub.k, and on two word lines w.sub.2 and w.sub.3 activated to logical 0's, logical 0's are generated at the READ output lines 22 as RRO.sub.1 and RRO.sub.2.

As it is defined in this invention that each of the two parts 1 (2) in the R-PLA performs the logic in the form of NOR (i.e., INVERT-AND) operations, each output Boolean function at the READ output line RRO.sub.j of the READ part 2 is realized in the `product of sums` for the READ input variables 130 of the SEARCH part 1.

In the R-PLA shown in FIG. 7, when WRITE ENABLE control signals designated by WE1 and WE2 are logical 1's, the R-PLA is in the WRITE mode. In the WRITE mode of the R-PLA, the two-channel selectors 13 (23) are controlled to select the WRITE input signals 131 (231) by setting the logical 1's at the select control lines SL1 and SL2 during the clock (CLK1 or CLK2) width time, and at least one of sense-drive circuits 16 (26) is controlled to start the WRITE operation by setting logical 1's at lines WPS1 and WPS2 during the write pulse width. The write pulse is made by two AND gates (A.sub.s and A.sub.c) and the delay line (DI).

The WRITE input lines 131 of the SEARCH part 1 are connected to the output lines of the EXCLUSIVE-OR circuits 7. The EXCLUSIVE-OR circuits 7 send the first WRITE data signals (FWDS) to the output lines when the TRUE output signal Q of the J/K flip-flop 500 in the control circuits is logical 0, and send the inverted signals of the FWDS to the output lines when the TRUE output signal Q is logical 1. The JK input lines and trigger input line of the J/K flip-flop 500 are connected to the lines fixed to logical 1's and the output line of the AND gate A.sub.c with the inputs WE1 and CLK1 respectively. Therefore, the TRUE output signal Q is inverted in turn by the High-to-Low transition of the clock CLK1 during WE1=1. According to a plurality of logical 1's of the WRITE input signals 131, a plurality of bit lines 10 on the SEARCH array 14 are activated to logical 0's. In the SEARCH part 1, only one sense-drive circuit 16 addressed by the WRITE address decoder 6 can receive the write pulse signal of logical 1 at the line WPS1. Because each WPS1 line is connected to the output line of each AND gate A.sub.s with the input signals of WE1.CLK1, DCLK1 (delay clock) and DEC (the decoded output of the WRITE address decoder). All DRIVE input lines (DI) of the sense-drive circuits 16 in the SEARCH part 1 are connected in common to the FALSE output Q of the J/K flip-flop 500. Therefore, only the one sense-drive circuit 16 having just received the write pulse signal starts to drive the logical 1 when the non-inverted signals of the FWDS are sent to the WRITE input lines 131 or drive the logical 0 when the inverted signals of the FWDS are sent to the WRITE input lines 131.

The WRITE input lines 231 of the READ part 2 are connected to the decoded output lines 61 of the WRITE address decoder 6. Therefore, only one word line 20 on the READ array 24 activates to logical 0. In the READ part 2, all of the sense-drive circuits 26 can receive the write pulse signal of logical 1 at the same time at the line WPS2, because all WPS2 lines are connected in common to the output of the AND gate A.sub.s with inputs of WE2.multidot.CLK2 and DCLK2 (delay clock). Also, each DRIVE input line 71 off the sense-drive circuits 26 in the READ part 2 comes independently from the second WRITE data signals (SWDS). Therefore, all sense-drive circuits 26 just having received the write pulse signals start to drive the SWDS at the same time.

The WRITE operation of the SEARCH (READ) part 1 (2) of the R-PLA is performed such that, when at least one of the sense-drive circuits 16 (26) receives the write pulse signal, the DRIVE input signal 161 (261) inputted at the sense-drive circuit 16 (26) is written, through a pair of sense-drive word (bit) lines 15 (25), into at least one of CML memory cells 11 (21) on the bit (word) lines 10 (20) activated to logical 0's according to the logical 1's of the WRITE input signals 131 (231) selected by the selectors 13 (23).

When the clock CLK1 has twice as frequency as the clock CLK2, the timing chart for each signal in the WRITE mode of the R-PLA is shown in FIG. 9.

In order to illustrate the WRITE operation of the R-PLA, the 2-bit adder shown in FIG. 2 is used again. The simplified representation for the WRITE mode of the R-PLA is shown in FIG. 10. Now, it is defined that each column word CW.sub.j (j=0,1,2,3) consists of the contents of the CML memory cells 11 on a pair of sense-drive word lines sw.sub.j (j=0,1,2,3) in the SEARCH array 14 and the contents of the CML memory cells 21 on the corresponding word line w.sub.j (j=0,1,2,3) in the READ array 24. Then, the first column word CW.sub.0 is already written as

The second column word CW.sub.1 as

is about to be written into the CML memory cells on the line sw.sub.1 and the line w.sub.1. Other two column words CW.sub.2 and CW.sub.3 are not written yet and their contents are in DON'T CARE states designated by x symbols in FIG. 10. In order to load the second column word CW.sub.1 into the CML memory cells on the lines sw.sub.1 and w.sub.1, the FWDS and the SWDS are set respectively as

The WRITE operation of the SEARCH part 1 is performed in synchronism with the clock CLK1 which has twice as frequency as the clock CLK2. When the TRUE output signal Q of the J/K flip-flop 500 which enters in common to all EXCLUSIVE- OR circuits 7 is logical 0 during a cycle of the clock CLK1, the WRITE input signals 131 of the selectors 13 are given by

As the selectors 13 are controlled to select the WRITE input signals 131 to the inverted outputs by means of the logical 1 at the line SL1, the bit lines b.sub.i (i=0,1, . . . , 7) on the SEARCH array 14 are set as

Three bit lines b.sub.3, b.sub.5 and b.sub.6 are activated to logical 0's. As the WRITE address input signals 60 are set {1,0}, the decoded output signals 61 becomes as {0,1,0,0} and only second sense-drive circuit 16 of the SEARCH part 1 can receive the write pulse signal at the line WPS1. Therefore, the logical 1 at the DRIVE input line (DI) which comes from the FALSE output Q of the J/K flip-flop 500 are written into the CML memory cells 11 at intersections of (b.sub.3,sw.sub.1), (b.sub.5,sw.sub.1), (b.sub.6,sw.sub.1).

When the TRUE output Q of the J/K flip-flop 500 becomes logical 1 during the secceeding next cycle of the clock CLK1, the WRITE input signals 131 of the selectors 13 equal the inverse of the given FWDS as

Therefore, the logical 0 at the DRIVE input line which is generated by means of Q=0 is written into the CML memory cells 11 at intersections of (b.sub.0,sw.sub.1), (b.sub.1,sw.sub.1), (b.sub.2,sw.sub.1), (b.sub.4,sw.sub.1) and (b.sub.7,sw.sub.1). Thus, the FWDS is written into the CML memory cells 11 on the line sw.sub.1 during two cycles of the clock CLK1.

On the other hand, the WRITE operation of the READ part 2 is performed in sychronism with the clock CLK2. The WRITE input signals 231 of the selector 23 of the READ part 2 equal to the decoded output signals 61 of the WRITE address decoder 6 as

As the selector 23 is controlled to select the WRITE input signals 231 to the inverted output by means of the logical 1 at the line SL2, word lines w.sub.j (j=0,1,2,3) on the READ array 24 are set as

Note that unlike the SEARCH part 1 only one word line w.sub.1 is activated to logical 0 in the READ part 2. As all sense-drive circuits 26 of the READ part 2 receive in common the write pulse signal at the line WPS2, the DRIVE input signals 71 {1,0,0} which comes from the SWDS are written into the CML memory cells 21 on the word line w.sub.1 activated to logical 0 during one cycle of the clock CLK2.

Next, the READ/WRITE operations of the R-PLA are considered electrically.

FIG. 11 shows a section of the SEARCH part 1 which containes two CML memory cells M.sub.0 and M.sub.10 existing at intersections (b.sub.0, sw.sub.0) and (b.sub.10, sw.sub.0) respectively on the SEARCH array 14, the sense-drive circuit 16 with a DRIVE gate (DG) and a reference circuit (RC) and the AND gate (A.sub.s). Bit lines b.sub.0 and b.sub.10 come from emitter terminals of the transistors E.sub.0 and E.sub.10 respectively. Each base terminal of the transistors is connected to the corresponding inverted output line of the selector (SEL) 13 of the SEARCH part 1. Here, note that the subscript j in the representation of the cell M.sub.ij at intersection (b.sub.i, sw.sub.j) is omitted for clarity. Each CML memory cell M.sub.i (i=0, 10), which is interconnected to the bit line b.sub.i (i=0,10) and to a pair of sense-drive word lines sw.sub.0, consists of the multi-emitter-type transistor T.sub.i.sup.1 and T.sub.i.sup.2 (i=0, 10), collector resistors with the value R.sub.1, Schottky Barrier Clamp diodes SBD.sub.i.sup.1 and SBD.sub.i.sup.2 (i=0,10) and a constant current supply with the value I.sub.1. Each sense-drive line (sw.sub.0.sup.1 or sw.sub.0.sup.2) is connected at the terminal to the sense-drive circuit 16 which consists of the reference circuit (RC) and the DRIVE gate (DG). The reference circuit to generate the READ output signal at the line SRO.sub.0 contains the reference transistors Q.sup.1 and Q.sup.2, emitter follower transistors E.sup.11, E.sup.12, E.sup.21, and E.sup.22, resistors with the value r, and a constant current supply with the value I.sub.2. The DRIVE gate to receive the DRIVE input signal from the line DI contains the transistors t.sup.1 and t.sup.2, three collector resistors which have the value R.sub.2, R.sub.3 and R.sub.3, and a constant current with the value I.sub.3. The AND gate A.sub.s, which consists of the transistors t.sup.11, t.sup.12, t.sup.13 and t.sup.21, collector resistors with the values R.sub.2, R.sub.3, and the constant current supply with the value I.sub.3, receives the AND signal (WE1.CLK1), the delay clock signal (DCLK1) and the decoded output signal (DEC) of the WRITE address decoder, and generates the write pulse signal at the output line WPS1.

FIG. 12 illustrates operating voltage level relations with respect to the circuits shown in FIG. 11.

When the WRITE ENABLE control signal designated by WE1 is HIGH voltage (logical 0) of the READ mode of the R-PLA, the transistor t.sup.11 of the AND gate A.sub.s in FIG. 11 is ON and the voltage levels of the line WPS1 is -R.sub.2 I.sub.3. The voltage levels of the base terminals of the transistors E.sup.11 and E.sup.21 in the reference circuit, which are determined by the collector voltages of the transistors t.sup.2 and t.sup.1 in the DRIVE gate respectively, are below -R.sub.2 I.sub.3. Therefore, the reference voltages V.sub.ref.sup.1 and V.sub.ref.sup.2 on the base terminals of the transistors Q.sup.1 and Q.sup.2 are given, as shown in FIG. 12, by

where V.sub.be represents the forward voltage drop (about 0.8 V) between base and emitter of a bipolar transistor.

Let V(b.sub.i) be the voltage level of the bit line b.sub.i on the SEARCH array 14, it is assumed that V(b.sub.i) is given by

where V.sub.L and V.sub.H are LOW voltage and HIGH voltage corresponding to the logical 1 and the logical 0 respectively for the inverted output signals of the selector 13. It is also assumed that, in the circuits shown in FIG. 11, the transistors T.sub.0.sup.1 and T.sub.0.sup.2 of the cell M.sub.0 are OFF and ON respectively, and the transistors T.sub.10.sup.1 and T.sub.10.sup.2 of the cell M.sub.10 are OFF and ON respectively. In a general R-PLA, the content of the cell M.sub.ij (i=0,1, . . . ,N-1;j=0,1, . . . , l-1) in the SEARCH array 14 is defined as the logic level corresponding to the collector voltage level of the left transistor T.sub.ij.sup.1 in the cell M.sub.ij, M.sub.0 and M.sub.10 in the R-PLA shown in the FIG. 11 are said to be the 'cells with the content 0.

When the voltage V(b.sub.0) of the bit line b.sub.0 in FIG. 11 is LOW (logical 1) at V.sub.L -V.sub.be (-1.6 V), collector voltages V(c.sup.1) and V(c.sup.2) of the transistors T.sub.0.sup.1 and T.sub.0.sup.2 in the cell M.sub.0 are given respectively, as shown in FIG. 12, by

where V.sub.SBD is the forward voltage drop (about 0.4 V) of the SBD. The condition of the reference voltage such that the cell M.sub.0 is in the HOLD state in the READ mode of the R-PLA is ##EQU2## When the HOLD condition (13) is satisfied, the first emitters e.sub.0.sup.11 and e.sub.0.sup.21 of the transistors T.sub.0.sup.1 and T.sub.0.sup.2 in the cell M.sub.0 are CUT-OFF and the current does not flow at the emitters. Of course, the current I.sub.1 flows through the second emitter e.sub.0.sup.22 of the ON transistor T.sub.0.sup.2 but not through the second emitter e.sub.0.sup.12 of the OFF transistor T.sub.0.sup.1.

If all cells on the line sw.sub.0 were in the HOLD state, the voltage of the READ output line SRO.sub.0 would be LOW level (logical 1) by means of the ON state of the reference transistor Q.sup.2. But, note that in the READ mode of the R-PLA a plurality of bit lines 10 on the SEARCH array 14 are always activated to the HIGH voltage (logical 0) at V.sub.H -V.sub.be (-0.8 V) at the same time according to the READ input signals 130 as described in the previous section.

When the voltage V(b.sub.0) of the bit line b.sub.0 in FIG. 11 rises to the HIGH level (logical 0) at V.sub.H -V.sub.be (-0.8 V), the collector voltages V(c.sup.1) and V(c.sup.2) of the transistors T.sub.0.sup.1 and T.sub.0.sup.2 in the cell M.sub.0 become higher respectively, as shown in FIG. 12, as

The condition of the reference voltage such that the content (i.e., collector voltage level V(c.sup.1) of the transistor T.sub.0.sup.1) of the cell M.sub.0 can be read out is given, as shown in FIG. 12, by ##EQU3## When the READ condition (16) is satisfied, the first emitters e.sub.0.sup.11 and e.sub.0.sup.21 of the transistors T.sub.0.sup.1 and T.sub.0.sup.2 of the cell M.sub.0 are OFF and ON respectively. Therefore, since the reference transistor Q.sup.2 becomes OFF, the voltage at the line SRO.sub.0 is HIGH level (logical 0) at 0 voltage.

If the voltage V(b.sub.10) of the another bit line b.sub.10 rises to the HIGH level (logical 0) at V.sub.H -V.sub.be (-0.8 V), the first emitter e.sub.10.sup.11 and e.sub.10.sup.21 of the transistors T.sub.10.sup.1 and T.sub.10.sup.2 in the another M.sub.10 are also OFF and ON respectively.

Thus, in a general R-PLA, when a plurality of the bit lines 10 on the SEARCH array 14 are activated to the HIGH voltages (logical 0's) at V.sub.H -V.sub.be (-0.8 V) at the same time according to the READ input signals 130, the READ current I.sub.R flow through each first ON emitter of each cell with content 0 to the line sw.sub.j.sup.2 (j=0.1, . . . , l-1) is given by

Here, .alpha. represents the total number of the cells with content 0 on the line sw.sub.j and on the bit lines 10 activated in the READ mode to the HIGH voltages (logical 0's) at V.sub.H -V.sub.be (-0.8 V). It is clear that, when the p-bit decoders are used as the bit partitioning networks 3 in a general R-PLA with n inputs, .alpha. satisfies

where n/p is the number of the p-bit decoders.

On the other hand, when the WRITE ENABLE control signal designated WE1 in FIG. 11 is LOW voltage (logical 1) of the WRITE mode and the decoded output signal (DEC) of the WRITE address decoder 6 is also LOW voltage (logical 1), the write pulse signal is generated at the line WPS1 while both of the clock (CLK1) and the delay clock (DCLK1) are LOW voltage. The voltage level of the write pulse signal generated at the line WPS1 by switching transistor t.sup.21 of the AND gate A.sub.s to the ON state is -R.sub.2 I.sub.3 -R.sub.3 I.sub.3.

If the voltage level of the DRIVE input signal (DI) inputted at the base terminal of the transistor t.sup.1 in the DRIVE gate is LOW (logical 1), the voltage levels of the base terminals of the transistors E.sup.11 and E.sup.21 are -R.sub.2 I.sub.3 -R.sub.3 I.sub.3 and -R.sub.2 I.sub.3 respectively. Therefore, the reference voltage V.sub.ref.sup.1 and V.sub.ref.sup.2 of the base terminals Q.sup.1 and Q.sup.2 are given respectively, as shown in FIG. 12, by

When the voltage V(b.sub.0) of the bit line b.sub.0 is LOW level (logical 1) at V.sub.L -V.sub.be (-1.6 V), both collector voltages V(c.sup.1) and V(c.sup.2) of the transistors T.sub.0.sup.1 and T.sub.0.sup.2 in the cell M.sub.0 are given by equations (11) and (12) respectively. Therefore, the condition of the reference voltage such that the cell M.sub.0 remains in the HOLD state also in the WRITE mode of the R-PLA is given, as shown in FIG. 12, by ##EQU4## It is clear that if the condition (21) is satisified the condition (13) is satisfied.

When the V(b.sub.0) of the bit line b.sub.0 in the FIG. 11 rises to the HIGH level (logical 0) at V.sub.H -V.sub.be (-0.8 V), the collector voltage V(c.sup.1) and V(c.sup.2) of the transistors T.sub.0.sup.1 and T.sub.0.sup.2 in the cell M.sub.0 become higher as indicated by equations (14) and (15) respectively. Therefore, the condition of the reference voltage such that the content (i.e., collector voltage level V(c.sup.1) of the transistor T.sub.0.sup.1) of the cell M.sub.0 can be changed from the logical 0 (HIGH voltage) to the logical 1 (LOW voltage) is given, as shown in FIG. 12, by ##EQU5## When the WRITE condition (22) is satisfied, the transistors T.sub.0.sup.1 and T.sub.0.sup.2 of the cell M.sub.0 change from OFF to ON and ON to OFF respectively since the WRITE current I.sub.w flows through the emitter e.sub.0.sup.11 to the line sw.sub.0.sup.1.

Here, note that also in the WRITE mode of the R-PLA a plurality of the bit lines 10 on the SEARCH array 14 are activated to the HIGH voltages (logical 0's) at V.sub.H -V.sub.be (-0.8 V) at the same time according to the WRITE input signals 131 as described in the previous section. If the voltage V(b.sub.10) of the another bit line b.sub.10 rises to the HIGH level (logical 0) at V.sub.H -V.sub.be (-0.8 V) at the same time as the HIGH voltage V(b.sub.0), the transistors T.sub.10.sup.1 and T.sub.10.sup.2 in the another cell M.sub.10 also change from OFF to ON and ON to OFF respectively since the WRITE current I.sub.w flows through the emitter e.sub.10.sup.11 to the line sw.sub.0.sup.1.

Thus, in a general R-PLA, when a plurality of the bit lines 10 on the SEARCH array 14 are activated in the WRITE mode to the HIGH voltages (logical 0's) at V.sub.H -V.sub.be (-0.8 V) at the same time according to the WRITE input signals 131 and the LOW voltage (logical 1) is inputted at the DRIVE input line (DI), the WRITE current I.sub.w to flow through each first ON emitter of each cell with the content 0 to the line sw.sub.j (j=0,1, . . . , l-1) is given by

Here, .beta. represents the total number of the cells with the content 0's on the line sw.sub.j and on the bit lines activated in the WRITE mode to the HIGH voltages (logical 0's) at V.sub.H -V.sub.be (-0.8 V). It is clear that, when there exists N bit lines 10 on the SEARCH array 14 in a general R-PLA, .beta. satisfies

Also, the WRITE current to standby current ratio I.sub.w /I.sub.1 to change the content of a CML memory cell sufficiently must be

The READ/WRITE operations of the READ part 2 in the R-PLA will be proved electrically similar to those of the SEARCH part 1 discussed above. Noting that the number of word lines 20 activated to the HIGH voltages (logical 0's) at V.sub.H -V.sub.be (-0.8 V) is only one in the WRITE mode of the READ part 2, the relation of the currents I.sub.1 ' and I.sub.2 ' corresponding to the currents I.sub.1 and I.sub.2 for the SEARCH part 1 respectively is given, as a condition to change the content of a CML memory cell, by

Also, in the READ mode of the READ part 2, the number of word lines 20 activated to the HIGH voltages (logical 0's) at V.sub.H -V.sub.be (-0.8 V) is 0 from l where l is the number of word lines 20 of the general R-PLA.

Therefore, the current I.sub.2 for the SEARCH array 14 and the current I.sub.2 ' for the READ array 24 will be determined approximately as

Owing to the existence of the conditions (27), the problem for the design of the R-PLA is the reduction of power dissipation rather than the speed.

The R-PLA with 1-bit decoders shown in FIG. 13 is identified with a maskable Content Addressable Memory (CAM). The Boolean product represented at each READ output line of the SEARCH part 1 (i.e., CAM) is obtained by selecting the appropriate output from each 1-bit decoder and ANDing all of these together. The personality associated with any given variables A,B, and C can be (.sub.1.sup.0), (.sub.0.sup.1) or (.sub.1.sup.1). The personality (.sub.0.sup.0) is not normally used. For the personality (.sub.1.sup.1), we have a DON'T CARE situation for that particular variable. This is functionally equivalent to `mask` the variable. That is, for a variable A, the parsonalities (.sub.1.sup.0), (.sub.0.sup.1) and (.sub.1.sup.1) represent A=0, A=1 and the mask of A. In the READ part 2 which works as a RAM in FIG. 13, a word addressed by means of the match for the input and the product can be readout.

Also, a functional logic such as an arithmetic logic unit which requires large number of cells to realized by using a read-only type of the conventional PLA in a single cycle will be realized by using the R-PLA in many cycles.

When the R-PLA is used as a control store, a high performance system with a dynamic microprogramming such as a debugging machine [4] will be established in future.

References:

1. H. Fleisher and L. I. Maissel, "An Introduction to Array Logic," IBM Journal of Research and Development, Vol. 19, No. 2, pp. 98-109, March, 1975.

2. P. L. Gardner, "Functional Memory and its Microprogramming Inplications," IEEE Trans. Comp., Vol. 20, No. 7, pp. 764-775, July, 1971.

3. J. W. Jones, "Array Logic Macro," IBM Journal of Research and Development, Vol. 19, No. 2, pp. 120-126, March, 1975.

4. K. Sakamura, H. Kitafusa, Y. Takeyari and H. Aiso, "A Debugging Machine--An Approach to an Adaptive Computer," Proceedings of IFIP Congress 77, Toronto, August 8-12, 1977, pp. 23-28.

These references are referred to at various places in the foregoing sepcification by their identification numeral in brackets.

Claims

What is claimed is:

1. A rewritable programmable logic array (R-PLA), which loads a word pattern of bit personalities to generate specific logic function into memory cells from the word direction comprising: a SEARCH array (14) comprising bit lines (10), sense-drive word lines (15) having end terminals thereon and multi-emitter type bistable Current Mode Logic (CML) memory cells (11) at all intersections of said bit lines with said sense-drive word lines; a READ array (24) comprising word lines (20), sense-drive bit lines (25) having end terminals thereon and multi-emitter type bistable CML memory cells at all intersections of said word lines with said sense-drive word lines; a first two-channel selector (13) comprising first READ inputs (130) and first WRITE inputs (131) to which input signals are respectively supplied, the outputs of said first selector being connected to said bit lines of said SEARCH array; first sense-drive circuits (160) operable in a READ mode and a WRITE mode connected to said terminals of said sense-drive word lines of said SEARCH array, having first DRIVE inputs (161) and first WRITE pulse signal inputs (160) respectively receiving signals in said WRITE mode and having first READ outputs (12) for generating AND-function signals in response to said first READ inputs of said first selector in said READ mode; a second two-channel selector (23) comprising second READ inputs (230) and second WRITE inputs (231) to which input signals are respectively supplied, and second READ inputs of said second selector being connected to said first READ outputs of said first sense-drive circuits, the outputs of said second selector being connected to said word lines of said READ array; second sense-drive circuits (26) operable in a READ mode and a WRITE mode connected to said terminals of said sense-drive bit lines of said READ array, having second DRIVE inputs (261) and second WRITE pulse signal inputs (260) respectively receiving signals in said WRITE mode and having second READ outputs (22) for generating AND-function signals in response to said second READ inputs of said second selector in said READ mode; bit partitioning networks (3) having inputs (30) for receiving input variables and having outputs (130) connected to said first READ inputs of said first selector to deliver signals to said first selector; a WRITE address decoder (6) having inputs (60) for receiving WRITE address signals and outputs (61) connected, through means (8) for generating said first WRITE pulse signals, to said first WRITE pulse signal inputs of said first sense-drive circuit and also connected to said second WRITE inputs of said second selector, first READ/WRITE control circuits (5, 6, 7 and 8) including said means for generating said first WRITE pulse signals and connected to said first WRITE inputs to a selected control lines (SLI) of said first selector and to said first sense-drive circuits; and second READ/WRITE control circuits (5, 9) connected to said second selector and also to said second sense-drive circuits; whereby AND-functions are conducted by using one multi-emitter of a transistor in each said CML memory cell and an emitter of a reference transistor in each of said sense-drive circuits in the READ mode of said R-PLA.

2. The R-PLA according to claim 1 wherein the said first and second READ/WRITE control circuits include means to let a word pattern of the said bit personalities load into the said CML memory cells existing along said sense-drive word lines on said SEARCH array and along said word lines in the said READ array respectively in the WRITE mode of the R-PLA.

3. The R-PLA according to claim 2 in which said means for letting the said bit personalities load into the said cells comprises EXCLUSIVE-OR circuits (7), the first of two inputs of each said EXCLUSIVE-OR circuit receiving each bit of said bit personalities to be stored in the said CML memory cells on said SEARCH array and the output of each of one of said EXCLUSIVE-OR circuits being connected to each of one of said first WRITE inputs of said first two-channel selector.

4. The R-PLA according to claim 3 in which said means for letting the said bit personalities load into the said cells comprises a J/K flip-flop (500), the true output of the said J/K flip-flop being inverted in turn by a trigger input and connected to the second of said two inputs of each said EXCLUSIVE-OR circuit, and the false output of the said J/K flip-flop being connected to each of said first DRIVE inputs of said first sense-drive circuits.

Patent Citations (12)

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Non-Patent Literature (1)

"Programmable Architectural Array", E. H. Stoops, IBM Tech. Disc. Bull., vol. 19, No. 12, May 1977, p. 4569.

Abstract

Description