Electronically Controlled Franking Machine

The invention relates to an electronically controlled franking machine, preferably a postage meter and stamping machine with a printing device, a postage value printing selection device, a total postage charge storage register, and a settable subtracting value counter; the control device of which comprises a processor, preferably a microprocessor, and associated semiconductor memories.

In electronically controlled postage meter and stamping machines with semiconductor storage for the number of all printing and setting operations as well as for the mechanical wear data and rate limits, it is required that, in the event of a line voltage failure, the last memory contents must be preserved. In addition, certain states of the control logic must be stored so that the commands or functions initiated prior to the line failure can be executed or continued when the line voltage returns. For this purpose, non-volatile semiconductor memories are used.

Known non-volatile semiconductor memories, however, have the disadvantage that they are unusable after about 10.sup.6 writing cycles. Furthermore, the number of reading cycles after a one-time writing cycle is limited, since a small voltage is continuously present at the control input of the memories. This voltage acts like a weak writing voltage, so that after about 10.sup.10 read operations, the memory content is no longer reliably recognizable. A further disadvantage is the limited storage time, which depends on the combination of the voltage amplitude and the pulse width of the data to be fed-in and in a normal temperature range without supply voltage is only in the order of 10.sup.4 hours.

Such a non-volatile memory can therefore not be used like a normal memory, since the limited number of writing cycles would be quickly reached.

It is accordingly an object of the invention to provide an electronically controlled franking machine which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type by suitable switching measures.

With the foregoing and other objects in view there is provided, in accordance with the invention, an electronic control for franking machines such as postage meters and stamping machines having a printing device, a postage value printing selection device, a total postal charge storage register and a settable subtracting value counter, comprising a microprocessor, a volatile main memory for storing data, and non-volatile semiconductor memories for storing data and the number of writing cycles performed, the memories being connected to the microprocessor, a line voltage power supply, supply capacitors disposed in the power supply, switch means controlled by the microprocessor for connecting the non-volatile memories to the supply capacitors of the power supply exclusively in the event of an interruption of the line voltage to cause the non-volatile memories to take over data stored in the main memory, and register means connected to one of the non-volatile memories for preventing the exceeding of a predetermined number of writing cycles of the one non-volatile memory after the power supply resumes.

In accordance with another feature of the invention, there are provided devices for releasing a signal after a given number of writing cycles of the non-volatile memories has been reached.

In accordance with a further feature of the invention, there are provided devices for releasing a print inhibit signal when the predetermined number of writing cycles is at least reached.

In accordance with an added feature of the invention, there are provided a clock signal generator disposed in the microprocessor for measuring uninterrupted data storage time, and devices for triggering an automatic cleaning and writing phase for refreshing the memory contents after a given interrupted storage time.

In accordance with an additional feature of the invention, the clock signal generator is restarted after each line interruption.

In accordance with a concomitant feature of the invention, there are provided devices controlled by the clock signal generator for periodically determining total postage charges.

Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in an electronically controlled franking machine, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying single FIGURE of the drawing which is a block diagram of an electronically controlled postage meter and stamping machine.

Referring now to the single FIGURE of the drawing, it is seen that several memories and a minicomputer, preferably a microprocessor MP, are used for controlling the postage indication and the value or denomination printing. The microprocessor disclosed in German Published, Non-Prosecuted Application DEOS No. 30 40 549, corresponding to U.S. patent application Ser. No. 089,413 is one of several such available devices usable as the microprocessor MP. In the block diagram, the indicator and denomination printing devices are controlled through the undesignated terminals of the microprocessor MP. These are not shown since they are not important for the invention. In addition to a main memory ASP and a program memory PSP, two non-volatile semiconductor memories SP1, SP2, preferably MNOS memories, are used. The first of these is an exchangeable memory SP1 which serves, for instance, for storing the monthly postage total, for storing the postal rates, for containing customer, country, or postal-related program routines, or it can be used as a variable data storage for automated mail lines. If postal rates change, it is easily exchanged. The second, permanently assigned memory SP2 serves for storing the total postage and the remaining postage total etc., as well as the number of times the line was connected and thereby the number of writing cycles of both non-volatile memories SP1 and SP2.

The volatile main memory ASP, preferably a RAM, stores the actual state of the control logic and also totals the operating time of the postage meter and stamping machine. The main memory ASP continues to be supplied with voltage even after the equipment is switched off, as long as the connection with the line voltage is preserved.

A switch SS for the power supply is controlled by the processor MP and is associated with the non-volatile semiconductor memories SP1, SP2. In order to preclude the possible 10.sup.6 writing cycles of the non-volatile memories and to nevertheless ensure continuous readiness for storage of the memories during the entire life of the equipment, a command to store is given only if an interruption of the line voltage occurs. After the power plug of the equipment is pulled or after some other interruption, a line failure signal is generated, for instance by the dropping voltage at the output of the power supply N, which cuases the processor MP to actuate the switch SS. Storage capacitors provided in the power supply N then supply the energy required for transferring the data stored in the main memory ASP into the non-volatile memories SP1 and SP2, respectively.

In addition, the second, permanently assigned memory SP2 has a special register. The latter is loaded after every line return with the value n+1.fwdarw.n; l.e., the then applicable entered number of the performed writing cycles has risen by the value 1 and now forms the new reference point n for a signal S which is indicated, for instance, after n=9.times.10.sup.5 writing cycles. This signal S constitutes, for instance, a call for servicing. When the equipment is checked, the register content is indicated and the memory is exchanged if necessary. If servicing does not take place, a print inhibit DV coupled to a mechanical locking device is additionally triggered when about 10.sup.6 writing cycles are reached.

The processor MP contains a quartz-controlled timer which generates a certain clock rate. This time base allows the measurement of periods of time, such as after an uninterrupted storage time of say one year, a clear-and-write phase is automatically provided to refresh the memory contents. In the process, the stored data of the time measurement are simultaneously cleared and set to the starting value, as also occurs after every line failure when the line voltage returns.

The time measurement finally makes it possible to determine the monthly charges and number of prints, etc., as well as the determination of the charges and the indication of the last n number of months.