Apparatus for Use in Testing an Internal Combustion Engine Ignition System

This invention relates to an apparatus for use in testing an internal combustion engine ignition system, particularly a system utilizing an ignition coil and electronic switch means for periodically connecting the primary winding of said ignition coil across a supply and for periodically interrupting the coil primary current.

With such a system it is difficult to establish in a test apparatus whether or not the switch means is operating satisfactorily so as to produce a spark. It is an object of the invention to provide apparatus for testing electronic ignition systems in which this difficulty is overcome.

Apparatus in accordance with the invention comprises a voltage comparator means for connection to the ignition system for detecting the voltage across said switch means and indicating when such voltage is in excess of a predetermined value which is an order of magnitude higher than the system voltage and timing means associated with said comparator means and producing an output indicating a satisfactory interruption of coil current only when the output of the comparator means persists in a state indicating that said voltage has been above said predetermined level for less than a predetermined duration.

Preferably said predetermined level is about 200 V for a 12 V system and said predetermined duration is about 20 .mu.S.

The apparatus preferably also includes a lock-out circuit comprising a further timing means connected to block the input to said first timing means for a second predetermined time (for example about 1 mS) after said first timing means has produced said output.

An example of the invention is shown in the accompanying drawings in which FIG. 1 is a schematic circuit diagram of the test apparatus and

FIG. 2 is a graphical representation of waveforms at various points in FIG. 1.

The ignition system to be tested is shown at the lefthand end of FIG. 1. The system includes an ignition coil 10 having a primary winding 10a and a secondary winding 10b joined at one end. This common end of winding 10a and 10b is connected by a ballast resistor 11 to the positive pole of a battery 13. An electronic switch 12, including an output transistor 12a connects the other end of the primary winding 10a to earth. The other end of the secondary winding 10b is connected via the usual distributor 14 to the spark plugs 15.

The test apparatus derives its power from the battery 13 via a voltage regulator 16. A reference voltage generator 17 is also connected to the battery 13 and provides a reference voltage which is applied to the inverting input of a voltage comparator 18. The non-inverting input of comparator 18 is connected to a point on a voltage dividing network 19, 20 between said other end of the primary winding 10a of the coil 10 and earth and chosen so that when the voltage at said other end of the primary winding 10a is equal to 200 V the voltages at the inverting and non-inverting inputs of the comparator 18 are equal. Thus the output of comparator 18 is high whenever the voltage at said other end of the primary winding is above 200 V.

The output of the comparator 18 is connected to one input of a NAND gate 21, the output of which is connected to a monostable timer circuit comprising capacitors 22, 23 resistors 24, 25, a NAND gate 26 and an inverter 27. The resistors 24, 25 connect the two inputs of the NAND gate 26 to the +ve rail, capacitor 22 connects the output of NAND gate 21 to one input of NAND gate 26, capacitor 23 connects the output of the inverter 27 to the other input of NAND gate 26 and the output of NAND gate 26 is connected to the input of inverter 27.

The capacitor 22 and the resistor 24 acts to differentiate the output of gate 21 so that this monostable timer circuit is triggered by a negative going change in the output of the NAND gate 21. The capacitor 23 and resistor 25 causes the output of NAND gate 26 to remain high for about 20 .mu.S following triggering.

A further NAND gate 30 has its two inputs connected to the outputs of NAND gates 21 to 26 respectively, so that its output goes low only when both NAND gates 21 and 26 are producing high outputs. An inverter 32 connects the output of gate 30 to the input of a further monostable timer circuit comprising two capacitors 33, 34, two resistors 35, 36 and NAND gate 37 and an inverter 38, arranged to be triggered on by a negative going edge at the output of inverter 32 and to remain on for about 1 mS.

The circuit has two output terminals, namely an output terminal 39 connected via the capacitor 33 to the output of inverter 32, and an output terminal 40 connected to the output of gate 37. The output of inverter 38 is connected to the other input of gate 21.

Trace A in FIG. 2 shows at its left hand end a voltage waveform associated with a satisfactory interruption of coil primary current. It will be noted that the voltage rises very rapidly to a peak well in excess of 200 V, but falls very rapidly (usually about 10 .mu.S later) back below 200 V. The waveform may subsequently include peaks caused by resonance, interference etc which exceed 200 V, but if these occur after 20 .mu.S have elapsed they can be ignored. Trace B shows the output of the comparator 18 and trace C the inverted version of this which appears at the output of gate 21 whenever the output of inverter 38 is high (which is its normal state). Trace D shows the 20 .mu.s pulse generated by the timer 22 to 27 following initial detection of the voltage exceeding 200 V. The output of gate 30 (trace E) goes low only if this 20 .mu.S pulse continues after the output of gate 21 has gone high again indicating that the voltage was above 200 V for less than 20 .mu.S. If the output of gate 30 does go low, the timer 33 to 38 is triggered when this output goes high again, thereby causing the output of inverter 38 to go low for 1 mS and blocking gate 21 for this period.

The right hand end of FIG. 2 shows a situation in which, for various reasons, the voltage remains above 200 V for more than 20 .mu.S, indicating a fault condition (for example electronic switch 12 turning of too slowly)

It will be noted that trace E shows no negative going pulse so that the timer circuit 33 to 38 is not triggered.

The circuit described is used in a test apparatus as disclosed in co-pending U.S. application Ser. No. 151,929 of even date based on U.K. Application No. 7,918,389. The pulses from terminal 39 are combined with pulses from another part of the apparatus indicating that current flow in the resistor 11 has restarted within a set time of the spike detected by the circuit described herein, the combination of this spike with such current restarting indication a satisfactory operation. The pulse produced at each satisfactory operation is passed to a processing circuit including the missing pulse detector of co-pending U.S. application Ser. No. 152,127 of even date based on U.K. Application No. 7,918,385 and the recognition circuit of co-pending U.S. application Ser. No. 152,121 of even date based on U.K. Application No. 7,918,388.