Silicon Controlled Rectifier Trigger Circuit

This invention relates to a silicon controlled rectifier trigger circuit and, in particular, to such a circuit which is advantageously applicable to electric stapler and electric brad driver mechanisms.

Electrically operated stapling devices and associated control circuits for same are known in the prior art. For example, Wines and Power U.S. Pat. No. 3,971,969 entitled "Electrically Operated Stapling Device" discloses means for applying at least two unidirectional drive pulses derived from an input AC voltage for driving a single staple per switch activation. However, such device requires: two switches 23 and 37; and two silicon controlled rectifiers 71 and 86. Further, such device does not provide one pulse per staple at variable intervals nor does it provide either one and only one pulse per switch activation or two and only two pulses per switch activation.

Objects of the present invention are therefore to provide a silicon controlled rectifier trigger circuit which:

Is readily adaptable to an electric stapler or an electric brad driver and which will deliver one and only one staple or brad per switch activation;

If the switch is maintained activated, further drive pulses are delivered at intervals of less than a second to many seconds;

The drive pulse interval can be made adjustable by utilizing a potentiometer;

Utilizes only one activation switch;

Utilizes only one silicon controlled rectifier;

A train of drive pulses can be delivered to the load, each pulse being approximately one-half cycle long and at intervals of from less than a second to many seconds;

Provides two drive pulses per switch activation; and

Provides one drive pulse per switch activation.

A silicon controlled rectifier trigger circuit is responsive to an input AC voltage and provides at least one drive pulse per switch activation to a load circuit. Such load circuit advantageously includes an electric stapler or an electric brad driver. Such trigger circuit generally comprises: a two-position switch; first and second capacitors; first and second Zener diodes; a transistor; and a silicon controlled rectifier. The drive pulse is provided to the load circuit when the switch is in its second position; the first capacitor is charged by the input AC voltage when the switch is in its first position; the first Zener diode and the transistor are conductive when the input AC voltage is greater than a first predetermined value; the first and second Zener diodes are conductive and the transistor is non-conductive when the input AC voltage is greater than a second predetermined value; the second capacitor is interposed between the first Zener diode and the transistor; the silicon controlled rectifier is conductive when the transistor is conductive and when the switch is in its second position to provide the drive pulse to the load circuit.

Features of the present invention are therefore that:

A plurality of drive pulses is delivered at variable intervals as determined by the ratio of first and second resistor values;

The load activation period can be adjusted by utilizing a potentiometer whose wiper arm is interposed between first and second resistors;

There are utilized first and second serially connected Zener diodes as delay elements;

The base of the transistor is driven positive only when the positive half-cycle input wave is more positive by the Zener voltage of said first diode and wherein the drive to the base is essentially terminated when the positive half-cycle input wave is more positive by the sum of the Zener voltages of said first and second diodes; and

The action of said second Zener diode limits the time during which the base of the transistor is driven to near the zero crossover point of the input AC voltage whereby approximately one half-cycle of power is delivered to the load circuit

The above and other objects, features, and advantages of the present invention will be better appreciated from the following detailed description and the drawing in which:

FIG. 1 is a circuit diagram of a first illustrative embodiment of a silicon controlled rectifier trigger circuit according to the present invention;

FIGS. 2 and 3 are waveform diagrams explanatory of the operation of the present invention;

FIGS. 4, 5, and 6 are circuit diagrams of second, third, and fourth illustrative embodiments of silicon controlled rectifier trigger circuits according to the present invention; and

FIG. 7 is another waveform diagram explanatory of the operation of the present invention.

FIG. 1 is a circuit diagram of silicon controlled rectifier trigger circuit 10 according to the present invention. Generally, trigger circuit 10 is responsive to an alternating current voltage at input terminals L1 and L2 and provides at least one activation or driving pulse per switch activation to the load at output terminals L3 and L4. The elements of trigger circuit 10 and their recommended parameters or values are as follows:

The setting forth of the above elements and recommended values or parameters is done solely for illustrative purposes and is not intended to limit the principle and scope of the disclosed invention.

Trigger circuit 10 may be advantageously used in conjunction with an electric stapler or an electric brad driver connected to output load terminals L3 and L4 for delivery of one staple or lead immediately upon activation of trigger circuit 10. Generally, if switch S1 is held in the 2 position, further activation of the associated stapler or brad device takes place at less than one to many second intervals depending on the values of resistors R1 and R2. Further, Zener diodes ZD1 and ZD2 are utilized as delay elements as shall be hereinafter explained in detail.

Specifically, input terminals L1 and L2 are connected to two lines of an AC voltage. Such AC voltage is typically 115 volts; however, trigger circuit 10 can be designated to operate on other AC input voltages. When switch S1 is in position 1 as shown in FIG. 1, capacitor C1 charges to a voltage determined by the ratio of resistors R1 and R2. When switch S1 is activated to position 2, the voltage across charge storage device or capacitor C1 is applied to the first terminal of 4-layer diode or diac DI1. The second terminal of diac DI1 is connected to the collector of three terminal switching device or transistor Q1. Transistor Q1 has a high enough collector to emitter voltage rating such that no conduction thereof occurs unless the base is driven positive relative to the emitter.

The base voltage necessary to cause transistor Q1 to conduct is supplied through a network comprising resistor R4, Zener diodes ZD1 and ZD2, and capacitor C2. The action of this network is such that the base of transistor Q1 is driven positive only after input terminal L1 is more positive than input terminal L2. This is due to the Zener voltage of two terminal switching device or diode ZD1. The voltage drive to the base of transistor Q1 is essentially terminated after L1 is more positive than L2 by the sum of the Zener voltages of diodes ZD1 and ZD2.

FIGS. 2 and 3 are waveform diagrams explanatory of the operation of trigger circuit 10 of FIG. 1. In FIG. 2, the AC voltage on input terminal L1 is represented by a sinusoidal wave pattern labelled L1 while the voltage on input terminal L2 is represented by the horizontal wave pattern labelled L2. Further, the Zener voltage of diode ZD1 is represented by vertical line OA while the zener voltage of diode ZD2 is represented by vertical line AB. The ordinate of FIG. 3 is the output voltage of capacitor C2 applied to the base of transistor Q1. Time t1 designates the time of zero-crossing of waveform L1 over L2. In FIG. 3, at time t1 of the positive half-cycle, the input voltage at terminal L1 becomes more positive than the input voltage at terminal L2; during time interval t1 to t2 the voltage at input terminal L1 is more positive than the voltage at input terminal L2 by less than the Zener voltage of diode ZD1; during time interval t2 to t3 the voltage at input terminal L1 is more positive than the voltage at input terminal L2 by less than the sum of the Zener voltages of diodes ZD1 and ZD2 but greater than the Zener voltage of diode ZD1; at time t3 the voltage applied by capacitor C2 to the base of transistor Q1 is maximum. During the time interval t1 to t2, the voltage applied by capacitor C2 to the base of transistor Q1 is zero; during the time interval t2 to t3, the applied voltage gradually rises; at time t3 the applied voltage is a maximum; and during the time interval t3 to t4, the applied voltage gradually diminishes back to zero.

By suitably selecting the Zener voltages of diodes ZD1 and ZD2, it is thus possible to start the base drive to transistor Q1 only after the voltage at input terminal L1 is more positive than that at input terminal L2 by a sufficient margin to permit silicon controlled rectifier SCR1 to trigger and latch itself in reliably.

The action of Zener diode ZD2 limits the time during which the base of transistor Q1 is driven to near the zero-crossing point of the input voltage wave pattern so that approximately half-cycle of power is delivered to output load terminals L3 and L4.

Regardless of the time during full-cycle that switch S1 is activated from position 1 to position 2, capacitor C1 can only discharge through diac DI1 and through transistor Q1 into the input gate terminal of three terminal switching device or silicon controlled rectifier SCR1 during the time interval that the base of transistor Q1 is driven as described above.

During successive half-cycles of the input AC voltage, the depleted charge on capacitor C1 is built up through resistor R3 if switch S1 is held activated in position 2. When the breakover voltage of diac DI1 is reached after a number of cycles of the input AC voltage, then silicon controlled rectifier SCR1 is again triggered for only a half-cycle of the input AC voltage. By suitable selection of the values or parameters of resistors R1, R2, R3 and capacitor C1, silicon controlled rectifier SCR1 can be caused to deliver a timed train of drive pulses to output load terminals L3 and L4, each drive pulse being approximately one-half cycle long and at intervals of less than a second to many seconds. Resistor R5 permits bypassing of transistor Q1 base leakage current while resistor R6 permits bypassing of silicon controlled rectifier SCR1 leakage current.

FIG. 4 is a circuit diagram of silicon controlled rectifier trigger circuit 20 according to the present invention. Trigger circuit 20 is similar to trigger current 10 except that it further comprises adjustable potentiometer R8. In this case, the output load activation period can be selectively adjusted by varying the wiper arm position of potentiometer R8.

FIG. 5 is a circuit diagram of silicon controlled rectifier trigger circuit 30 according to the present invention. Trigger circuit 30 is similiar to trigger circuits 10 and 20 except that it does not include a diac nor an adjustable potentiometer. The elements of trigger circuit 30 and their recommended parameters or values are as follows:

Trigger Circuit 30 is advantageously utilized to provide one and only one pulse per switch S1 activation, i.e. no repeat function. In other words, trigger circuit 30 provides a single drive pulse on a non-repeating basis to output load terminals L3 and L4 whenever switch S1 is activated from the closed state, position 1, to the open state. While switch S1 is in the closed state, the base of transistor Q1 is held at zero volts relative to the emmitter and therefore transistor Q1 does not conduct. The charge on capacitor C1 builds up gradually over several cycles of the input AC voltage. Such buildup time is determined by the values of resistors R1 and R2, while the final voltage to which capacitor C1 is charged is specifically determined by the ratio of resistors R1 and R2. Once switch S1, which is normally closed, is opened then the base of transistor Q1 is driven by a pulse derived in the manner heretofore described in detail. When transistor Q1 conducts, the charge on capacitor C1 is passed to the input gate of silicon controlled rectifier SCR1 whereupon SCR1 fires for one-half cycle of the input AC voltage. The values of resistors R1 and R2 are chosen such that while switch S1 is held open, insufficient charge passes to capacitor C1 to re-trigger SCR1. However, the charge passed to capacitor C1 is exhausted everytime the base of transistor Q1 is pulsed. This silicon controlled rectifier SCR1 fires once and only once every time switch S1 is activated or opened.

FIG. 6 is a circuit diagram of silicon controlled rectifier trigger circuit 40 according to the present invention. Trigger circuit 40 is similiar to trigger circuit 30 except that it has extra elements as reflected by the following:

Trigger circuit 40 is advantageously utilized to provide two drive pulses to output load terminals L3 and L4 per activation of switch S1. The first drive or input gate pulse to silicon controlled rectifier SCR1 is derived from capacitor C1 which, in conjunction with the triggering circuitry comprising resistor R3, capacitor C3, and zener diodes ZD1 and ZD2, provides a first actuation of the load connected between terminals L3 and L4 in the manner previously described in connection with the earlier embodiments. In this circuit 40, diode D2 and capacitor C2 effect accumulation of charge on capacitor C2 and transistor Q4 thereby permitting the charge on capacitor C2 to be passed to silicon controlled rectifier SCR1 and a one-shot multivibrator formed by transistors Q2 and Q3, to perform a second actuation of rectifier SCR1. At the trailing edge of the first gate pulse appearing at the gate of silicon controlled rectifier SCR1, capacitor C5 triggers the one-shot multivibrator circuit. See FIG. 7, which is a waveform diagram explanatory of the operation of trigger circuit 40 and wherein point T illustrates the first input gate pulse trailing edge. The combination of capacitor C6 and resistor R10 determines the pulse output duration of one-shot multivibrator Q2, Q3 and their component values are so selected that the length of such output pulse is sufficient for formation of the second trigger pulse applied to silicon controlled rectifier SCR1. With the suggested component values recited above, and a line frequency of 60 Hz., the multivibrator output pulse duration exceeds 9 milliseconds.

While the one-shot multivibrator is active--i.e. after it has been triggered by discharge of capacitor C5--the base of transistor Q4 is connected to relative ground (terminal L2) through transistor Q2, and transistor Q4 becomes conductive. The charge stored in capacitor C2 is accordingly available at the collector of transistor Q1 so that when Q1 is activated, a trigger pulse of the charge stored in capacitor C2 is applied to the gate of silicon controlled rectifier SCR1 to fire it a second time. Transistor Q1 is activated in the same manner as previously described--in conjunction with resistor R3, capacitor C3, and zener diodes ZD1 and ZD2--at a given time following the zero crossing of A.C. voltage source lead L1 into the positive zone. Resistors R1 and R2 are so selected to ensure that capacitors C1 and C2 do not accumulate sufficient charge during any single cycle of the A.C. supply to permit triggering of silicon controlled rectifier SCR1. By suitable selection of the values of resistors R1 and R2, the precise time required to charge capacitors C1 and C2 to a sufficient level for triggering of rectifier SCR1 can be predetermined. At the same time, each triggering of SCR1 should dissipate substantially all of the charge stored in the respective capacitor C1 or C2. Thus, silicon controlled rectifier SCR1 cannot again be triggered until switch S1 is released (or returned to its first position), thereby effectively grounding the base of transistor Q1 and permitting the charge to build up on capacitors C1 and C2.

As in the earlier-described embodiments, capacitor C3 is utilized in conjunction with resistor R3 and zener diodes ZD1 and ZD2 to apply a shaped voltage pulse to the base of transistor Q1 as illustrated in FIGS. 2 and 3. Resistor R6 and capacitor C4 provide transient protection to silicon controlled rectifier SCR1, the main function of this series combination being to prevent false triggering of rectifier SCR1 by the high rate of voltage change applied to its anode when the circuit 40 happens to be turned on at the positive peak voltage of the A.C. supply. During operation of the unit 40, the capacitor C4 and resistor R6 combination further compensates for the highly inductive nature of the load by ensuring that silicon controlled rectifier SCR1 turns off cleanly.

While the arrangement according to the present invention has been described in terms of specific illustrative embodiments, it will be apparent to those skilled in the art that many modifications are possible within the spirit and scope of the disclosed principle.