Cathode Ray Tube Apparatus

This invention relates to a shadow-mask color cathode ray tube apparatus (which is called hereinafter a CRT apparatus), and more specifically to a color character display in which good convergence correction is provided following up deflections of electron beams.

The convergence correction in conventional cathode ray tube (which is called hereinafter a CRT) apparatus have obtained the desired convergence correcting magnetic field by flowing respectively the horizontal or vertical convergence coil with a current proportional to a parabolic waveform obtained by integrating the horizontal deflecting current or the vertical deflecting current with respect to time respectively. In such apparatus uniform convergence correction is only effected over the entire picture surface, and there have been the disadvantages that it is very difficult to effect the correction with a high accuracy over the entire picture surface and so on.

The present invention has been made in order to eliminate the prior art disadvantages as described above and is arranged to generate signal voltages substantially equal to ae.sub.X.sup.2 and bee.sub.Y.sup.2 (where a and b are variable constants or constants individually variable in accordance with the polarity of e.sub.X and e.sub.Y) from an X deflecting signal e.sub.X and a Y deflecting signal e.sub.Y, compare these signal voltages with a reference voltage e.sub.CX or e.sub.CY separately generated thereby to partition a picture surface of a CRT into a central portion and a peripheral portion (a left/right and an upper/lower end), generate different adjustable correction signal voltages for the central and peripheral portions thus partitioned and pass convergence currents corresponding to those correction signal voltages through the convergence coil respectively. The picture surface of the CRT is partitioned into the central portion where the convergence is easily effected and the peripheral portion where the convergence is bad and further the partitioned central or peripheral portion is divided into the upper/lower part and the left/right part thereby to make it possible to adjust separately the convergence. Since the temporal characteristics of the deflection is not pertinent, it is possible to be applied to the display of color images resulting from not only the raster scanning but also random scannings and its effect is great.

FIG. 1 is a block diagram illustrating a general construction of a cathode ray apparatus using a shadow-mask CRT;

FIG. 2 is a block diagram illustrating one embodiment of a convergence correction circuit according to the present invention;

FIGS. 3A-3C are explanatory diagrams for explaining the operation, thereof;

FIG. 4 is a diagram illustrating an example of a construction of the polarity discrimination circuit and coefficient circuit portions thereof;

FIG. 5 is a block diagram illustrating another embodiment of the present invention;

FIG. 6 is a diagram illustrating an example of a construction of the coefficient circuit portion thereof; and

FIG. 7 is a block diagram illustrating still another embodiment of the present invention.

In order to facilitate an understanding, an outline of the present invention is described. The present invention is to generate a signal that is ae.sub.X.sup.2 +be.sub.Y.sup.2 from an X and a Y deflecting signal e.sub.X and e.sub.Y supplied to a CRT apparatus and flow a convergence coil with a current proportional to the signal voltage while partitioning a picture surface of a CRT into a central portion and a peripheral portion at a position of ae.sub.X.sup.2 =e.sub.CX in the direction of the X axis and at a position of be.sub.Y.sup.2 =e.sub.CY in the direction of the Y axis and making it possible to adjust the convergence separately on the partitioned central and peripheral portions. In more detail, said picture surface of the CRT is partitioned into the upper and lower sides and the left and right and the convergence on at least said peripheral portion is made possible to be adjusted separately on the upper on lower sides and the left and right.

The construction and operation of the present invention is hereinafter described in detail. FIG. 1 is a structural diagram of a general CRT apparatus. In the FIG. (1) is a CRT, (2) a deflecting coil, (3) a convergence correction element, (4) a circuit for generating deflecting current, and (5) is a convergence correction circuit. (6) and (7) are input terminal for an X and a Y deflecting signal respectively. Assuming that the X and Y deflecting signals are given by signal voltages which are e.sub.X and e.sub.Y, the convergence correction circuit (5) in conventional apparatus generates convergence correction currents on the basis of signal waveforms (which are properly adjusted in accordance with a correction amount for each at R, G and B) proportional to respective time-integral values of the e.sub.X and e.sub.Y. If, in this case, a scanning system of the CRT apparatus is the raster scanning with a constant period, each of the deflecting signal voltages e.sub.X and e.sub.Y becomes a saw-toothed wave having a constant time constant, and therefore the time-integral values of the e.sub.X and e.sub.Y form parabolic waveforms repeated with constant periods. As a result, there is generated a convergence correction current proportional to e.sub.X.sup.2 or e.sub.Y.sup.2. That is, the convergence correction is proportional to the square of a deflection distance and meets the requirements for effecting a first order approximation of the convergence correction. However it is apparent in conventional apparatus that the scanning system is limited to the raster scanning with a constant period and it is difficult to effect the convergence correction over the entire area of the picture surface of the CRT with a high accuracy.

FIG. 2 is a block diagram illustrating one embodiment of a construction of the convergence correction circuit (5) according to the present invention. In the FIG. (8) shows a square law circuit making the deflecting signal voltage e.sub.X an input to provide an output voltage ae.sub.X.sup.2 substantially proportional to e.sub.X.sup.2, (9) a square law circuit making the deflecting signal voltage e.sub.Y an input to provide an output voltage be.sub.Y.sup.2 substantially proportional to e.sub.Y.sup.2, (10) a reference signal generation circuit for generating a reference voltage e.sub.CX for partitioning a central portion and a peripheral portion in the direction of the X axis, (11) a reference signal generation circuit for generating a reference voltage e.sub.CY for partitioning a central portion and a peripheral portion in the direction of the Y axis, (12) a subtraction circuit for providing a signal voltage that is e.sub.DX =ae.sub.X.sup.2 -e.sub.CX from the output ae.sub.X.sup.2 from said square law circuit (8) and the output e.sub.CX from said reference signal generation circuit (10), (13) a subtraction circuit for providing similarly a signal voltage that is e.sub.DY =be.sub.Y.sup.2 -e.sub.CY from the output ae.sub.Y.sup.2 from the square law circuit (9) and the output e.sub.CY from the reference signal generation circuit (11), (14) a polarity discrimination circuit for discriminating the polarity of the signal voltage e.sub.DX and delivering an output e.sub.DX ' only when e.sub.DX .gtoreq.0, (15) a polarity discrimination circuit for discriminating the polarity of the signal voltage e.sub.DY and delivering an output e.sub.DY ' only when e.sub.DY .gtoreq.0, (16) a coefficient circuit for providing a signal voltage K.sub.X .multidot.e.sub.DX ' that is the signal voltage e.sub.DX ' multiplied by a suitable coefficient K.sub.X, (17) a coefficient circuit for providing a signal voltage K.sub.Y .multidot.e.sub.CY ' that is the signal voltage e.sub.DY ' multiplied by a suitable coefficient K.sub.Y, (18) a addition circuit for providing a signal voltage that is e.sub.SX =a.multidot.e.sub.X.sup.2 +K.sub.X .multidot.e.sub.DX ' from the output K.sub.X .multidot.e.sub.DX ' from the coefficient circuit (16) and the output ae.sub.X.sup.2 from the square law circuit (8), (19) an addition circuit for providing a signal voltage that is e.sub.SY =b.multidot.e.sub.Y.sup.2 +K.sub.Y .multidot.e.sub.DY.sup.2 from the output K.sub.Y .multidot.e.sub.DY ' from the coefficient circuit (17) and the output b.multidot.e.sub.Y.sup.2 from the square law circuit (9), (20) an addition circuit for providing a signal voltage that is e.sub.S =e.sub.SX +e.sub.SY from the output e.sub.SX from the addition circuit (18) and the output e.sub.SY from the output e.sub.SY from the addition circuit, (21) an output circuit making the output e.sub.S an input to generate an electric source proportional to the e.sub.S and (22) shows a convergence correction coil forming a part of the convergence correction element (3).

Now assuming that, when the deflecting signal voltages e.sub.X and e.sub.Y are inputted, the picture surface of the CRT is expressed by an X and a Y coordinate and an X and a Y deflected component of an electron beam are proportional to the e.sub.X and e.sub.Y respectively, the output ae.sub.X.sup.2 from the square law circuit (8) with respect to the deflecting signal voltage e.sub.X as shown in FIG. 3(a) is substantially as shown in (b), and by comparing this with the constant value e.sub.CX and separating it according to its magnitude, the central portion and the peripheral portion (the left/right end) in the direction of the X axis can be divided in the direction of the X axis on the picture surface of the CRT as shown in (C). Accordingly, a correction amount that is e.sub.DX ' and acts only on the peripheral portion (the left/right end) can be obtained by discriminating the polarity of the output voltage e.sub.DX :

from the subtraction circuit (12) making the ae.sub.X.sup.2 and e.sub.CX the inputs and adding the e.sub.DX ' to the convergence correction only when e.sub.DX .gtoreq.0. That is, if the polarity discrimination circuit 14 is operated to pass its intact input therethrough only when e.sub.DX .gtoreq.0 and to render the output null when e.sub.2 <0 then the output e.sub.DX ' from that polarity discrimination circuit (14) becomes a signal acting only on the peripheral portion in said direction of the X axis. The coefficient circuit (16) is to multiply the output from the polarity discrimination circuit (14) by the suitable coefficient K.sub.X. Since the K.sub.X .multidot.e.sub.DX ' multiplied here by the coefficient K.sub.X is added to the output ae.sub.X.sup.2 from the square law circuit (8) in the next addition circuit (18), the output e.sub.SX from the addition circuit (18) is

for ae.sub.X.sup.2 .gtoreq.e.sub.CX or

for ae.sub.X.sup.2 <e.sub.CX.

On the other hand, the similar operation is performed with a system making the deflecting signal voltage e.sub.Y an input. Namely, the output be.sub.Y.sup.2 from the squar law circuit (9) is compared with the output voltage e.sub.CY from the reference signation generation circuit 11 and a central portion and a peripheral portion (the upper/lower end) in the direction of the Y axis are divided according to its magnitude. The polarity descrimination circuit (15) discriminates polarity of the output voltage e.sub.DY,

from the subtraction circuit (13) making the output be.sub.Y.sup.2 from the square law circuit and the output e.sub.CY from the reference signal generation circuit (13) the inputs, and passes it therethrough only when e.sub.DY .gtoreq.0, when e.sub.DY <0, the output is rendered null. The multiplication of the suitable coefficient K.sub.Y effected in the next coefficient circuit (17) results in the addition circuit (19) making this signal K.sub.Y .multidot.e.sub.DY ' and the output be.sub.Y.sup.2 from the square law circuit (9) inputs to form its output e.sub.SY,

for be.sub.Y.sup.2 .gtoreq.e.sub.CY or

for be.sub.Y.sup.2 <e.sub.CY.

The addition circuit 20 makes the output e.sub.SX from said addition circuit 18 and the output e.sub.SY from the addition circuit 19 inputs and its output e.sub.S is according to the relationships among the ae.sub.X.sup.2, be.sub.Y.sup.2, e.sub.CX and e.sub.CY as follows: ##EQU1## for ae.sub.X.sup.2 .gtoreq.e.sub.CX and be.sub.Y.sup.2 .gtoreq.e.sub.CY ', ##EQU2## for ae.sub.X.sup.2 .gtoreq.e.sub.CX and be.sub.Y.sup.2 <e.sub.CY ', ##EQU3## for ae.sub.X.sup.2 <e.sub.CX and be.sub.Y.sup.2 .gtoreq.e.sub.CY and ##EQU4## for ae.sub.X.sup.2 <e.sub.CX and be.sub.Y.sup.2 <e.sub.CY. If a current proportional to a voltage that is this e.sub.S passes through the convergence coil (22) through the output circuit (21) then a corrector of the convergence is obtained satisfying the expressions (7), (8) and (9) on the peripheral portion and a correction of the convergence is obtained satisfying the expression (10) on the central portion. Here if values of the e.sub.CX and e.sub.CY and the positive and negative and polarity of the coefficients K.sub.X and K.sub.Y are made variable then the picture surface of the CRT can be partitioned into a central and a peripheral portion as predetermined and only the peripheral portion can be independently adjust. Also as a correction amount at a boundary between the central and peripheral portions is determined by the e.sub.CX and e.sub.CY, no difference in correction amount is caused at the boundary between the central and peripheral portions.

FIG. 4 is a diagram illustrating a concrete embodiment of a circuit portion consisting of the polarity discrimination circuit (14) and the coefficient circuit (18) in said FIG. 2 wherein (23) is a diode; (24) a resistance, (25) a polarity inversion circuit and (26) is a potentiometer. In the Figure, the signal voltage e.sub.DX is half-wave rectified by the diode 23 and only a positive polarity portion e.sub.DX ' thereof is inputted to the coefficient circuit (16). A signal voltage that is the e.sub.DX ' is applied to one end of the potentiometer 26 while a signal voltage that is -e.sub.DX ' is applied to the other end thereof by means of the polarity inversion circuit (25). Therefore an output voltage from the potentiometer 26 may take any value within a range of from the e.sub.DX ' to -e.sub.DX. There is provided the effect equivalent to the value of the coefficient K.sub.X changing at will in a range of -1<K.sub.X <1. Still more, a circuit portion consisting of the polarity discrimination circuit (15) and the coefficient circuit (17) is identical and may use this embodiment.

FIG. 5 is a constructional diagram of another embodiment of the present invention by which the embodiment of FIG. 2 is developed to expand a degree of freedom of the convergence correction. In the FIG. (27) is a half plane discrimination circuit for discriminating the polarity of the deflecting signal voltage e.sub.X to discriminate which of left and right half planes in the direction of the X axis has electron beams lying therein, (28) a half plane discrimination circuit for discriminating the polarity of the deflecting signal voltage e.sub.Y to discriminate which of upper and lower half planes in the direction of the Y axis has the electron beams lying therein, (29) an output lead for delivering an output only when the deflecting signal voltage e.sub.X <0, that is to say, when the electron beams lie in the left half plane, (30) an output lead for delivering an output only when e.sub.X .gtoreq.0, that is, when the election beams lie in the right half plane, (31) an output lead for delivering an output only when the deflecting signal voltage e.sub.Y <0, that is to say, when the electron beams lie in the upper half plane, (32) an output lead for delivering an output only when e.sub.Y .gtoreq.0, that is, when the electron beams lie in the lower half plane, and (33) is a coefficient circuit for multiplying the signal e.sub.DX ' obtained by the polarity discrimination circuit (14) and corresponding to the peripheral portion (the left and right ends) in the direction of the X axis by a coefficient K.sub.X1 or a coefficient X.sub.X2 when the output appears on the output lead (31) or the output lead (32) respectively in accordance with the status of the half plane discrimination circuit (28). (34) is a coefficient circuit for multiplying obtained by the polarity discrimination circuit (40) and corresponding to the peripheral portion (the upper/lower end) in the direction of the Y axis by a coefficient K.sub.Y1 or a coefficient K.sub.Y2 when the output appears on the output lead (31) or the output lead (32) respectively in accordance with the status of the half plane discrimination circuit (28). In the embodiment of the convergence circuit according to the construction of FIG. 5 the adjustment on the peripheral portion in the embodiment of FIG. 2 is effected independently on the upper/lower side and the left/right. Namely according to the conditions ae.sub.X.sup.2 .gtoreq.e.sub.CX and be.sub.Y.sup.2 .gtoreq.e.sub.CY or to the polarity of the deflecting signal voltages e.sub.X and e.sub.Y when the electron beams lies on the peripheral portion the output e.sub.S from the addition circuit (20) becomes

for e.sub.X <0 and e.sub.Y <0,

for e.sub.X <0 and e.sub.Y .gtoreq.0,

for e.sub.X .gtoreq.0 and e.sub.Y <0 or

for e.sub.X .gtoreq.0 and e.sub.Y .gtoreq.0.

If a current proportional to this signal voltage e.sub.S flows through the convergence coil (22) through the output circuit coil (21) and if the positive and negative and magnitude of the coefficients K.sub.X1, K.sub.X2, K.sub.Y1 and K.sub.Y2 are made variable then the upper/lower and left/right convergence adjustments can be independently effected on the peripheral portion of the CRT picture surface.

For the same reasons as described above no difference is caused at the boundary between the central and peripheral portions.

FIG. 6 shows an example of the concrete construction of the coefficient circuit (33) in this case.

In the FIG. (26a) and (26b) show potentiometers and (35a) and (35b) show analog gates. This circuit has different coefficients K.sub.X1 and K.sub.X2 set by the potentiometers (26a) and (26b), and either one of the analog gates (35a) and (35b) is selected to be enabled with the output from the half plane discrimination circuit (27) and inputted to the addition circuit (18). Still also the coefficient circuit (34) may use a circuit of that construction.

FIG. 7 is a diagram illustrating another further developed embodiment of the present invention which makes it possible to adjust the convergence adjustment independently on the upper/lower side and the left/right not only on the peripheral portion as in the embodiment of FIG. 5 but also on the central CRT portion. In FIG. (36) and (37) are polarity discriminating circuits and (8a), (8b) and (9a) and (9b) are square law circuits capable of adjusting the characteristics. The polarity of input signals e.sub.X and e.sub.Y are discriminated by the polarity discrimination circuits (36) and (37) and the input signals e.sub.x and e.sub.y when negative are inputted to the square law circuits (8a) and (9a) respectively while the input signals e.sub.X and e.sub.Y when positive are inputted to the square law circuits (8b) and (9b) respectively. Outputs from the square law circuits (8a), (8b), (9a) and (9b) are a.sub.1 e.sub.X.sup.2 (-), a.sub.2 e.sub.X.sup.2 (+), b.sub.1 e.sub.Y.sup.2 (-) and b.sub.2 e.sub.Y.sup.2 (+), respectively.

Here a.sub.1, a.sub.2, b.sub.1 and b.sub.2 indicate the characteristics of the square law circuits (8a), (8b), (9a) and (9b) respectively.

A system with the square law circuit (8), the reference signal generation circuit (10), the subtraction circuit (12), the polarity discrimination circuit (14), the coefficient circuit (16) and the addition circuit (18) performs the similar operation as in the embodiment of FIG. 2, and e.sub.SX1 is outputted at the output of the addition circuit (18a) while e.sub.SX2 is outputted at the output of the addition circuit (18b). A system with the square law circuit (9), the reference signal generation circuit (11), the subtraction circuit (13), the polarity discrimination circuit (15), the coefficient circuit (17) and the addition circuit (19) performs also the similar operation as in the embodiment of FIG. 2 and e.sub.SY1 is outputted at the output of the addition circuit (19a) while e.sub.SY2 is outputted at the output of the addition circuit (19b). Those outputs e.sub.SX1, e.sub.SX2, e.sub.SY1 and e.sub.SY2 become convergence correction signal voltages for the left/right and the upper/lower half planes of the CRT picture surface respectively. (38) is an addition circuit for adding those signal voltages. On the central portion of the CRT picture surface, or for

An output e.sub.S from the addition circuit 38 is according to the polarity of the e.sub.X and e.sub.Y as follows:

for e.sub.X <0 and e.sub.Y <0,

for e.sub.X <0 and e.sub.Y .gtoreq.0,

for e.sub.X .gtoreq.0 and e.sub.Y <0, or

for e.sub.X .gtoreq.0 and e.sub.Y .gtoreq.0.

That is, even on the central portion of the CRT picture surface given by the expression (15) the left/right and upper/lower convergence corrections can be separately effected by changing the characteristics of the square law circuits (8a), (8b) and (9a), (9b). On the peripheral portion of the CRT picture surface or for

the convergence adjustment can be, of course, effected dependently on the left/right and upper/lower side by changing the positive and negative and magnitude of the coefficients K.sub.X1, K.sub.X2, K.sub.Y1 and K.sub.Y2 of the coefficient circuits (16a), (16b), (17a) and (17b) as in the embodiment of FIG. 5. Also the boundary between the central and peripheral portions does not cause a difference in amount of convergence correction for the same reason as described above. Further, by varying values of the output voltages e.sub.CX1, e.sub.CX2 and e.sub.CY1, e.sub.CY2 from the reference signal generation circuits (10a), (10b) and (11a), (11b), a position of the boundary between the central and peripheral portions may be also displaced freely.

The expression of the square law used in the embodiments as described above means what has the characteristic substantially approximating the square law but not the strict square law.