Solid State Current Sensing Circuit

This invention relates, in general, to current sensing circuits, and more particularly, to a solid state current sensing circuit.

It is often desirable to sense current flowing in a circuit for various reasons. One such reason may be to monitor the sensed current to prevent current from exceeding a certain limit. This would be especially true in power supply circuits wherein it is desired to limit the output current from the power supply. Limiting the output current of the power supply can prevent damage to circuitry being powered by the power supply.

In the past, at least one of the techniques used to sense output current was to insert a resistor in series with the output line of a power supply, for example, and then to measure the voltage drop developed across the known resistor. The disadvantage of this type of an arrangement is that as the current flow through the resistor increases the output voltage decreases because of the voltage being dropped across the resistor.

Accordingly, it is an object of the present invention to provide a solid state current sensing circuit which does not cause a varying voltage drop.

Another object of the present invention is to provide an improved current sensing circuit which is independent of temperature.

A further object of the present invention is to provide a solid state current sensing and limit circuit which is substantially free from process variations.

Yet another object of the present invention is to provide a solid state current sensing circuit which can be implemented as a CMOS circuit to sense current supplied by bipolar transistors.

In carrying out the above and other objects of the invention in one form, there is provided a solid state current sensing circuit. The solid state current sensing circuit has a first and a second transistor each having integral means for sampling a portion of current being carried by the transistor. Means for creating an unbalance in the current carried by one of the transistors is coupled to the second transistor so that the sampled current from the second transistor will be less than the current sampled from the first transistor. A current mirror is coupled to the means for sampling and provides an indication of when the unbalance in current reaches a predetermined level. The output of the current mirror is used to controllably limit the current supplied by the first and second transistors.

FIG. 1 illustrates a solid state current sensing circuit of the present invention;

FIG. 2 is a plan view of a lateral collector such as used in the circuit shown in FIG. 1; and

FIG. 3 illustrates in schematic form a simplified control circuit for the circuit of FIG. 1.

The exemplification set out herein illustrates a preferred embodiment of the invention, in one form thereof, and such exemplification is not to be considered as limiting in any manner.

The schematic of FIG. 1 shows field effect transistors as well as PNP transistors which can all be integrated on the same silicon chip. PNP transistors 11 and 12 are used to provide an output voltage, V.sub.out. Transistor 11 is illustrated as being a PNP transistor having its emitter coupled to a voltage terminal 14 and having its base electrode connected to a control circuit 10. Transistor 11 is shown as having two collectors 16 and 17. Collector 16 is shown as being the main current carrying collector which provides the output voltage whereas collector 17 is shown connected to a node 24. Collector 16 is a vertical collector whereas collector 17 is a long lateral collector and carries a fraction of the current carried by collector 16. In the preferred embodiment, where collector 17 is a long lateral collector, it would have its own emitter which would in turn be connected to the main emitter. The emitter for transistor 17 is therefore illustrated in the schematic as being a single emitter. The base of transistor 11 is also connected to the base of transistor 12.

Transistor 12 is illustrated as having its emitter coupled to voltage terminal 14 by a resistor 13. Transistor 12 has a collector 19 which is connected to an N-channel field effect transistor 21, and has a collector 18 which is illustrated as being connected to collector 16 and to output V.sub.out. Collector 19 is identical to collector 17 in that it is a long lateral collector having an associated emitter which is electrically connected to an emitter for collector 18. The portion of transistor 12 having a collector 18 is a verticl transistor, also known as a substrate transistor. It should be noted that collectors 16 and 18 are, in the preferred embodiment, the substrate of the silicon chip containing the circuitry illustrated in FIG. 1.

N-channel transistor 21 has its gate electrode connected to its drain electrode, and has its source electrode connected to voltage terminal 23 which is illustrated as ground. The gate electrode of transistor 21 is also connected to the gate electrode of an N-channel transistor 22. Transistor 22 has its drain connected to node 24 and has its source connected to voltage terminal 23. Transistors 21 and 22 form a current mirror. In a preferred embodiment, transistor 22 is twice as large as transistor 21. Node 24 is connected to the gate and drain of an N-channel transistor 26. Transistor 26 has its source connected to voltage terminal 23. Node 24 is also connected to the gate electrode of an N-channel transistor 27. The drain of transistor 27 is connected to control circuit 10, and its source is connected to voltage terminal 23.

Control circuit 10 provides an output to the base electrodes of transistors 11 and 12. Control circuit 10 establishes a reference as well as serving as a current control to establish the output V.sub.out. It will be noted that the circuitry illustrated in FIG. 1 can serve as a power supply, lamp driver, relay driver, or any other type of drive circuit. The control circuitry 10 establishes the output voltage, and as long as the load connected to the power supply draws a low amount of current then collectors 17 and 19 will also conduct a low amount of current. This low current will flow through transistors 22 and 21 respectively. As transistor 22 conducts low current levels the voltage at node 24 will be a low level and will not enable transistors 26 and 27. As current flow through transistors 11 and 12 increases it will be noted that transistor 11 will commence to conduct more current since resistor 13 will start to affect, to a greater extent, the current flow through transistor 12 thereby causing transistor 12 to conduct less current than transistor 11. Since collectors 17 and 19 are the same physical size, less current will flow through collector 19 than through collector 17 because transistor 12 is carrying the lesser current. When the current through collector 17 reaches twice as much as the current through collector 19 then the current mirror formed by transistors 21 and 22 is satisfied since transistor 22 is twice as large, or can conduct twice as much current, as transistor 21. However, as the current flow in collector 17 increases beyond twice as much as the current flow in collector 19, the voltage at node 24 will increase since transistor 22 will become saturated and its gate voltage remains fixed. Excess current at node 24 will be shunted to voltage terminal 23 by transistor 26. As the voltage at node 24 increases, transistor 26 and transistor 27 will be enabled thereby modifying the output from control circuitry 10 which will react to limit the output current provided by transistors 11 and 12.

As mentioned hereinbefore, in the preferred embodiment, the lateral collectors 17 and 19 are formed, as illustrated in FIG. 2, in a long narrow U configuration 45 with each having its associated emitter in the configuration of a narrow emitter finger 46 positioned inside the U configuration 45. This narrow emitter will have a metal contact 47 at one end thereby avoiding a metal contact over the narrow emitter portion. For Transistor 12, area 47 serves as the emitter area associated with collector 18, while for transistor 11 it also serves as the contact area to the main emitter. Contact to U configured collector 45 is made at its bight portion 48.

The following differential equation was developed for the voltage drop found along the long finger emitter 45 of FIG. 2:

where V is the voltage applied to the emitter, X is the distance along the emitter, .rho..sub.s is the sheet rho of the emitter finger, J.sub.s is the saturation current density of the long emitter finger, and exp is the well known designation used for exponent.

For a very long emitter finger, the current distribution is given by ##EQU1## where J(x) is the current density of the emitter finger at a point X, J.sub.o is the initial current density when X equals 0, and .beta. equals the well known quantity q.div.kT. To obtain the total current, I.sub.total, emitted by the emitter finger, the above equation is integrated to obtain ##EQU2## where W is the width of the emitter finger.

Due to the size ratios of transistors 21 and 22 it was determined that it was preferred to have the current in the two lateral collectors 17 and 19 be a ratio of M, or in other words, it was found to be preferrable to have the current densities in the two lateral emitters differ by a factor of M. When X approaches infinity, we have

where I.sub.12 is the total current in the emitter finger of transistor 12; W is the width of the emitter finger, and I.sub.11 is the total current in the emitter finger of transistor 11. By substituting the equation (2) into equation (3) it can be shown that

However, we must not forget the effects of resistor 13, which are ##EQU3## where R is the resistance of resistor 13, J.sub.11 is the current density of emitter area 47 for transistor 11, and J.sub.12 is the current density of emitter area 47 for transistor 12. Note that the current in the long emitter finger is being neglected since it is assumed to be much smaller than the current in area 47 and therefore would have a negligible effect on the results of the equation.

This equation (5) can be written as ##EQU4## However, ##EQU5## where L.sub.12 is the emitter pad 47 periphery for transistor 12 and .delta..sub.eff is the effective emitter width of the emitter pad 47 for transistor 12. So now the value for resistor 13 can be obtained from the equation ##EQU6## Note that if the temperature coefficient of the resistor is made equal to that of the quantity on the right the current limit can be made independent of temperature.

FIG. 3 shows in schematic form a simplified control circuitry 10 which can be used as the control circuit of FIG. 1. Line 30 in FIG. 3 represents the line connected to the drain of transistor 27 (FIG. 1). Line 30 is connected to the drain of a P-channel transistor 34 and the drain of an N-channel transistor 31. Transistor 34 forms a current mirror with a P-channel transistor 35 wherein both have their sources connected to voltage terminal 14. Transistor 34 has its gate connected to its drain which is also connected to the gate of transistor 35. Transistor 35 has its drain connected to a node 37. Transistor 31 has its source connected to the source of a transistor 32 and to a current source 33. Transistor 32 has its drain connected to node 37. Transistors 31, 32, 34 and 35 form a differential amplifier. Transistor 32 has its gate electrode connected to a reference circuit which helps establish the output voltage provided by the power supply of FIG. 1. Transistor 31 has its gate electrode connected to a feedback input f.b. The feedback can be derived from a resistive voltage divider network connected from collector 16 to ground terminal 23. Node 37 is connected to the gate electrode of a P-channel transistor 38 which has its drain electrode connected to the drain electrode of an N-channel transistor 39. Transistor 39 has its gate electrode connected to its drain and has its source connected to ground terminal 23. Transistor 38 has its source electrode connected to line 40 which is also connected to a resistor 41. The other end of resistor 41 is connected to voltage terminal 14. Line 40 is coupled to the base electrodes of transistors 11 and 12.