Sampling Filter

The present invention relates to sampling filters. These filters are similar to digital filters because they use a sampling process, but they differ therefrom because the samples used are not digitized. This similarity permits the use of methods of synthesis used in the computation of digital filters. Such filters are particularly useful in automatic telephone switches of the temporal type.

The manufacture of such filters is known and a description thereof can be found in the article "Transverse Filtering Using Charge-Transfer Devices" published by Dennis D. BUSS et al. in volume SC8, No. 2, of April 1973 in the review "IEEE Journal of Solid-State Circuits".

The charge-transfer devices used in these filters are also known. We will name them according to the notation CCD in English-language documents. A detailed description thereof will be found in the article "Charge-Coupled Devices" published by Gilbert. F. AMELIO in volume 230, No. 2 February 1974 of the review "Scientific American".

The sampling used disturbs the response curve of the filter and causes a phenomena known for example under the name "spectrum folding" or "ghosts". In order to minimize this phenomena, the filter most often used is a circuit of the "sample hold" type which allows a staircase output signal to be obtained whose spectrum is less extended than that of a signal composed of narrow separate pulses.

It is nevertheless often necessary to complete the action of such a filter by analog filtering more or less depending on the results desired. This is particularly the case in telephony where complementary filter lobe suppressors are used when a very considerable attenuation of the spurious signals outside the band is required.

The invention aims at reducing to a minimum this analog filtering, or even suppressing it.

In order to accomplish this a device is used which we will call "first order interpolator and which is sometimes known under the name of first order sample and hold circuit" in contrast to the output circuit mentioned above, which is in this case named "zero order sample and hold circuit".

The above and other objects, features and advantages of the present invention will become apparent from the following description, given solely by way of non-limiting illustration, when taken in conjunction with the accompanying drawings.

FIG. 1 shows a filter using a charge-transfer device according to the invention.

FIG. 2 is a timing diagram of the signals present at different points on the filter.

The filter shown in FIG. 1 comprises a charge-transfer device weighted in a known way to achieve a definite filtering function and provided with subsidiary devices such as a transfer signal generator and a zero order sample and hold. This CCD and its subsidiary circuits are contained in a box 101 which receives the signal to be filtered E and a clock signal H.sub.1. The signal thus filtered in a known way and containing spurious signals leaves at output S.sub.1 and is applied through a resistor R.sub.1 to a first switching transistor T.sub.1, of the field-effect type in this embodiment, and through a resistor R.sub.2 to a second switching transistor T.sub.2.

This signal S.sub.1 is shown in FIG. 2 in company with different clock signals used in the filter. It is composed of steps whose beginning is in phase with the trailing edge of the pulses of clock signal H.sub.1. This stepped form is characteristic of the output zero order sample and hold circuit of box 101.

To the control electrode of T.sub.1 there is applied a clock signal H.sub.2 similar to H.sub.1 and shown in FIG. 2, but in which the leading edge of the pulses is shifted by a time .tau. in relation to the trailing edge of the pulses of H.sub.1 ; the trailing edge of the pulses of H.sub.2 coinciding in this example with the leading edge of the pulses of H.sub.1 and in any case not having to extend into the transitions between the steps. In this way T.sub.1 is momentarily closed for short periods by these pulses, which allows signal S.sub.1 to be transmitted to the - input of a first differential amplifier A.sub.1 whose + input is connected to ground by means of a resistor R.sub.3. This amplifier is coupled with negative feedback by means of a resistor R.sub.4 between its output and the input of T.sub.1 and a capacitor C.sub.1 between this output and its negative input. By giving for example to C.sub.1 a value of 200 pF and to R.sub.4 and R.sub. 1 a common value of 4 k.OMEGA., signal -S.sub.1 is thus stored in this capacitor with a delay equal to .tau.. In fact C.sub.1 is charged when T.sub.1 is closed and remains charged when T.sub.1 is open.

The output signal of A.sub.1, this representing -S.sub.1 with a delay .tau. is applied through a resistor R.sub.5 to T.sub.2 in parallel with S.sub.1 which arrives through R.sub.2. T.sub.2 receives on its control electrode a clock signal H.sub.3 shown in FIG. 2, similar to H.sub.1 and H.sub.2, but whose pulses are inserted between those of H.sub.1 and of H.sub.2 without overlapping either of them. For the sake of convenience there is shown in the figure the extreme situations where the edges of H.sub.1, H.sub.2 and H.sub.3 coincide, but they can be separated from each other provided the widths of the pulses do not overlap.

When T.sub.2 is opened under the influence of H.sub.3, the outputs of R.sub.2 and R.sub.5 are electrically connected to the - input of a second amplifier A.sub.2 whose + input is connected to ground through a third switching transistor T.sub.3, a resistor R.sub.6 and a capacitor C.sub.2. T.sub.3 receives H.sub.3 on its control electrode and serves, with R.sub.6 and C.sub.2, to compensate for a spurious clock skip due to the sampling. A.sub.2 is coupled with negative feedback by means of a resistor R.sub.7 between its output and the input of T.sub.2 and by means of a capacitor C.sub.3 between its output and its negative input. By giving for example to C.sub.3 a value of 220 pF, to R.sub.7 a value of 8.25 k.OMEGA. and to R.sub.2 and R.sub.5 a value of 2 k.OMEGA., the signals transmitted by R.sub.2 and R.sub.5 are added, the result of this addition is multiplied by a factor substantially equal to 4 and the result of these operations is stored in C.sub.3. As the signal transmitted by R.sub.5 is equal to the signal transmitted by R.sub.2 but delayed by a time .tau. and since the operation effected by A.sub.2 is effected during the time .tau. which follows the end of each step of signal S.sub.1, there is obtained--except for a multiplication factor and a delay--at the output of A.sub.2 a signal representing the difference between the signal S.sub.1 (t) and signal S.sub.1 (t-T), T representing the period of clock H.sub.1.

To obtain a first order interpolator, after obtaining this difference it is necessary to proceed with integration of the signal obtained.

For that the signal at the output of A.sub.2 is applied through a resistor R.sub.8 to the negative input of an amplifier A.sub.3 coupled with negative feedback between its output and this input through a resistor R.sub.9 and a capacitor C.sub.4. The + input of A.sub.3 is connected to ground through a resistor R.sub.10. By giving to R.sub.8 a value of 4.02 k.OMEGA., to R.sub.9 a value of 40.2 k.OMEGA., to C.sub.3 a value of 133 nF, and to R.sub.10 a value of 4 k.OMEGA., this stage behaves like an integrator and forms with the preceding stages a first order interpolator which considerably minimizes the out-of-band signals contained in signal S.sub.1.

In relation to complementary filtering of the type comprising coils, such a circuit has the advantage of being very easily integratable and delivers at the output S of A.sub.3 an output signal whose out-of-band characteristics are particularly good.

Another embodiment of such a filter consists in achieving the subtraction operation obtained in the above example with A.sub.1 and A.sub.2, in the CCD itself. In fact a CCD operates by weighting on a set of n successive samples of the signal to be filtered s(t) to s(t-(n-1)T) by multiplying the value of these samples by a set of n weights a.sub.1 to a.sub.n calculated in accordance with the known techniques of the synthesis of digital filters.

Thus signal S.sub.1 (t) is given by:

Signal S.sub.1 (t-T) is given by:

The difference signal is given by:

ti S.sub.1 (t)-S.sub.1 (t-T)=a.sub.1 .multidot.s(t)+(a.sub.2 -a.sub.1).multidot.s(t-T)+(a.sub.3 -a.sub.2).multidot.s(t-2T)+. . . +(a.sub.n -a.sub.n-1).multidot.s(t-(n-1)T)-a.sub.n .multidot.s(t-nT).

It can be seen that the assembly composed of the CCD contained in box 101 and amplifiers A.sub.1 and A.sub.2 may be replaced with their subsidiary members by another CCD comprising an additional cell and characterized by an assembly of n+1 weights defined by: a.sub.1, a.sub.2 -a.sub.1, a.sub.3 -a.sub.2, . . . , a.sub.n -a.sub.n-1, -a.sub.n. This CCD will therefore have one more weighting cell than that of the CCD used in the circuit of FIG. 1 in the amount of material, this single cell will replace the two amplifiers A.sub.1 and A.sub.2 and their subsidiary members. The integrator, formed by amplifier A.sub.3 and its subsidiary members, will remain nevertheless necessary.

The choice between these two embodiments will depend on the difficulties of construction of the CCDs. In fact it is known that one of the difficulties met in the construction of these devices is the accuracy required in the weighting cells. The greater the range of weightings, the more difficult it is to obtain accuracy for the low weightings. This range is different in the two embodiments since the weighting assemblies are different. These weightings themselves depend on the filtering patterns to be obtained and the choice is thus a specific case according to the desired pattern.

It is apparent that within the scope of the invention, modifications and different arrangements can be made other than is here disclosed. The present disclosure is merely illustrative with the invention comprehending all variations thereof.